int main() {
int i;
GENLIB_DEF_LOFIG("dpt_alu32");
GENLIB_LOCON("A[31:0]" , IN , "A[31:0]");
GENLIB_LOCON("B[31:0]" , IN , "B[31:0]");
GENLIB_LOCON("Ctrl[2:0]", IN , "Ctrl[2:0]");
GENLIB_LOCON("Res[31:0]", OUT, "Res[31:0]");
GENLIB_LOCON("Zero" , OUT, "Zero");
GENLIB_LOCON("Vdd" , IN, "Vdd");
GENLIB_LOCON("Vss" , IN, "Vss");
/*
ALU1 pins: A, B, Cin, Less, Binv, Op, Res, Cout, Set, Vdd, Vss
*/
// ALU[0]
GENLIB_LOINS("dpt_alu1", "alu_0",
"A[0]", "B[0]",
"Ctrl[2]", "Set[31]",
"Ctrl[2]", "Ctrl[1:0]",
"Res_i[0]", "Cout[0]",
"Set[0]", POWER);
// ALU[1..30]
for(i = 1; i < 31; i++) {
GENLIB_LOINS("dpt_alu1", GENLIB_NAME("alu_%d", i ),
GENLIB_ELM("A", i), // A
GENLIB_ELM("B", i), // B
GENLIB_ELM("Cout", i-1), // Cin
"Vss", // Less
"Ctrl[2]", // Binv
"Ctrl[1:0]", // Op
GENLIB_ELM("Res_i", i), // Res
GENLIB_ELM("Cout", i), // Cout
GENLIB_ELM("Set", i), // Set
POWER);
}
// ALU[31]
GENLIB_LOINS("dpt_alu1", "alu_31",
"A[31]", "B[31]",
"Cout[30]", "Vss",
"Ctrl[2]", "Ctrl[1:0]",
"Res_i[31]", "Cout[31]",
"Set[31]", POWER);
// Zero detector circuit
GENLIB_LOINS("dpt_alu32_zero", "alu_zero", "Res_i[31:0]", "Zero", POWER);
// Buffers for result signals
for(i = 0; i < 32; i++) {
GENLIB_LOINS("dpt_buffer", GENLIB_NAME("res_buff_%d", i), GENLIB_ELM("Res_i", i), GENLIB_ELM("Res", i), POWER);
}
GENLIB_SAVE_LOFIG();
}
extern int main()
{
long i;
/* Generate all the operators required for the register file. */
GENLIB_MACRO (DPGEN_INV , "model_inv_x8", F_PLACE, 4, 8);
GENLIB_MACRO (DPGEN_SFF , "model_sff" , F_PLACE, 4);
GENLIB_MACRO (DPGEN_NBUSE, "model_nbuse" , F_PLACE, 4);
/* Generate all the operators required */
GENLIB_MACRO (DPGEN_MUX2 , "model_mux2", F_PLACE, 4, 2);
GENLIB_MACRO (DPGEN_NAND2MASK, "model_nand2mask_0000", F_PLACE, 4,"0b0000");
GENLIB_MACRO (DPGEN_XNOR2MASK, "model_xnor2mask_1111", F_PLACE, 4, "0b1111");
GENLIB_MACRO (DPGEN_NAND2 , "model_nand2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_NOR2MASK , "model_nor2mask_1111", F_PLACE, 4,"0b1111");
GENLIB_MACRO (DPGEN_NMUX2 , "model_nmux2", F_PLACE, 4,2);
GENLIB_MACRO (DPGEN_INV , "model_inv", F_PLACE, 4,1);
GENLIB_MACRO (DPGEN_NOR2 , "model_nor2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_XOR2 , "model_xor2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_XNOR2 , "model_xnor2", F_PLACE, 4, 4); /* 1 ou 4 */
GENLIB_MACRO (DPGEN_SFFT , "model_sfft", F_PLACE, 4); /* 1 ou 4 */
/* Netlist description. */
GENLIB_DEF_LOFIG ("amd2901_dpt");
/* Command for selecting operands R and S.*/
GENLIB_LOCON ("ops_mx[2:0]" , IN , "ops_mx[2:0]");
GENLIB_LOCON ("opr_mx[1:0]" , IN , "opr_mx[1:0]");
/* ALU commands and auxiliary terminals. */
GENLIB_LOCON ("alu_k[4:0]" , IN , "alu_k[4:0]");
GENLIB_LOCON ("alu_cin" , IN , "alu_cin") ;
GENLIB_LOCON ("alu_cout", OUT , "alu_cout") ;
GENLIB_LOCON ("alu_over" , INOUT , "alu_over");
/* RAM, ACCU shifter commands and auxiliary terminals.*/
GENLIB_LOCON ("ram_sh[1:0]" , IN , "ram_sh[1:0]") ;
GENLIB_LOCON ("acc_sh[1:0]" , IN , "acc_sh[1:0]") ;
/* RAM shifter inputs.*/
GENLIB_LOCON ("ram_i_up" , IN , "ram_i_up");
GENLIB_LOCON ("ram_i_down" , IN , "ram_i_down");
/* ACCU shifter inputs.*/
GENLIB_LOCON ("acc_i_up" , IN , "acc_i_up" ) ;
GENLIB_LOCON ("acc_i_down" , IN , "acc_i_down") ;
/* ACCU shifter outputs ("acc_scout" is "acc_q_up").*/
GENLIB_LOCON ("acc_q_down" , OUT , "acc_q_down");
/* Output multiplexer commnand (for X bus).*/
GENLIB_LOCON ("out_mx" , IN , "out_mx");
/* ACCU controls terminals.*/
GENLIB_LOCON ("acc_ck" , IN , "acc_ck" );
GENLIB_LOCON ("acc_wen" , IN , "acc_wen" );
GENLIB_LOCON ("acc_test" , IN , "acc_test" );
GENLIB_LOCON ("acc_scin" , IN , "acc_scin") ; /* Scan-Path input.*/
GENLIB_LOCON ("acc_scout", INOUT ,"acc_scout"); /* Scan-Path output.*/
/* Register file controls terminals.*/
GENLIB_LOCON ("ram_ck[15:0]", IN ,"ram_ck[15:0]") ; /* Register clocks (ck) */
GENLIB_LOCON ("b_w[15:0]" , IN , "b_w[15:0]") ; /* Write enable */
GENLIB_LOCON ("a[15:0]" , IN , "a[15:0]") ; /* Register A address. */
GENLIB_LOCON ("b[15:0]" , IN , "b[15:0]") ; /* Register B address. */
/* Data buses terminals.*/
GENLIB_LOCON ("opr_d[3:0]" , IN ,"opr_d[3:0]");
GENLIB_LOCON ("alu_f[3:0]" , INOUT ,"alu_f[3:0]");
GENLIB_LOCON ("alu_np[3:0]" , OUT ,"alu_np[3:0]");
GENLIB_LOCON ("alu_ng[3:0]" , OUT , "alu_ng[3:0]");
GENLIB_LOCON ("out_x[3:0]" ,OUT , "out_x[3:0]");
/* Power supply connectors. */
GENLIB_LOCON ("vdd", IN , "vdd");
GENLIB_LOCON ("vss", IN , "vss");
/* Register file description. */
for (i = 0; i < 16; i++)
{
/* Register part. */
GENLIB_LOINS ("model_sff", GENLIB_NAME("ram_reg%ld",i),
GENLIB_ELM ("b_w", i),
GENLIB_ELM ("ram_ck" , i),
"ram_d[3:0]",
GENLIB_NAME ("ram_q%ld[3:0]", i),
"vdd", "vss", NULL);
/* Tristate for A output. */
GENLIB_LOINS ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i),
GENLIB_ELM ("a", i),
GENLIB_NAME ("ram_q%ld[3:0]", i),
"ram_nra[3:0]",
"vdd", "vss", NULL);
/* Tristate for B output. */
GENLIB_LOINS ("model_nbuse", GENLIB_NAME("ram_ntsb%ld",i),
GENLIB_ELM ("b", i),
GENLIB_NAME ("ram_q%ld[3:0]", i),
"ram_nrb[3:0]",
"vdd", "vss", NULL);
}
/* Output drivers for A & B output. */
GENLIB_LOINS ("model_inv_x8", "inv_ra",
"ram_nra[3:0]",
"ram_ra[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv_x8", "inv_rb",
"ram_nrb[3:0]",
"ram_rb[3:0]",
"vdd", "vss", NULL);
/* --------------------------------------------------------------
* RAM shifter.
*/
GENLIB_LOINS ("model_nmux2", "ram_nmux_0",
"ram_sh[0]",
"ram_i_up", "alu_f[3:1]", /* i1 */
"alu_f[2:0]", "ram_i_down", /* i0 */
"ram_nmux_0[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "ram_inv_1",
"alu_f[3:0]", /* i2 */
"ram_inv_1[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nmux2", "ram_nmux_1",
"ram_sh[1]",
"ram_inv_1[3:0]",
"ram_nmux_0[3:0]",
"ram_d[3:0]",
"vdd", "vss", NULL);
/* *********************** Operand S ************************ */
GENLIB_LOINS ("model_nmux2", "ops_nmux_0",
"ops_mx[0]",
"ram_rb[3:0]", /* i1 */
"acc_scout", "acc_q[2:1]", "acc_q_down", /* i0 */
"ops_nmux_0[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "ops_inv_1",
"ram_ra[3:0]", /* i2 */
"ops_inv_1[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nmux2", "ops_nmux_1",
"ops_mx[1]",
"ops_inv_1[3:0]",
"ops_nmux_0[3:0]",
"ops_it[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nand2mask_0000", "ops_na2mask_0b0000",
"ops_mx[2]" ,
"ops_it[3:0]",
"ops_ns[3:0]",
"vdd", "vss", NULL);
/* *********************** Operand R ************************ */
GENLIB_LOINS ("model_mux2", "opr_mux",
"opr_mx[0]",
"opr_d[3:0]", /* i1 */
"ram_ra[3:0]", /* i0 */
"opr_it[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nand2mask_0000", "opr_na2mask_0b0000",
"opr_mx[1]" ,
"opr_it[3:0]",
"opr_nr[3:0]",
"vdd", "vss", NULL);
/* *********************** ALU Description ****************** */
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opnr",
"alu_k[0]" ,
"opr_nr[3:0]",
"alu_xr[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opns",
"alu_k[1]" ,
"ops_ns[3:0]",
"alu_xs[3:0]",
"vdd", "vss", NULL);
/* Compute of "generate". */
GENLIB_LOINS ("model_nand2", "alu_na2_ng",
"alu_xr[3:0]",
"alu_xs[3:0]",
"alu_ng[3:0]",
"vdd", "vss", NULL);
/* Compute of "propagate". */
GENLIB_LOINS ("model_nor2", "alu_no2_np",
"alu_xr[3:0]",
"alu_xs[3:0]",
"alu_np[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "alu_n1_p" ,
"alu_np[3:0]",
"alu_p[3:0]",
"vdd", "vss", NULL);
/* Compute of carry. */
GENLIB_LOINS ("model_nand2", "alu_na2_npc" ,
"alu_p[3:0]",
"alu_over", "alu_carry[2:1]", "alu_cin",
"alu_npc[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nand2", "alu_na2_carry",
"alu_ng[3:0]",
"alu_npc[3:0]",
"alu_cout", "alu_over", "alu_carry[2:1]",
"vdd", "vss", NULL);
/* Logical and arithmetical operators. */
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_and",
"alu_k[2]" ,
"alu_ng[3:0]",
"alu_r_and_s[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_or" ,
"alu_k[3]" ,
"alu_np[3:0]",
"alu_r_or_s[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_add",
"alu_k[4]" ,
"alu_over", "alu_carry[2:1]", "alu_cin",
"alu_r_add_s[3:0]",
"vdd", "vss", NULL);
/* Output. */
GENLIB_LOINS ("model_xor2", "alu_nxr2_op",
"alu_r_and_s[3:0]",
"alu_r_or_s[3:0]",
"alu_r_op_s[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_xnor2", "alu_nxr2_f" ,
"alu_r_op_s[3:0]",
"alu_r_add_s[3:0]",
"alu_f[3:0]",
"vdd", "vss", NULL);
/* ******************** ACCU Description ******************** */
GENLIB_LOINS ("model_nmux2", "accu_nmux_0",
"acc_sh[0]",
"acc_i_up", "acc_scout", "acc_q[2:1]", /* i1 : down */
"acc_q[2:1]", "acc_q_down", "acc_i_down", /* i0 : up */
"accu_nmux_0[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_inv", "accu_inv_1",
"alu_f[3:0]", /* i2: no */
"accu_inv_1[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_nmux2", "accu_nmux_1",
"acc_sh[1]",
"accu_inv_1[3:0]",
"accu_nmux_0[3:0]",
"acc_d[3:0]",
"vdd", "vss", NULL);
GENLIB_LOINS ("model_sfft", "acc_reg",
"acc_test" ,
"acc_scin" ,
"acc_wen",
"acc_ck" ,
"acc_d[3:0]",
"acc_scout", "acc_q[2:1]", "acc_q_down",
"vdd", "vss", NULL);
/* ******************* Output Multiplexer ******************* */
GENLIB_LOINS ("model_mux2", "out_mx",
"out_mx" ,
"ram_ra[3:0]", /* i1 */
"alu_f[3:0]", /* i0 */
"out_x[3:0]",
"vdd", "vss", NULL);
/* End of netlist description. */
GENLIB_SAVE_LOFIG ();
/* Partial placement description. */
GENLIB_DEF_PHFIG ("amd2901_rf");
for (i = 0; i < 16; i++)
{
/* Register part. */
if (!(i % 8)) {
if (!i) {
GENLIB_PLACE ("model_sff", GENLIB_NAME ("ram_reg%ld",i), NOSYM, 0, 0);
} else {
GENLIB_DEF_PHINS (GENLIB_NAME ("ram_reg%ld", i - 8));
GENLIB_PLACE_TOP ("model_sff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
}
} else {
GENLIB_PLACE_RIGHT ("model_sff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
}
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i), NOSYM);
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsb%ld",i), NOSYM);
}
GENLIB_PLACE_RIGHT ("model_inv_x8", "ram_ra", NOSYM);
GENLIB_DEF_PHINS ("ram_ntsb7");
GENLIB_PLACE_RIGHT ("model_inv_x8", "ram_rb", NOSYM);
/* Add enougth place for the decoder : 2 slice). */
GENLIB_DEF_AB (0, 0, 0, 100);
/* End of placement description. */
GENLIB_SAVE_PHFIG ();
/* A good C program must always terminate by an "exit(0)". */
exit(0);
}
int main ()
{
int i;
GENLIB_DEF_LOFIG("amd2901_chip");
GENLIB_LOCON("ck", IN ,"ck");
GENLIB_LOCON( "cin", IN, "cin");
GENLIB_LOCON( "cout", OUT, "cout");
GENLIB_LOCON( "np", OUT , "np");
GENLIB_LOCON( "ng", OUT , "ng");
GENLIB_LOCON( "ovr", OUT , "ovr");
GENLIB_LOCON( "zero", OUT , "zero");
GENLIB_LOCON("signe", UNKNOWN,"signe");
GENLIB_LOCON("r0", UNKNOWN, "r0");
GENLIB_LOCON("r3", UNKNOWN, "r3");
GENLIB_LOCON("q0", UNKNOWN, "q0");
GENLIB_LOCON("q3", UNKNOWN, "q3");
GENLIB_LOCON( "fonc", IN , "fonc");
GENLIB_LOCON( "test", IN , "test");
GENLIB_LOCON( "scin", IN , "scin");
GENLIB_LOCON("scout", OUT ,"scout");
GENLIB_LOCON("a[3:0]", IN , "a[3:0]");
GENLIB_LOCON("b[3:0]", IN , "b[3:0]");
GENLIB_LOCON("d[3:0]", IN , "d[3:0]");
GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
GENLIB_LOCON("noe" , IN , "noe" );
GENLIB_LOCON("y[3:0]", UNKNOWN, "y[3:0]");
GENLIB_LOCON("vdd" , IN , "vdd" );
GENLIB_LOCON("vss" , IN , "vss" );
GENLIB_LOCON("vdde", IN , "vdde");
GENLIB_LOCON("vsse", IN , "vsse");
GENLIB_LOINSE ( "amd2901_core", "core",
"cin => cin_i",
"cout => cout_i",
"np => np_i",
"ng => ng_i",
"over => ovr_i",
"zero => zero_i",
"sh_right => sh_right",
"sh_left => sh_left",
"ram_o_down => ram_o_down",
"ram_o_up => ram_o_up",
"ram_i_down => ram_i_down",
"ram_i_up => ram_i_up",
"acc_o_down => acc_o_down",
"acc_o_up => acc_o_up",
"acc_i_down => acc_i_down",
"acc_i_up => acc_i_up",
"fonc => fonc_i",
"test => test_i",
"scin => scin_i",
"ck => ckc",
"a[3:0] => a_i[3:0]",
"b[3:0] => b_i[3:0]",
"d[3:0] => d_i[3:0]",
"i[8:0] => i_i[8:0]",
"y[3:0] => y_i[3:0]",
"noe => noe_i",
"oe => oe",
"vdd => vdd",
"vss => vss",
NULL);
GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
GENLIB_LOINS("pi_sp","p_fonc","fonc","fonc_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_test","test","test_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_scin","scin","scin_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_cin","cin","cin_i","cki", POWER );
GENLIB_LOINS("pi_sp","p_noe","noe","noe_i","cki", POWER );
for (i=0;i<4;i++)
{
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_a%d",i), GENLIB_ELM("a",i), GENLIB_ELM("a_i",i), "cki", POWER );
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_b%d",i), GENLIB_ELM("b",i), GENLIB_ELM("b_i",i), "cki", POWER );
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_d%d",i), GENLIB_ELM("d",i), GENLIB_ELM("d_i",i), "cki", POWER );
}
for (i=0;i<9;i++)
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_i%d",i), GENLIB_ELM("i",i), GENLIB_ELM("i_i",i), "cki", POWER );
GENLIB_LOINS("po_sp","p_cout","cout_i","cout","cki", POWER );
GENLIB_LOINS("po_sp","p_np","np_i","np","cki", POWER );
GENLIB_LOINS("po_sp","p_ng","ng_i","ng","cki", POWER );
GENLIB_LOINS("po_sp","p_ovr","ovr_i","ovr","cki", POWER );
GENLIB_LOINS("po_sp","p_zero","zero_i","zero","cki", POWER );
GENLIB_LOINS("po_sp","p_signe","ram_o_up","signe","cki", POWER );
GENLIB_LOINS("po_sp","p_scout","acc_o_up","scout","cki", POWER );
for (i=0;i<4;i++)
GENLIB_LOINS ("pot_sp",GENLIB_NAME("p_y%d",i),
GENLIB_ELM("y_i",i), "oe", GENLIB_ELM("y",i), "cki", POWER );
GENLIB_LOINS ("piot_sp","p_q0",
"acc_o_down","sh_right","acc_i_down","q0","cki", POWER );
GENLIB_LOINS ("piot_sp","p_q3",
"acc_o_up","sh_left","acc_i_up","q3","cki", POWER );
GENLIB_LOINS ("piot_sp","p_r0",
"ram_o_down","sh_right","ram_i_down","r0","cki", POWER );
GENLIB_LOINS ("piot_sp","p_r3",
"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",NULL);
GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",NULL);
GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",NULL);
GENLIB_SAVE_LOFIG();
exit (0);
}
main()
{
long i;
GENLIB_DEF_LOFIG("amd2901_ctl");
/* ***************** Terminal Declarations ****************** */
/* Input/Output from and to the data-path. */
/* Command for selecting operands R and S. */
GENLIB_LOCON("ops_mx[2:0]", OUT, "ops_mx[2:0]");
GENLIB_LOCON("opr_mx[1:0]", OUT, "opr_mx[1:0]");
/* ALU commands and auxiliary terminals. */
GENLIB_LOCON("alu_k[4:0]", OUT, "alu_k[4:0]");
GENLIB_LOCON("alu_cout" , IN , "alu_cout" );
GENLIB_LOCON("alu_over" , IN , "alu_over" );
/* RAM, ACCU shifter commands and auxiliary terminals.
* ("acc_sh" is same as "ram_sh")
*/
GENLIB_LOCON("ram_sh[1:0]", OUT, "ram_sh[1:0]");
/* Output multiplexer commnand (for X bus). */
GENLIB_LOCON("out_mx", OUT, "out_mx");
/* ACCU controls terminals.
* ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots)
*/
GENLIB_LOCON("acc_wen" , OUT, "acc_wen" );
/* Data bus terminals. */
GENLIB_LOCON( "alu_f[3:0]", IN, "alu_f[3:0]");
GENLIB_LOCON("alu_np[3:0]", IN, "alu_np[3:0]");
GENLIB_LOCON("alu_ng[3:0]", IN, "alu_ng[3:0]");
/* Input/Output from and to the plots. */
/* Test terminals from/to plots. */
GENLIB_LOCON("core_test", IN , "core_test");
GENLIB_LOCON("core_fonc", IN , "core_fonc");
/* ALU terminals from/to plots. */
/* GENLIB_LOCON("core_cout", OUT, "core_cout"); */
GENLIB_LOCON("core_np" , OUT, "core_np" );
GENLIB_LOCON("core_ng" , OUT, "core_ng" );
GENLIB_LOCON("core_over", OUT, "core_over");
GENLIB_LOCON("core_zero", OUT, "core_zero");
/* RAM, ACCU shifter terminals from/to plots.
* RAM and ACCU I/O plots controls.
*/
GENLIB_LOCON("core_sh_right" , OUT, "core_sh_right" );
GENLIB_LOCON("core_sh_left" , OUT, "core_sh_left" );
/* Data bus terminals from/to the plots. */
GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
GENLIB_LOCON("noe", IN , "noe");
GENLIB_LOCON("oe", OUT , "oe");
/* + */
GENLIB_LOCON("a[3:0]", IN, "a[3:0]");
GENLIB_LOCON("b[3:0]", IN, "b[3:0]");
// GENLIB_LOCON("wb[3:0]", OUT, "wb[3:0]");
GENLIB_LOCON("deca[15:0]", OUT, "deca[15:0]");
GENLIB_LOCON("decb[15:0]", OUT, "decb[15:0]");
GENLIB_LOCON("decwb[15:0]", OUT, "decwb[15:0]");
/* - */
// GENLIB_LOCON("ram_wri", OUT, "ram_wri");
/* Power supply connectors. */
GENLIB_LOCON("vdd", IN , "vdd");
GENLIB_LOCON("vss", IN , "vss");
/* + */
/* decoders for RAM RA and RB addresses. */
GENLIB_LOINS ("inv_x4", "inv_a0", "a[0]", "na[0]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_a1", "a[1]", "na[1]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_a2", "a[2]", "na[2]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_a3", "a[3]", "na[3]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_b0", "b[0]", "nb[0]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_b1", "b[1]", "nb[1]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_b2", "b[2]", "nb[2]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_b3", "b[3]", "nb[3]", "vdd", "vss", NULL);
GENLIB_LOINS ("inv_x4", "inv_wen", "ram_wri", "ram_nwen", "vdd", "vss", NULL);
for (i = 0; i < 16; i++)
{
GENLIB_LOINS ("na4_x1", GENLIB_NAME ("na4_ram_adrb_%d_0", i),
GENLIB_NAME ("%s[3]", (getbit (i, 3) ? "b" : "nb")),
GENLIB_NAME ("%s[2]", (getbit (i, 2) ? "b" : "nb")),
GENLIB_NAME ("%s[1]", (getbit (i, 1) ? "b" : "nb")),
GENLIB_NAME ("%s[0]", (getbit (i, 0) ? "b" : "nb")),
GENLIB_NAME ("ram_adrb_%d",i),
"vdd", "vss", NULL);
GENLIB_LOINS ("inv_x2", GENLIB_NAME ("n1_ram_adrb_%d_1",i),
GENLIB_NAME ("ram_adrb_%d", i),
GENLIB_ELM ("decb", i),
"vdd", "vss", NULL);
GENLIB_LOINS ("no2_x1", GENLIB_NAME ("no2_ram_adri_%d_0",i),
GENLIB_NAME ("ram_adrb_%d", i),
"ram_nwen",
GENLIB_ELM ("decwb", i),
"vdd", "vss", NULL);
GENLIB_LOINS ("a4_x2", GENLIB_NAME ("a4_ram_adra_%d_0",i),
GENLIB_NAME("%s[3]", (getbit (i, 3) ? "a" : "na")),
GENLIB_NAME("%s[2]", (getbit (i, 2) ? "a" : "na")),
GENLIB_NAME("%s[1]", (getbit (i, 1) ? "a" : "na")),
GENLIB_NAME("%s[0]", (getbit (i, 0) ? "a" : "na")),
GENLIB_ELM("deca", i),
"vdd", "vss", NULL);
}
/* - */
/* ***************** S multiplexer control ****************** */
GENLIB_LOINS("inv_x1", "n1_i2", "i[2]", "ni[2]", POWER);
GENLIB_LOINS("inv_x1", "n1_i1", "i[1]", "ni[1]", POWER);
GENLIB_LOINS("inv_x1", "n1_i0", "i[0]", "ni[0]", POWER);
GENLIB_LOINS("no2_x1", "no2_ops_mx0", "i[2]", "ni[0]", "ops_mx[0]", POWER);
GENLIB_LOINS("no2_x1", "no2_ops_mx1", "ni[2]", "i[1]", "ops_mx[1]", POWER);
GENLIB_LOINS( "a3_x2", "a3_ops_mx2", "i[2]", "i[1]", "i[0]", "ops_mx[2]", POWER);
/* ***************** R multiplexer control ****************** */
GENLIB_LOINS( "o2_x2", "o2_opr_mx0" , "i[2]", "i[1]", "opr_mx[0]", POWER);
GENLIB_LOINS("na2_x1", "na2_opr_mx1_0", "ni[2]", "i[1]", "opr_mx1_0", POWER);
GENLIB_LOINS("na3_x1", "na3_opr_mx1_1", "i[2]", "ni[1]", "ni[0]","opr_mx1_1", POWER);
GENLIB_LOINS("na2_x1", "na2_opr_mx1_2", "opr_mx1_0","opr_mx1_1","opr_mx[1]", POWER);
/* ***************** X multiplexer control ****************** */
GENLIB_LOINS("inv_x1", "n1_i3", "i[7]", "ni[3]", POWER);
GENLIB_LOINS("no3_x1", "no3_out_mx0", "i[8]", "ni[3]", "i[6]", "out_mx", POWER);
/* ********************** ALU control *********************** */
/* ALU commands. */
GENLIB_LOINS("xr2_x1", "xr2_alu_k0", "i[5]", "i[3]", "alu_k[0]", POWER);
GENLIB_LOINS("xr2_x1", "xr2_alu_k1", "i[5]", "i[4]", "alu_k[1]", POWER);
GENLIB_LOINS( "inv_x1", "n1_i4", "i[4]", "ni[4]", POWER);
GENLIB_LOINS( "a2_x2", "a2_alu_k2", "i[5]", "ni[4]", "alu_k[2]", POWER);
GENLIB_LOINS( "inv_x1", "n1_i5", "i[5]", "ni[5]", POWER);
GENLIB_LOINS( "a3_x2", "a3_alu_k3", "ni[5]","i[4]","i[3]","alu_k[3]", POWER);
GENLIB_LOINS( "a2_x2", "a2_alu_k4", "i[4]", "i[3]", "alu_k4_0", POWER);
GENLIB_LOINS( "o2_x2", "o2_alu_k4", "alu_k4_0", "i[5]", "alu_k[4]", POWER);
/* Compute of ALU flags.
* Propagate.
*/
GENLIB_LOINS("no2_x1", "no2_alu_p_0", "alu_np[0]", "alu_np[1]", "alu_p_0", POWER);
GENLIB_LOINS("no2_x1", "no2_alu_p_1", "alu_np[2]", "alu_np[3]", "alu_p_1", POWER);
GENLIB_LOINS("na2_x1", "na2_alu_p", "alu_p_0", "alu_p_1", "core_np", POWER);
/* Generate. */
GENLIB_LOINS("no2_x1", "no2_alu_g_0", "alu_np[1]", "alu_ng[0]", "alu_g_0", POWER);
GENLIB_LOINS("no2_x1", "no2_alu_g_1", "alu_np[3]", "alu_np[2]", "alu_g_1", POWER);
GENLIB_LOINS( "inv_x1", "n1_alu_g_2", "alu_ng[1]", "alu_g_2", POWER);
GENLIB_LOINS("noa22_x1", "noa3_alu_g_3", "alu_np[3]","alu_ng[2]","alu_ng[3]","alu_g_3" , POWER);
GENLIB_LOINS( "inv_x1", "n1_alu_g_4", "alu_g_3" , "alu_g_4", POWER);
GENLIB_LOINS("na2_x1", "na2_alu_g_5", "alu_g_0", "alu_g_1", "alu_g_5", POWER);
GENLIB_LOINS("na2_x1", "na2_alu_g_6", "alu_g_1", "alu_g_2", "alu_g_6", POWER);
GENLIB_LOINS("a3_x2", "na3_alu_g_7", "alu_g_4",
"alu_g_5",
"alu_g_6",
"core_ng" , POWER);
/* Zero and overflow */
GENLIB_LOINS("no2_x1", "no2_alu_zero_0", "alu_f[0]", "alu_f[1]", "alu_zero_0", POWER);
GENLIB_LOINS("no2_x1", "no2_alu_zero_1", "alu_f[2]", "alu_f[3]", "alu_zero_1", POWER);
GENLIB_LOINS("a2_x2", "a2_alu_zero", "alu_zero_0", "alu_zero_1", "core_zero", POWER);
GENLIB_LOINS("xr2_x1", "nxr2_alu_nover", "alu_over",
"alu_cout", "core_over", POWER);
/* ********************* ACCU control *********************** */
GENLIB_LOINS("inv_x1", "n1_i6", "i[8]", "ni[6]", POWER);
/* Compute of ACCU write enable. */
GENLIB_LOINS("noa22_x1", "nao3_acc_wen", "ni[6]",
"i[7]",
"i[6]",
"acc_wen" , POWER);
/* ********************** RAM control *********************** */
/* ACCU and RAM shift multiplexer control. */
GENLIB_LOINS("na2_x1", "na2_ram_sh0", "i[8]", "i[7]", "ram_sh[0]", POWER);
GENLIB_LOINS( "inv_x1", "n1_ram_sh1", "i[8]", "ram_sh[1]", POWER);
/* RAM and ACCU I/O plots controls. */
GENLIB_LOINS("a2_x2","a2_core_sh_left" ,"i[8]", "i[7]","core_sh_left" ,POWER);
GENLIB_LOINS("a2_x2","a2_core_sh_right","i[8]","ni[3]","core_sh_right",POWER);
/* Compute of RAM write enable. */
GENLIB_LOINS( "inv_x1", "n1_ram_nwri_0", "core_fonc", "core_nfonc", POWER);
GENLIB_LOINS( "no2_x1", "no2_ram_nwri_1", "core_test", "core_nfonc",
"fonc_mode" , POWER);
GENLIB_LOINS("noa22_x1", "noa3_ram_nwri_2", "i[8]",
"i[7]",
"fonc_mode" ,
"ram_nwri" , POWER);
GENLIB_LOINS("inv_x1","inv_ram_wri","ram_nwri","ram_wri", POWER );
GENLIB_LOINS( "inv_x1","inv_noe","noe","oe", POWER);
GENLIB_SAVE_LOFIG();
exit(0);
}
