uint32_t TM_DMA_GetFlags(DMA_Stream_TypeDef* DMA_Stream, uint32_t flag) {
uint32_t stream_number = 0;
uint32_t location = 0;
uint32_t flags = 0;
/* Check stream value */
if (DMA_Stream < DMA2_Stream0) {
location = (uint32_t)&DMA1->LISR;
stream_number = GET_STREAM_NUMBER_DMA1(DMA_Stream);
} else {
location = (uint32_t)&DMA2->LISR;
stream_number = GET_STREAM_NUMBER_DMA2(DMA_Stream);
}
/* Get register offset */
if (stream_number >= 4) {
/* High registers for DMA clear */
location += 4;
/* Do offset for high DMA registers */
stream_number -= 4;
}
/* Get register value */
flags = *(__IO uint32_t *)location;
flags >>= DMA_Flags_Bit_Pos[stream_number];
flags &= DMA_FLAG_ALL;
/* Return value */
return flags;
}
void TM_DMA_ClearFlag(DMA_Stream_TypeDef* DMA_Stream, uint32_t flag) {
uint32_t location;
uint32_t stream_number;
/* Check stream value */
if (DMA_Stream < DMA2_Stream0) {
location = (uint32_t)&DMA1->LIFCR;
stream_number = GET_STREAM_NUMBER_DMA1(DMA_Stream);
} else {
location = (uint32_t)&DMA2->LIFCR;
stream_number = GET_STREAM_NUMBER_DMA2(DMA_Stream);
}
/* Get register offset */
if (stream_number >= 4) {
/* High registers for DMA clear */
location += 4;
/* Do offset for high DMA registers */
stream_number -= 4;
}
/* Clear flags */
*(__IO uint32_t *)location = (flag & DMA_FLAG_ALL) << DMA_Flags_Bit_Pos[stream_number];
}
void TM_DMA_EnableInterrupts(DMA_Stream_TypeDef* DMA_Stream) {
uint32_t stream_number;
IRQn_Type type;
uint32_t preemption;
/* Clear flags first */
TM_DMA_ClearFlag(DMA_Stream, DMA_FLAG_ALL);
/* Check stream value */
if (DMA_Stream < DMA2_Stream0) {
stream_number = GET_STREAM_NUMBER_DMA1(DMA_Stream);
preemption = DMA1_NVIC_PREEMPTION_PRIORITY;
type = DMA_IRQs[0][stream_number];
} else {
stream_number = GET_STREAM_NUMBER_DMA2(DMA_Stream);
preemption = DMA2_NVIC_PREEMPTION_PRIORITY;
type = DMA_IRQs[1][stream_number];
}
/* Disable IRQ */
HAL_NVIC_DisableIRQ(type);
/* Set priorities */
HAL_NVIC_SetPriority(type, preemption, stream_number);
/* Enable IRQ */
HAL_NVIC_EnableIRQ(type);
/* Enable DMA stream interrupts */
DMA_Stream->CR |= DMA_SxCR_TCIE | DMA_SxCR_HTIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE;
DMA_Stream->FCR |= DMA_SxFCR_FEIE;
}
void TM_DMA_DisableInterrupts(DMA_Stream_TypeDef* DMA_Stream) {
NVIC_InitTypeDef NVIC_InitStruct;
uint32_t stream_number;
/* Clear flags first */
TM_DMA_ClearFlags(DMA_Stream);
/* Check stream value */
if (DMA_Stream < DMA2_Stream0) {
stream_number = GET_STREAM_NUMBER_DMA1(DMA_Stream);
NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = DMA1_NVIC_PREEMPTION_PRIORITY;
NVIC_InitStruct.NVIC_IRQChannel = DMA_IRQs[0][stream_number];
} else {
stream_number = GET_STREAM_NUMBER_DMA2(DMA_Stream);
NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = DMA2_NVIC_PREEMPTION_PRIORITY;
NVIC_InitStruct.NVIC_IRQChannel = DMA_IRQs[1][stream_number];
}
NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
NVIC_InitStruct.NVIC_IRQChannelSubPriority = stream_number;
/* Init NVIC */
NVIC_Init(&NVIC_InitStruct);
/* Disable DMA stream interrupts */
DMA_Stream->CR &= ~(DMA_SxCR_TCIE | DMA_SxCR_HTIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE);
DMA_Stream->FCR &= DMA_SxFCR_FEIE;
}
void TM_DMA_DisableInterrupts(DMA_Stream_TypeDef* DMA_Stream) {
IRQn_Type IRQValue;
/* Clear flags first */
TM_DMA_ClearFlag(DMA_Stream, DMA_FLAG_ALL);
/* Check stream value */
if (DMA_Stream < DMA2_Stream0) {
IRQValue = DMA_IRQs[0][GET_STREAM_NUMBER_DMA1(DMA_Stream)];
} else {
IRQValue = DMA_IRQs[0][GET_STREAM_NUMBER_DMA2(DMA_Stream)];
}
/* Disable NVIC */
HAL_NVIC_DisableIRQ(IRQValue);
/* Disable DMA stream interrupts */
DMA_Stream->CR &= ~(DMA_SxCR_TCIE | DMA_SxCR_HTIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE);
DMA_Stream->FCR &= DMA_SxFCR_FEIE;
}
