static size_t probe_max_it(vaddr_t gicc_base, vaddr_t gicd_base)
{
int i;
uint32_t old_ctlr;
size_t ret = 0;
const size_t max_regs = ((GIC_MAX_INTS + NUM_INTS_PER_REG - 1) /
NUM_INTS_PER_REG) - 1;
/*
* Probe which interrupt number is the largest.
*/
old_ctlr = read32(gicc_base + GICC_CTLR);
write32(0, gicc_base + GICC_CTLR);
for (i = max_regs; i >= 0; i--) {
uint32_t old_reg;
uint32_t reg;
int b;
old_reg = read32(gicd_base + GICD_ISENABLER(i));
write32(0xffffffff, gicd_base + GICD_ISENABLER(i));
reg = read32(gicd_base + GICD_ISENABLER(i));
write32(old_reg, gicd_base + GICD_ICENABLER(i));
for (b = NUM_INTS_PER_REG - 1; b >= 0; b--) {
if (BIT32(b) & reg) {
ret = i * NUM_INTS_PER_REG + b;
goto out;
}
}
}
out:
write32(old_ctlr, gicc_base + GICC_CTLR);
return ret;
}
void gic_init(vaddr_t gicc_base, vaddr_t gicd_base)
{
size_t n;
gic.gicc_base = gicc_base;
gic.gicd_base = gicd_base;
gic.max_it = probe_max_it();
for (n = 0; n <= gic.max_it / NUM_INTS_PER_REG; n++) {
/* Disable interrupts */
write32(0xffffffff, gic.gicd_base + GICD_ICENABLER(n));
/* Make interrupts non-pending */
write32(0xffffffff, gic.gicd_base + GICD_ICPENDR(n));
/* Mark interrupts non-secure */
if (n == 0) {
/* per-CPU inerrupts config:
* ID0-ID7(SGI) for Non-secure interrupts
* ID8-ID15(SGI) for Secure interrupts.
* All PPI config as Non-secure interrupts.
*/
write32(0xffff00ff, gic.gicd_base + GICD_IGROUPR(n));
} else {
write32(0xffffffff, gic.gicd_base + GICD_IGROUPR(n));
}
}
/* Enable GIC */
write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN,
gic.gicc_base + GICC_CTLR);
write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1,
gic.gicd_base + GICD_CTLR);
}
void gic_init(vaddr_t gicc_base, vaddr_t gicd_base)
{
size_t n;
gic.gicc_base = gicc_base;
gic.gicd_base = gicd_base;
gic.max_it = probe_max_it();
for (n = 0; n <= gic.max_it / 32; n++) {
/* Disable interrupts */
write32(0xffffffff, gic.gicd_base + GICD_ICENABLER(n));
/* Make interrupts non-pending */
write32(0xffffffff, gic.gicd_base + GICD_ICPENDR(n));
/* Mark interrupts non-secure */
write32(0xffffffff, gic.gicd_base + GICD_IGROUPR(n));
}
/* Enable GIC */
write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN,
gic.gicc_base + GICC_CTLR);
write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1,
gic.gicd_base + GICD_CTLR);
}
static size_t probe_max_it(void)
{
int i;
uint32_t old_ctlr;
size_t ret = 0;
/*
* Probe which interrupt number is the largest.
*/
old_ctlr = read32(gic.gicc_base + GICC_CTLR);
write32(0, gic.gicc_base + GICC_CTLR);
for (i = GIC_MAX_INTS / 32; i > 0; i--) {
uint32_t old_reg;
uint32_t reg;
int b;
old_reg = read32(gic.gicd_base + GICD_ISENABLER(i));
write32(0xffffffff, gic.gicd_base + GICD_ISENABLER(i));
reg = read32(gic.gicd_base + GICD_ISENABLER(i));
write32(old_reg, gic.gicd_base + GICD_ICENABLER(i));
for (b = 31; b > 0; b--) {
if ((1 << b) & reg) {
ret = i * 32 + b;
goto out;
}
}
}
out:
write32(old_ctlr, gic.gicc_base + GICC_CTLR);
return ret;
}
/**
* \fn init_gic_distributor
*
* Initialise GIC Dirstributor.
*
* Configure all IRQs to be active low, level sensitive, target cpu0,
* priority 0xa0 and disable all interrupts.
*/
void init_gic_distributor()
{
GICD[GICD_CTLR] = 0x0; // disable GIC
unsigned int typer = GICD[GICD_TYPER];
unsigned int lines = 32 * ((typer & 0x1F) + 1);
unsigned int i;
/* set global interrupts to active low, level sensitive */
for (i = 32; i < lines; i += 16) {
GICD[GICD_ICFGR(i / 16)] = 0x0;
}
for (i = 32; i < lines; i += 4) {
GICD[GICD_ITARGETSR(i / 4)] = 0x01010101;
}
for (i = 32; i < lines; i += 4) {
GICD[GICD_IPRIORITYR(i / 4)] = 0xa0a0a0a0;
}
for (i = 32; i < lines; i += 32) {
GICD[GICD_ICENABLER(i / 32)] = 0xFFFFFFFF;
}
for (i = 32; i < lines; i += 32) {
GICD[GICD_IGROUPR(i / 32)] = 0x0;
}
GICD[GICD_CTLR] = 0x0;
}
void irqctrl_disable(unsigned int irq) {
int n = irq / BITS_PER_REGISTER;
int m = irq % BITS_PER_REGISTER;
/* Writing zeroes to this register has no
* effect, so we just write single "1" */
REG_STORE(GICD_ICENABLER(n), 1 << m);
}
static void gic_it_disable(struct gic_data *gd, size_t it)
{
size_t idx = it / NUM_INTS_PER_REG;
uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
/* Assigned to group0 */
assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));
/* Disable the interrupt */
write32(mask, gd->gicd_base + GICD_ICENABLER(idx));
}
void gic_it_disable(size_t it)
{
size_t idx = it / NUM_INTS_PER_REG;
uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
assert(it <= gic.max_it); /* Not too large */
/* Assigned to group0 */
assert(!(read32(gic.gicd_base + GICD_IGROUPR(idx)) & mask));
/* Disable the interrupt */
write32(mask, gic.gicd_base + GICD_ICENABLER(idx));
}
/**
* \fn init_gic_cpu
*
* Initialise GIC CPU interface
*/
void init_gic_cpu()
{
unsigned int i;
GICD[GICD_ICENABLER(0)] = 0xFFFF0000;
GICD[GICD_ISENABLER(0)] = 0x0000FFFF;
for (i = 0; i < 128; i += 4)
GICD[GICD_IPRIORITYR(i / 4)] = 0xa0a0a0a0;
GICC[GICC_PMR] = 0xff;
GICC[GICC_BPR] = 0;
GICC[GICC_CTLR] = 0x201;
}
static void gic_it_add(struct gic_data *gd, size_t it)
{
size_t idx = it / NUM_INTS_PER_REG;
uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
/* Disable the interrupt */
write32(mask, gd->gicd_base + GICD_ICENABLER(idx));
/* Make it non-pending */
write32(mask, gd->gicd_base + GICD_ICPENDR(idx));
/* Assign it to group0 */
write32(read32(gd->gicd_base + GICD_IGROUPR(idx)) & ~mask,
gd->gicd_base + GICD_IGROUPR(idx));
}
void gic_it_add(size_t it)
{
size_t idx = it / NUM_INTS_PER_REG;
uint32_t mask = 1 << (it % NUM_INTS_PER_REG);
assert(it <= gic.max_it); /* Not too large */
/* Disable the interrupt */
write32(mask, gic.gicd_base + GICD_ICENABLER(idx));
/* Make it non-pending */
write32(mask, gic.gicd_base + GICD_ICPENDR(idx));
/* Assign it to group0 */
write32(read32(gic.gicd_base + GICD_IGROUPR(idx)) & ~mask,
gic.gicd_base + GICD_IGROUPR(idx));
}
void gic_init(struct gic_data *gd, vaddr_t gicc_base, vaddr_t gicd_base)
{
size_t n;
gic_init_base_addr(gd, gicc_base, gicd_base);
for (n = 0; n <= gd->max_it / NUM_INTS_PER_REG; n++) {
/* Disable interrupts */
write32(0xffffffff, gd->gicd_base + GICD_ICENABLER(n));
/* Make interrupts non-pending */
write32(0xffffffff, gd->gicd_base + GICD_ICPENDR(n));
/* Mark interrupts non-secure */
if (n == 0) {
/* per-CPU inerrupts config:
* ID0-ID7(SGI) for Non-secure interrupts
* ID8-ID15(SGI) for Secure interrupts.
* All PPI config as Non-secure interrupts.
*/
write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(n));
} else {
write32(0xffffffff, gd->gicd_base + GICD_IGROUPR(n));
}
}
/* Set the priority mask to permit Non-secure interrupts, and to
* allow the Non-secure world to adjust the priority mask itself
*/
write32(0x80, gd->gicc_base + GICC_PMR);
/* Enable GIC */
write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN,
gd->gicc_base + GICC_CTLR);
write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1,
gd->gicd_base + GICD_CTLR);
}
/*
* ディストリビュータの初期化
*/
void
gicd_initialize(void)
{
int i;
/*
* ディストリビュータをディスエーブル
*/
sil_wrw_mem(GICD_CTLR, GICD_CTLR_DISABLE);
#ifdef TOPPERS_SAFEG_SECURE
/*
* すべての割込みをグループ1（IRQ）に設定
*/
for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) {
sil_wrw_mem(GICD_IGROUPR(i), 0xffffffffU);
}
#endif /* TOPPERS_SAFEG_SECURE */
/*
* すべての割込みを禁止
*/
for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) {
sil_wrw_mem(GICD_ICENABLER(i), 0xffffffffU);
}
/*
* すべての割込みペンディングをクリア
*/
for (i = 0; i < (GIC_TNUM_INTNO + 31) / 32; i++) {
sil_wrw_mem(GICD_ICPENDR(i), 0xffffffffU);
}
/*
* すべての割込みを最低優先度に設定
*/
for (i = 0; i < (GIC_TNUM_INTNO + 3) / 4; i++){
sil_wrw_mem(GICD_IPRIORITYR(i), 0xffffffffU);
}
/*
* すべての共有ペリフェラル割込みのターゲットをプロセッサ0に設定
*/
for (i = GIC_INTNO_SPI0 / 4; i < (GIC_TNUM_INTNO + 3) / 4; i++) {
sil_wrw_mem(GICD_ITARGETSR(i), 0x01010101U);
}
/*
* すべてのペリフェラル割込みをレベルトリガに設定
*/
for (i = GIC_INTNO_PPI0 / 16; i < (GIC_TNUM_INTNO + 15) / 16; i++) {
#ifdef GIC_ARM11MPCORE
sil_wrw_mem(GICD_ICFGR(i), 0x55555555U);
#else /* GIC_ARM11MPCORE */
sil_wrw_mem(GICD_ICFGR(i), 0x00000000U);
#endif /* GIC_ARM11MPCORE */
}
/*
* ディストリビュータをイネーブル
*/
sil_wrw_mem(GICD_CTLR, GICD_CTLR_ENABLE);
}