rtems_status_code bsp_interrupt_facility_initialize(void) { volatile gic_cpuif *cpuif = GIC_CPUIF; volatile gic_dist *dist = ARM_GIC_DIST; uint32_t id_count = get_id_count(dist); uint32_t id; arm_cp15_set_exception_handler( ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt ); for (id = 0; id < id_count; ++id) { gic_id_set_priority(dist, id, PRIORITY_DEFAULT); } for (id = 32; id < id_count; ++id) { gic_id_set_targets(dist, id, 0x01); } cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE; dist->icddcr = GIC_DIST_ICDDCR_ENABLE; return RTEMS_SUCCESSFUL; }
BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) { volatile gic_cpuif *cpuif = GIC_CPUIF; volatile gic_dist *dist = ARM_GIC_DIST; while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { /* Wait */ } cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE; }
BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) { volatile gic_cpuif *cpuif = GIC_CPUIF; volatile gic_dist *dist = ARM_GIC_DIST; while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { /* Wait */ } #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 dist->icdigr[0] = 0xffffffff; #endif cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); cpuif->iccicr = CPUIF_ICCICR; enable_fiq(); }