Example #1
0
void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
    __IO uint32_t *dmy_ctr;

    /* Wake-up Irq is not supported */
    if (type != IRQ_WAKEUP) {
        if (enable) {
            dmy_ctr = CTR_MATCH[obj->ch];
            if (type == IRQ_ERROR) {
                /* EWIE interrupts is enable */
                *dmy_ctr |= 0x00000200;
            } else if (type == IRQ_OVERRUN) {
                /* OLIE interrupts is enable */
                *dmy_ctr |= 0x00002000;
            } else if (type == IRQ_PASSIVE) {
                /* EPIE interrupts is enable */
                *dmy_ctr |= 0x00000400;
            } else if (type == IRQ_ARB) {
                /* ALIE interrupts is enable */
                *dmy_ctr |= 0x00008000;
            } else if (type == IRQ_BUS) {
                /* BEIE interrupts is enable */
                *dmy_ctr |= 0x00000100;
            }
            InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
            GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
            GIC_SetConfiguration(can_int_info[obj->ch][type].int_num, 1);
            GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
        } else {
            GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
        }
    }
}
Example #2
0
void lp_ticker_init(void)
{
    GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
    GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);

    /* Power Control for Peripherals      */
    mtu2_init();

    if (lp_ticker_inited) return;
    lp_ticker_inited = 1;

    MTU2TCR   = MTU2_TCR_TPSC;
    MTU2TSTR  |= MTU2_TSTR_CST;
    MTU2TIER  |= MTU2_TIER_n_TGIEA;

    // INTC settings
    InterruptHandlerRegister(LP_TICKER_TIMER_IRQn, (void (*)(uint32_t))lp_ticker_irq_handler);
    GIC_SetPriority(LP_TICKER_TIMER_IRQn, 5);
    GIC_SetConfiguration(LP_TICKER_TIMER_IRQn, 3);
}
Example #3
0
void us_ticker_init(void)
{
    GIC_DisableIRQ(OSTMI1TINT_IRQn);
    GIC_ClearPendingIRQ(OSTMI1TINT_IRQn);

    /* Power Control for Peripherals      */
    CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */

    if (us_ticker_inited) return;
    us_ticker_inited = 1;

    // timer settings
    OSTM1TT   = 0x01;    /* Stop the counter and clears the OSTM1TE bit.     */
    OSTM1CTL  = 0x02;    /* Free running timer mode. Interrupt disabled when star counter  */

    OSTM1TS   = 0x1;     /* Start the counter and sets the OSTM0TE bit.     */

    // INTC settings
    InterruptHandlerRegister(OSTMI1TINT_IRQn, (void (*)(uint32_t))us_ticker_irq_handler);
    GIC_SetPriority(OSTMI1TINT_IRQn, 5);
    GIC_SetConfiguration(OSTMI1TINT_IRQn, 3);
}