/**
* Reset TX & RX queue & statistics
* \param pGmacd Pointer to GMAC Driver instance.
*/
void GMACD_Reset(sGmacd *pGmacd)
{
Gmac *pHw = pGmacd->pHw;
GMACD_ResetRx(pGmacd, GMAC_QUE_0);
GMACD_ResetRx(pGmacd, GMAC_QUE_1);
GMACD_ResetRx(pGmacd, GMAC_QUE_2);
GMACD_ResetTx(pGmacd, GMAC_QUE_0);
GMACD_ResetTx(pGmacd, GMAC_QUE_1);
GMACD_ResetTx(pGmacd, GMAC_QUE_2);
//memset((void*)&GmacStatistics, 0x00, sizeof(GmacStats));
GMAC_NetworkControl(pHw, GMAC_NCR_TXEN | GMAC_NCR_RXEN
| GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);
}
/**
* Initialize necessary allocated buffer lists for GMAC Driver to transfer data.
* Must be invoked after GMACD_Init() but before RX/TX start.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pRxBuffer Pointer to allocated buffer for RX. The address should
* be 8-byte aligned and the size should be
* GMAC_RX_UNITSIZE * wRxSize.
* \param pRxD Pointer to allocated RX descriptor list.
* \param wRxSize RX size, in number of registered units (RX descriptors).
* \param pTxBuffer Pointer to allocated buffer for TX. The address should
* be 8-byte aligned and the size should be
* GMAC_TX_UNITSIZE * wTxSize.
* \param pTxD Pointer to allocated TX descriptor list.
* \param pTxCb Pointer to allocated TX callback list.
* \param wTxSize TX size, in number of registered units (TX descriptors).
* \return GMACD_OK or GMACD_PARAM.
* \note If input address is not 8-byte aligned the address is automatically
* adjusted and the list size is reduced by one.
*/
uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer, sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer, sGmacTxDescriptor *pTxD, fGmacdTransferCallback *pTxCb,
uint16_t wTxSize)
{
Gmac *pHw = pGmacd->pHw;
if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM;
/* Assign RX buffers */
if ( ((uint32_t)pRxBuffer & 0x7)
|| ((uint32_t)pRxD & 0x7) ) {
wRxSize --;
TRACE_DEBUG("RX list address adjusted\n\r");
}
pGmacd->pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8);
pGmacd->pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8);
pGmacd->wRxListSize = wRxSize;
/* Assign TX buffers */
if ( ((uint32_t)pTxBuffer & 0x7)
|| ((uint32_t)pTxD & 0x7) ) {
wTxSize --;
TRACE_DEBUG("TX list address adjusted\n\r");
}
pGmacd->pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8);
pGmacd->pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8);
pGmacd->wTxListSize = wTxSize;
pGmacd->fTxCbList = pTxCb;
/* Reset TX & RX */
GMACD_ResetRx(pGmacd);
GMACD_ResetTx(pGmacd);
/* Enable Rx and Tx, plus the stats register. */
GMAC_TransmitEnable(pHw, 1);
GMAC_ReceiveEnable(pHw, 1);
GMAC_StatisticsWriteEnable(pHw, 1);
/* Setup the interrupts for RX/TX completion (and errors) */
GMAC_EnableIt(pHw,
GMAC_INT_RX_BITS |
GMAC_INT_TX_BITS |
GMAC_IER_HRESP);
return GMACD_OK;
}
/**
* Initialize necessary allocated buffer lists for GMAC Driver to transfer data.
* Must be invoked after GMACD_Init() but before RX/TX start.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pRxBuffer Pointer to allocated buffer for RX. The address should
* be 8-byte aligned and the size should be
* GMAC_RX_UNITSIZE * wRxSize.
* \param pRxD Pointer to allocated RX descriptor list.
* \param wRxSize RX size, in number of registered units (RX descriptors).
* \param pTxBuffer Pointer to allocated buffer for TX. The address should
* be 8-byte aligned and the size should be
* GMAC_TX_UNITSIZE * wTxSize.
* \param pTxD Pointer to allocated TX descriptor list.
* \param pTxCb Pointer to allocated TX callback list.
* \param wTxSize TX size, in number of registered units (TX descriptors).
* \return GMACD_OK or GMACD_PARAM.
* \note If input address is not 8-byte aligned the address is automatically
* adjusted and the list size is reduced by one.
*/
uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer, sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer, sGmacTxDescriptor *pTxD, fGmacdTransferCallback *pTxCb,
uint16_t wTxSize,
gmacQueList_t queIdx)
{
Gmac *pHw = pGmacd->pHw;
if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM;
/* Assign RX buffers */
if ( ((uint32_t)pRxBuffer & 0x7)
|| ((uint32_t)pRxD & 0x7) )
{
wRxSize --;
TRACE_DEBUG("RX list address adjusted\n\r");
}
pGmacd->queueList[queIdx].pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8);
pGmacd->queueList[queIdx].pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8);
pGmacd->queueList[queIdx].wRxListSize = wRxSize;
/* Assign TX buffers */
if ( ((uint32_t)pTxBuffer & 0x7)
|| ((uint32_t)pTxD & 0x7) )
{
wTxSize --;
TRACE_DEBUG("TX list address adjusted\n\r");
}
pGmacd->queueList[queIdx].pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8);
pGmacd->queueList[queIdx].pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8);
pGmacd->queueList[queIdx].wTxListSize = wTxSize;
pGmacd->queueList[queIdx].fTxCbList = pTxCb;
/* Reset TX & RX */
GMACD_ResetRx(pGmacd, queIdx);
GMACD_ResetTx(pGmacd, queIdx);
/* Setup the interrupts for RX/TX completion (and errors) */
switch(queIdx)
{
case GMAC_QUE_0:
/* YBP: Que 0 should be configured last so as to enable transmit and Receive in the NCR register */
/* Enable Rx and Tx, plus the stats register. */
GMAC_TransmitEnable(pHw, 1);
GMAC_ReceiveEnable(pHw, 1);
GMAC_StatisticsWriteEnable(pHw, 1);
GMAC_EnableIt(pHw,
GMAC_INT_RX_BITS |
GMAC_INT_TX_BITS |
GMAC_INT_TX_ERR_BITS, GMAC_QUE_0);
break;
case GMAC_QUE_1:
GMAC_EnableIt(pHw,
GMAC_INT_RX_BITS |
GMAC_INT_TX_BITS |
GMAC_INT_TX_ERR_BITS, GMAC_QUE_1);
break;
case GMAC_QUE_2:
GMAC_EnableIt(pHw,
GMAC_INT_RX_BITS |
GMAC_INT_TX_BITS |
GMAC_INT_TX_ERR_BITS, GMAC_QUE_2);
break;
};
return GMACD_OK;
}
/**
* Initialize necessary allocated buffer lists for GMAC Driver to transfer data.
* Must be invoked after GMACD_Init() but before RX/TX start.
* \param pGmacd Pointer to GMAC Driver instance.
* \param pRxBuffer Pointer to allocated buffer for RX. The address should
* be 8-byte aligned and the size should be
* GMAC_RX_UNITSIZE * wRxSize.
* \param pRxD Pointer to allocated RX descriptor list.
* \param wRxSize RX size, in number of registered units (RX descriptors).
* \param pTxBuffer Pointer to allocated buffer for TX. The address should
* be 8-byte aligned and the size should be
* GMAC_TX_UNITSIZE * wTxSize.
* \param pTxD Pointer to allocated TX descriptor list.
* \param pTxCb Pointer to allocated TX callback list.
* \param wTxSize TX size, in number of registered units (TX descriptors).
* \return GMACD_OK or GMACD_PARAM.
* \note If input address is not 8-byte aligned the address is automatically
* adjusted and the list size is reduced by one.
*/
uint8_t GMACD_InitTransfer( sGmacd *pGmacd,
uint8_t *pRxBuffer, sGmacRxDescriptor *pRxD,
uint16_t wRxSize,
uint8_t *pTxBuffer, sGmacTxDescriptor *pTxD, fGmacdTransferCallback *pTxCb,
uint16_t wTxSize)
{
Gmac *pHw = pGmacd->pHw;
if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM;
/* Assign RX buffers */
if ( ((uint32_t)pRxBuffer & 0x7)
|| ((uint32_t)pRxD & 0x7) )
{
wRxSize --;
TRACE_DEBUG("RX list address adjusted\n\r");
}
pGmacd->pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8);
pGmacd->pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8);
pGmacd->wRxListSize = wRxSize;
/* Assign TX buffers */
if ( ((uint32_t)pTxBuffer & 0x7)
|| ((uint32_t)pTxD & 0x7) )
{
wTxSize --;
TRACE_DEBUG("TX list address adjusted\n\r");
}
pGmacd->pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8);
pGmacd->pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8);
pGmacd->wTxListSize = wTxSize;
pGmacd->fTxCbList = pTxCb;
/* Reset TX & RX */
GMACD_ResetRx(pGmacd);
GMACD_ResetTx(pGmacd);
/* Enable Rx and Tx, plus the stats register. */
GMAC_TransmitEnable(pHw, 1);
GMAC_ReceiveEnable(pHw, 1);
GMAC_StatisticsWriteEnable(pHw, 1);
/* Setup the interrupts for TX (and errors) */
GMAC_EnableIt(pHw, GMAC_IER_MFS
|GMAC_IER_RCOMP
|GMAC_IER_RXUBR
|GMAC_IER_TXUBR
|GMAC_IER_TUR
|GMAC_IER_RLEX
|GMAC_IER_TFC
|GMAC_IER_TCOMP
|GMAC_IER_ROVR
|GMAC_IER_HRESP
|GMAC_IER_PFNZ
|GMAC_IER_PTZ
|GMAC_IER_PFTR
|GMAC_IER_EXINT
|GMAC_IER_DRQFR
|GMAC_IER_SFR
|GMAC_IER_DRQFT
|GMAC_IER_SFT
|GMAC_IER_PDRQFR
|GMAC_IER_PDRSFR
|GMAC_IER_PDRQFT
|GMAC_IER_PDRSFT);
//0x03FCFCFF
return GMACD_OK;
}