/** * \brief Initialize the GMAC with the Gmac controller address * \param pGmacd Pointer to GMAC Driver instance. * \param pHw Pointer to HW address for registers. * \param bID HW ID for power management * \param enableCAF Enable/Disable CopyAllFrame. * \param enableNBC Enable/Disable NoBroadCast. */ void GMACD_Init(sGmacd *pGmacd, Gmac *pHw, uint8_t bID, uint8_t enableCAF, uint8_t enableNBC ) { uint32_t dwNcfgr, dwDcfgr; /* Check parameters */ // assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX); TRACE_DEBUG("GMAC_Init\n\r"); /* Initialize struct */ pGmacd->pHw = pHw; pGmacd->bId = bID; /* Power ON */ PMC_EnablePeripheral(bID); /* Disable TX & RX and more */ GMAC_NetworkControl(pHw, 0); GMAC_DisableAllQueueIt(pHw, ~0u); GMAC_ClearStatistics(pHw); /* Clear all status bits in the receive status register. */ GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO); /* Clear all status bits in the transmit status register */ GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE | GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP | GMAC_TSR_UND | GMAC_TSR_HRESP ); /* Clear All interrupts */ GMAC_GetItStatus(pHw, GMAC_QUE_0); GMAC_GetItStatus(pHw, GMAC_QUE_1); GMAC_GetItStatus(pHw, GMAC_QUE_2); /* Enable the copy of data into the buffers ignore broadcasts, and don't copy FCS. */ dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_DBW(0) | GMAC_NCFGR_CLK_MCK_64; /* enable 1536 buffer */ // dwNcfgr |= GMAC_NCFGR_MAXFS; if( enableCAF ) { dwNcfgr |= GMAC_NCFGR_CAF; } if( enableNBC ) { dwNcfgr |= GMAC_NCFGR_NBC; } dwDcfgr = (GMAC_DCFGR_DRBS(8) | (0<<8) | (0<<10) ); GMAC_Configure(pHw, dwNcfgr); GMAC_DmaConfigure(pHw, dwDcfgr); }
/** * \brief Initialize the GMAC driver. * * \param p_gmac Pointer to the GMAC instance. * \param p_gmac_dev Pointer to the GMAC device instance. * \param p_opt GMAC configure options. */ void gmac_dev_init(Gmac* p_gmac, gmac_device_t* p_gmac_dev, gmac_options_t* p_opt) { /* Disable TX & RX and more */ gmac_network_control(p_gmac, 0); gmac_disable_interrupt(p_gmac, ~0u); gmac_clear_statistics(p_gmac); /* Clear all status bits in the receive status register. */ gmac_clear_rx_status(p_gmac, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA | GMAC_RSR_HNO); /* Clear all status bits in the transmit status register */ gmac_clear_tx_status(p_gmac, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE | GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP | GMAC_TSR_HRESP ); /* Enable the copy of data into the buffers ignore broadcasts, and not copy FCS. */ gmac_set_config(p_gmac, gmac_get_config(p_gmac) | GMAC_NCFGR_FD | GMAC_NCFGR_DBW(0) | GMAC_NCFGR_MAXFS | GMAC_NCFGR_RFCS | GMAC_NCFGR_PEN); gmac_enable_copy_all(p_gmac, p_opt->uc_copy_all_frame); gmac_disable_broadcast(p_gmac, p_opt->uc_no_boardcast); gmac_init_queue(p_gmac, p_gmac_dev); gmac_set_address(p_gmac, 0, p_opt->uc_mac_addr); #ifdef FREERTOS_USED /* Asynchronous operation requires a notification semaphore. First, * create the semaphore. */ vSemaphoreCreateBinary(netif_notification_semaphore); vQueueAddToRegistry(netif_notification_semaphore, "GMAC Sem"); /* Then set the semaphore into the correct initial state. */ xSemaphoreTake(netif_notification_semaphore, 0); #endif }