static void nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) { u32 magic[GPC_MAX][4]; u32 offset; int gpc; mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x408010, 0x80000000, 0, 0); mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x4064cc, 0x80000000, 0, 0); mmio_list(0x408004, 0x00000000, 8, 0); mmio_list(0x408008, 0x80000030, 0, 0); mmio_list(0x418808, 0x00000000, 8, 0); mmio_list(0x41880c, 0x80000030, 0, 0); mmio_list(0x4064c8, 0x01800600, 0, 0); mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x405830, 0x02180648, 0, 0); mmio_list(0x4064c4, 0x0192ffff, 0, 0); for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { u16 magic0 = 0x0218 * (priv->tpc_nr[gpc] - 1); u16 magic1 = 0x0648 * (priv->tpc_nr[gpc] - 1); u16 magic2 = 0x0218; u16 magic3 = 0x0648; magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; magic[gpc][1] = 0x00000000 | (magic1 << 16); offset += 0x0324 * (priv->tpc_nr[gpc] - 1); magic[gpc][2] = 0x10000000 | (magic2 << 16) | offset; magic[gpc][3] = 0x00000000 | (magic3 << 16); offset += 0x0324; } for (gpc = 0; gpc < priv->gpc_nr; gpc++) { mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); offset += 0x07ff * (priv->tpc_nr[gpc] - 1); mmio_list(GPC_UNIT(gpc, 0x32c0), magic[gpc][2], 0, 0); mmio_list(GPC_UNIT(gpc, 0x32e4), magic[gpc][3] | offset, 0, 0); offset += 0x07ff; } mmio_list(0x17e91c, 0x06060609, 0, 0); mmio_list(0x17e920, 0x00090a05, 0, 0); }
static void gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) { struct nvkm_device *device = gr->base.engine.subdev.device; nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); }
static void gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv) { int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { for (gpc = 0; gpc < priv->gpc_nr; gpc++) { if (tpc < priv->tpc_nr[gpc]) { nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); id++; } nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); } } }
static void nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) { u32 magic[GPC_MAX][2]; u32 offset; int gpc; mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); mmio_list(0x40800c, 0x00000000, 8, 1); mmio_list(0x408010, 0x80000000, 0, 0); mmio_list(0x419004, 0x00000000, 8, 1); mmio_list(0x419008, 0x00000000, 0, 0); mmio_list(0x408004, 0x00000000, 8, 0); mmio_list(0x408008, 0x80000018, 0, 0); mmio_list(0x418808, 0x00000000, 8, 0); mmio_list(0x41880c, 0x80000018, 0, 0); mmio_list(0x418810, 0x80000000, 12, 2); mmio_list(0x419848, 0x10000000, 12, 2); mmio_list(0x405830, 0x02180324, 0, 0); mmio_list(0x4064c4, 0x00c9ffff, 0, 0); for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { u16 magic0 = 0x0218 * priv->tpc_nr[gpc]; u16 magic1 = 0x0324 * priv->tpc_nr[gpc]; magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; magic[gpc][1] = 0x00000000 | (magic1 << 16); offset += 0x0324 * priv->tpc_nr[gpc]; } for (gpc = 0; gpc < priv->gpc_nr; gpc++) { mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); offset += 0x07ff * priv->tpc_nr[gpc]; } mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */ }
void gp102_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; const struct gf100_grctx_func *grctx = gr->func->grctx; const u32 alpha = grctx->alpha_nr; const u32 attrib = grctx->attrib_nr; const u32 pertpc = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); const u32 size = roundup(gr->tpc_total * pertpc, 0x80); const int s = 12; const int b = mmio_vram(info, size, (1 << s), false); const int max_batches = 0xffff; u32 ao = 0; u32 bo = ao + grctx->alpha_nr_max * gr->tpc_total; int gpc, ppc, n = 0; mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_refn(info, 0x419c2c, 0x10000000, s, b); mmio_refn(info, 0x419b00, 0x00000000, s, b); mmio_wr32(info, 0x419b04, 0x80000000 | size >> 7); mmio_wr32(info, 0x405830, attrib); mmio_wr32(info, 0x40585c, alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; const u32 u = 0x418ea0 + (n * 0x04); const u32 o = PPC_UNIT(gpc, ppc, 0); const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); if (!(gr->ppc_mask[gpc] & (1 << ppc))) continue; mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, p, bs); mmio_wr32(info, o + 0xf4, bo); mmio_wr32(info, o + 0xf0, bs); bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xf8, ao); ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, u, bs); } } mmio_wr32(info, 0x4181e4, 0x00000100); mmio_wr32(info, 0x41befc, 0x00000100); }
void gm200_grctx_generate_tpcid(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; int gpc, tpc, id; for (tpc = 0, id = 0; tpc < TPC_MAX_PER_GPC; tpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) { if (tpc < gr->tpc_nr[gpc]) { nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); id++; } } } }
int nve4_graph_init(struct nouveau_object *object) { struct nvc0_graph_oclass *oclass = (void *)object->oclass; struct nvc0_graph_priv *priv = (void *)object; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int ret, i; ret = nouveau_graph_init(&priv->base); if (ret) return ret; nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); nvc0_graph_mmio(priv, oclass->mmio); nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); for (i = 0, gpc = -1; i < priv->tpc_total; i++) { do { gpc = (gpc + 1) % priv->gpc_nr; } while (!tpcnr[gpc]); tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } nv_wr32(priv, GPC_BCAST(0x0980), data[0]); nv_wr32(priv, GPC_BCAST(0x0984), data[1]); nv_wr32(priv, GPC_BCAST(0x0988), data[2]); nv_wr32(priv, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); } nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); nv_wr32(priv, 0x400500, 0x00010001); nv_wr32(priv, 0x400100, 0xffffffff); nv_wr32(priv, 0x40013c, 0xffffffff); nv_wr32(priv, 0x409ffc, 0x00000000); nv_wr32(priv, 0x409c14, 0x00003e3e); nv_wr32(priv, 0x409c24, 0x000f0001); nv_wr32(priv, 0x404000, 0xc0000000); nv_wr32(priv, 0x404600, 0xc0000000); nv_wr32(priv, 0x408030, 0xc0000000); nv_wr32(priv, 0x404490, 0xc0000000); nv_wr32(priv, 0x406018, 0xc0000000); nv_wr32(priv, 0x407020, 0x40000000); nv_wr32(priv, 0x405840, 0xc0000000); nv_wr32(priv, 0x405844, 0x00ffffff); nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); } nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < priv->rop_nr; rop++) { nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); } nv_wr32(priv, 0x400108, 0xffffffff); nv_wr32(priv, 0x400138, 0xffffffff); nv_wr32(priv, 0x400118, 0xffffffff); nv_wr32(priv, 0x400130, 0xffffffff); nv_wr32(priv, 0x40011c, 0xffffffff); nv_wr32(priv, 0x400134, 0xffffffff); nv_wr32(priv, 0x400054, 0x34ce3464); return nvc0_graph_init_ctxctl(priv); }
int gm107_gr_init(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_fb *fb = device->fb; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int i; nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8); nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8); gf100_gr_mmio(gr, gr->func->mmio); gm107_gr_init_bios(gr); nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); for (i = 0, gpc = -1; i < gr->tpc_total; i++) { do { gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gr->tpc_total); nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); gr->func->init_rop_active_fbps(gr); nvkm_wr32(device, 0x400500, 0x00010001); nvkm_wr32(device, 0x400100, 0xffffffff); nvkm_wr32(device, 0x40013c, 0xffffffff); nvkm_wr32(device, 0x400124, 0x00000002); nvkm_wr32(device, 0x409c24, 0x000e0000); nvkm_wr32(device, 0x404000, 0xc0000000); nvkm_wr32(device, 0x404600, 0xc0000000); nvkm_wr32(device, 0x408030, 0xc0000000); nvkm_wr32(device, 0x404490, 0xc0000000); nvkm_wr32(device, 0x406018, 0xc0000000); nvkm_wr32(device, 0x407020, 0x40000000); nvkm_wr32(device, 0x405840, 0xc0000000); nvkm_wr32(device, 0x405844, 0x00ffffff); nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); gr->func->init_ppc_exceptions(gr); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < gr->rop_nr; rop++) { nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); } nvkm_wr32(device, 0x400108, 0xffffffff); nvkm_wr32(device, 0x400138, 0xffffffff); nvkm_wr32(device, 0x400118, 0xffffffff); nvkm_wr32(device, 0x400130, 0xffffffff); nvkm_wr32(device, 0x40011c, 0xffffffff); nvkm_wr32(device, 0x400134, 0xffffffff); nvkm_wr32(device, 0x400054, 0x2c350f63); gf100_gr_zbc_init(gr); return gf100_gr_init_ctxctl(gr); }
static void nve0_graph_gpc_trap(struct nvc0_graph_priv *priv) { const u32 mask = nv_rd32(priv, 0x400118); int gpc; for (gpc = 0; gpc < 4; ++gpc) { u32 stat; int tp; if (!(mask & (1 << gpc))) continue; stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); if (stat & 0x0001) { u32 trap[4]; int i; trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); nv_error(priv, "GPC%i/PROP trap:", gpc); for (i = 0; i <= 29; ++i) { if (!(trap[0] & (1 << i))) continue; pr_cont(" "); nouveau_enum_print(nve0_gpc_rop_error, i); } pr_cont("\n"); nv_error(priv, "x = %u, y = %u, " "format = %x, storage type = %x\n", trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, trap[3] & 0xff); nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); stat &= ~0x0001; } if (stat & 0x0002) { u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); nv_error(priv, "GPC%i/ZCULL trap: %08x\n", gpc, trap); nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); stat &= ~0x0002; } if (stat & 0x0004) { u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); nv_error(priv, "GPC%i/CCACHE trap: %08x\n", gpc, trap); nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); stat &= ~0x0004; } if (stat & 0x0008) { u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); nv_error(priv, "GPC%i/ESETUP trap %08x\n", gpc, trap); nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); stat &= ~0x0008; } for (tp = 0; tp < 8; ++tp) { if (stat & (1 << (16 + tp))) nve0_graph_tp_trap(priv, gpc, tp); } stat &= ~0xff0000; if (stat) { nv_error(priv, "GPC%i: unknown stat %08x\n", gpc, stat); } }
int gm204_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr_priv *priv = (void *)object; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; int ret, i; u32 tmp; ret = nvkm_gr_init(&priv->base); if (ret) return ret; tmp = nv_rd32(priv, 0x100c80); /*XXX: mask? */ nv_wr32(priv, 0x418880, 0x00001000 | (tmp & 0x00000fff)); nv_wr32(priv, 0x418890, 0x00000000); nv_wr32(priv, 0x418894, 0x00000000); nv_wr32(priv, 0x4188b4, priv->unk4188b4->addr >> 8); nv_wr32(priv, 0x4188b8, priv->unk4188b8->addr >> 8); nv_mask(priv, 0x4188b0, 0x00040000, 0x00040000); /*XXX: belongs in fb */ nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8); nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8); nv_mask(priv, 0x100cc4, 0x00040000, 0x00040000); gf100_gr_mmio(priv, oclass->mmio); gm107_gr_init_bios(priv); nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); for (i = 0, gpc = -1; i < priv->tpc_total; i++) { do { gpc = (gpc + 1) % priv->gpc_nr; } while (!tpcnr[gpc]); tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } nv_wr32(priv, GPC_BCAST(0x0980), data[0]); nv_wr32(priv, GPC_BCAST(0x0984), data[1]); nv_wr32(priv, GPC_BCAST(0x0988), data[2]); nv_wr32(priv, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); } nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); nv_wr32(priv, GPC_BCAST(0x033c), nv_rd32(priv, 0x100804)); nv_wr32(priv, 0x400500, 0x00010001); nv_wr32(priv, 0x400100, 0xffffffff); nv_wr32(priv, 0x40013c, 0xffffffff); nv_wr32(priv, 0x400124, 0x00000002); nv_wr32(priv, 0x409c24, 0x000e0000); nv_wr32(priv, 0x405848, 0xc0000000); nv_wr32(priv, 0x40584c, 0x00000001); nv_wr32(priv, 0x404000, 0xc0000000); nv_wr32(priv, 0x404600, 0xc0000000); nv_wr32(priv, 0x408030, 0xc0000000); nv_wr32(priv, 0x404490, 0xc0000000); nv_wr32(priv, 0x406018, 0xc0000000); nv_wr32(priv, 0x407020, 0x40000000); nv_wr32(priv, 0x405840, 0xc0000000); nv_wr32(priv, 0x405844, 0x00ffffff); nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < priv->rop_nr; rop++) { nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); } nv_wr32(priv, 0x400108, 0xffffffff); nv_wr32(priv, 0x400138, 0xffffffff); nv_wr32(priv, 0x400118, 0xffffffff); nv_wr32(priv, 0x400130, 0xffffffff); nv_wr32(priv, 0x40011c, 0xffffffff); nv_wr32(priv, 0x400134, 0xffffffff); nv_wr32(priv, 0x400054, 0x2c350f63); gf100_gr_zbc_init(priv); return gm204_gr_init_ctxctl(priv); }