/* Configure UART clock - based on the gsbi id */ void clock_config_uart_dm(uint8_t id) { /* Enable gsbi_uart_clk */ clock_config(UART_DM_CLK_NS_115200, UART_DM_CLK_MD_115200, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id)); /* Configure clock selection register for tx and rx rates. * Selecting 115.2k for both RX and TX. */ writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id)); /* Enable gsbi_pclk */ writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); }
/* Configure i2c clock */ void clock_config_i2c(uint8_t id, uint32_t freq) { uint32_t ns; uint32_t md; switch (freq) { case 24000000: ns = I2C_CLK_NS_24MHz; md = I2C_CLK_MD_24MHz; break; default: ASSERT(0); } clock_config(ns, md, GSBIn_QUP_APPS_NS(id), GSBIn_QUP_APPS_MD(id)); /* Enable the GSBI HCLK */ writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id)); }
void set_i2c_clk(struct qup_i2c_dev *dev) { uint32_t md = 0; uint32_t ns = 0; switch (dev->src_clk_freq) { case 24000000: ns = I2C_APPS_CLK_NS_24MHz; md = I2C_APPS_CLK_MD_24MHz; break; default: return; } /* Enable the GSBI8 HCLK */ writel((GSBI8_HCLK_CTL_CLK_ENA << GSBI8_HCLK_CTL_S), GSBIn_HCLK_CTL(dev->gsbi_number)); clock_config(ns, md, GSBIn_QUP_APPS_NS(dev->gsbi_number), GSBIn_QUP_APPS_MD(dev->gsbi_number)); }