static int gsc_src_set_addr(struct device *dev, struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, enum drm_exynos_ipp_buf_type buf_type) { struct gsc_context *ctx = get_gsc_context(dev); struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; struct drm_exynos_ipp_property *property; if (!c_node) { DRM_ERROR("failed to get c_node.\n"); return -EFAULT; } property = &c_node->property; DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", property->prop_id, buf_id, buf_type); if (buf_id > GSC_MAX_SRC) { dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); return -EINVAL; } /* address register set */ switch (buf_type) { case IPP_BUF_ENQUEUE: gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], GSC_IN_BASE_ADDR_Y(buf_id)); gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], GSC_IN_BASE_ADDR_CB(buf_id)); gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], GSC_IN_BASE_ADDR_CR(buf_id)); break; case IPP_BUF_DEQUEUE: gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id)); gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id)); gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id)); break; default: /* bypass */ break; } return gsc_src_set_buf_seq(ctx, buf_id, buf_type); }
void gsc_hw_set_input_addr(struct gsc_dev *dev, struct gsc_addr *addr, int index) { gsc_dbg("src_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X", index, addr->y, addr->cb, addr->cr); writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index)); writel(addr->cb, dev->regs + GSC_IN_BASE_ADDR_CB(index)); writel(addr->cr, dev->regs + GSC_IN_BASE_ADDR_CR(index)); }