void
obio_cfattach(struct device *parent, struct device *self, void *aux)
{
struct gt_softc * const gt = device_private(parent);
struct obio_softc *sc = device_private(self);
struct gt_attach_args *ga = aux;
uint32_t datal, datah;
GT_OBIOFOUND(gt, ga);
datal = bus_space_read_4(ga->ga_memt, ga->ga_memh,
obio_info[ga->ga_unit].low_decode);
datah = bus_space_read_4(ga->ga_memt, ga->ga_memh,
obio_info[ga->ga_unit].high_decode);
if (GT_LowAddr_GET(datal) > GT_HighAddr_GET(datah)) {
aprint_normal(": disabled\n");
return;
}
sc->sc_memt = obio_bs_tags[ga->ga_unit];
if (sc->sc_memt == NULL) {
aprint_normal(": unused\n");
return;
}
aprint_normal(": addr %#x-%#x, %s-endian\n",
GT_LowAddr_GET(datal), GT_HighAddr_GET(datah),
GT_PCISwap_GET(datal) == 1 ? "little" : "big");
config_search_ia(obio_cfsearch, &sc->sc_dev, "obio", NULL);
}
void
gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs,
struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi)
{
/* See how I/O space is configured. Read the base and top
* registers.
*/
paddr_t pbasel, pbaseh;
uint32_t datal, datah;
datal = gtpci_read(gtpc, lo);
datah = gtpci_read(gtpc, hi);
pbasel = GT_LowAddr_GET(datal);
pbaseh = GT_HighAddr_GET(datah);
/*
* If the start is greater than the end, ignore the region.
*/
if (pbaseh < pbasel)
return;
if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase
&& (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) {
bs->bs_regions[bs->bs_nregion].br_vbase =
gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask);
}
bs->bs_regions[bs->bs_nregion].br_pbase = pbasel;
if (bs->bs_flags & _BUS_SPACE_RELATIVE) {
bs->bs_regions[bs->bs_nregion].br_start = 0;
bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel;
} else {
bs->bs_regions[bs->bs_nregion].br_start = pbasel;
bs->bs_regions[bs->bs_nregion].br_end = pbaseh;
}
bs->bs_nregion++;
}
void
gtpci_bus_init(struct gtpci_chipset *gtpc)
{
const struct pci_init *pi;
uint32_t data, datal, datah;
pcireg_t pcidata;
int i;
/*
* disable all BARs to start.
*/
gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
0xffffffff);
#ifndef GT_PCI0_EXT_ARBITER
#define GT_PCI0_EXT_ARBITER 0
#endif
#ifndef GT_PCI1_EXT_ARBITER
#define GT_PCI1_EXT_ARBITER 0
#endif
if (gtpc->gtpc_host &&
((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) ||
(!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) {
/*
* Enable internal arbiter
*/
data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno));
data |= PCI_ARBCTL_EN;
gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data);
} else {
/*
* Make sure the internal arbiter is disabled
*/
gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0);
}
/*
* Make the GT reflects reality.
* We always enable internal memory.
*/
if (gtpc->gtpc_host) {
pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
0x20) & 0xfff;
gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 0x20,
GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) |
pcidata);
}
data = PCI_BARE_IntMemEn;
for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++)
gtpci_write(gtpc, pi->barsize, 0);
if (gtpc->gtpc_host) {
/*
* Enable bus master access (needed for config access).
*/
pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
PCI_COMMAND_STATUS_REG);
pcidata |= PCI_COMMAND_MASTER_ENABLE;
gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
PCI_COMMAND_STATUS_REG, pcidata);
}
/*
* Map each SCS BAR to correspond to each SDRAM decode register.
*/
for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) {
datal = gtpci_read(gtpc, pi->low_decode);
datah = gtpci_read(gtpc, pi->high_decode);
pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
pi->bar_regno);
gtpci_write(gtpc, pi->accctl_high, 0);
if (datal < datah) {
datal &= 0xfff;
pcidata &= 0xfff;
pcidata |= datal << 20;
data |= pi->bar_enable;
datah -= datal;
datal |= PCI_ACCCTLBASEL_PrefetchEn|
PCI_ACCCTLBASEL_RdPrefetch|
PCI_ACCCTLBASEL_RdLinePrefetch|
PCI_ACCCTLBASEL_RdMulPrefetch|
PCI_ACCCTLBASEL_WBurst_8_QW|
PCI_ACCCTLBASEL_PCISwap_NoSwap;
gtpci_write(gtpc, pi->accctl_low, datal);
} else {
pcidata &= 0xfff;
datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap;
datah = 0;
}
gtpci_write(gtpc, pi->barsize,
datah ? ((datah << 20) | 0xff000) : 0);
if (gtpc->gtpc_host) {
gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
pi->bar_regno, pcidata);
}
gtpci_write(gtpc, pi->accctl_low, datal);
gtpci_write(gtpc, pi->accctl_top, datah);
}
/*
* Now re-enable those BARs that are real.
*/
gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
~data);
if (gtpc->gtpc_host) {
/*
* Enable I/O and memory (bus master is already enabled) access.
*/
pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
PCI_COMMAND_STATUS_REG);
pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
PCI_COMMAND_STATUS_REG, pcidata);
}
}
void
gt_attach_common(struct gt_softc *gt)
{
uint32_t cpucfg, cpumode, cpumstr;
#ifdef DEBUG
uint32_t loaddr, hiaddr;
#endif
gtfound = 1;
cpumode = gt_read(gt, GT_CPU_Mode);
aprint_normal(": id %d", GT_CPUMode_MultiGTID_GET(cpumode));
if (cpumode & GT_CPUMode_MultiGT)
aprint_normal (" (multi)");
switch (GT_CPUMode_CPUType_GET(cpumode)) {
case 4: aprint_normal(", 60x bus"); break;
case 5: aprint_normal(", MPX bus"); break;
default: aprint_normal(", %#x(?) bus", GT_CPUMode_CPUType_GET(cpumode)); break;
}
cpumstr = gt_read(gt, GT_CPU_Master_Ctl);
cpumstr &= ~(GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock);
#if 0
cpumstr |= GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock;
#endif
gt_write(gt, GT_CPU_Master_Ctl, cpumstr);
switch (cpumstr & (GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock)) {
case 0: break;
case GT_CPUMstrCtl_CleanBlock: aprint_normal(", snoop=clean"); break;
case GT_CPUMstrCtl_FlushBlock: aprint_normal(", snoop=flush"); break;
case GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock:
aprint_normal(", snoop=clean&flush"); break;
}
aprint_normal(" wdog=%#x,%#x\n",
gt_read(gt, GT_WDOG_Config),
gt_read(gt, GT_WDOG_Value));
#if DEBUG
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS0_High_Decode));
aprint_normal("%s: scs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS1_High_Decode));
aprint_normal("%s: scs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS2_High_Decode));
aprint_normal("%s: scs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS3_High_Decode));
aprint_normal("%s: scs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS0_High_Decode));
aprint_normal("%s: cs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS1_High_Decode));
aprint_normal("%s: cs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS2_High_Decode));
aprint_normal("%s: cs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS3_High_Decode));
aprint_normal("%s: cs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_BootCS_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_BootCS_High_Decode));
aprint_normal("%s: bootcs=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_IO_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_IO_High_Decode));
aprint_normal("%s: pci0io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_IO_Remap);
aprint_normal("remap=%#010x\n", loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode));
aprint_normal("%s: pci0mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode));
aprint_normal("%s: pci0mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode));
aprint_normal("%s: pci0mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode));
aprint_normal("%s: pci0mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_IO_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_IO_High_Decode));
aprint_normal("%s: pci1io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_IO_Remap);
aprint_normal("remap=%#010x\n", loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode));
aprint_normal("%s: pci1mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode));
aprint_normal("%s: pci1mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode));
aprint_normal("%s: pci1mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode));
aprint_normal("%s: pci1mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_Internal_Decode));
aprint_normal("%s: internal=%#10x-%#10x\n", gt->gt_dev.dv_xname,
loaddr, loaddr+256*1024);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU0_High_Decode));
aprint_normal("%s: cpu0=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU1_High_Decode));
aprint_normal("%s: cpu1=%#10x-%#10x", gt->gt_dev.dv_xname, loaddr, hiaddr);
#endif
aprint_normal("%s:", gt->gt_dev.dv_xname);
cpucfg = gt_read(gt, GT_CPU_Cfg);
cpucfg |= GT_CPUCfg_ConfSBDis; /* per errata #46 */
cpucfg |= GT_CPUCfg_AACKDelay; /* per restriction #18 */
gt_write(gt, GT_CPU_Cfg, cpucfg);
if (cpucfg & GT_CPUCfg_Pipeline)
aprint_normal(" pipeline");
if (cpucfg & GT_CPUCfg_AACKDelay)
aprint_normal(" aack-delay");
if (cpucfg & GT_CPUCfg_RdOOO)
aprint_normal(" read-ooo");
if (cpucfg & GT_CPUCfg_IOSBDis)
aprint_normal(" io-sb-dis");
if (cpucfg & GT_CPUCfg_ConfSBDis)
aprint_normal(" conf-sb-dis");
if (cpucfg & GT_CPUCfg_ClkSync)
aprint_normal(" clk-sync");
aprint_normal("\n");
gt_init_hostid(gt);
gt_watchdog_init(gt);
gt_init_interrupt(gt);
#ifdef GT_ECC
gt_ecc_intr_enb(gt);
#endif
gt_comm_intr_enb(gt);
gt_devbus_intr_enb(gt);
gt_watchdog_disable();
config_search(gt_cfsearch, >->gt_dev, NULL);
gt_watchdog_service();
gt_watchdog_enable();
}