void Interpreter::dcbz_l(UGeckoInstruction inst)
{
if (!HID2.LCE)
{
GenerateProgramException();
return;
}
const u32 address = Helper_Get_EA_X(inst);
if (!HID0.DCE)
{
GenerateAlignmentException(address);
return;
}
// FAKE: clear memory instead of clearing the cache block
PowerPC::ClearCacheLine(address & (~31));
}
int Interpreter::SingleStepInner()
{
if (HandleFunctionHooking(PC))
{
UpdatePC();
return PPCTables::GetOpInfo(m_prev_inst)->numCycles;
}
#ifdef USE_GDBSTUB
if (gdb_active() && gdb_bp_x(PC))
{
Host_UpdateDisasmDialog();
gdb_signal(GDB_SIGTRAP);
gdb_handle_exception();
}
#endif
NPC = PC + sizeof(UGeckoInstruction);
m_prev_inst.hex = PowerPC::Read_Opcode(PC);
// Uncomment to trace the interpreter
// if ((PC & 0xffffff)>=0x0ab54c && (PC & 0xffffff)<=0x0ab624)
// startTrace = 1;
// else
// startTrace = 0;
if (startTrace)
{
Trace(m_prev_inst);
}
if (m_prev_inst.hex != 0)
{
if (IsInvalidPairedSingleExecution(m_prev_inst))
{
GenerateProgramException();
CheckExceptions();
}
else if (MSR.FP)
{
m_op_table[m_prev_inst.OPCD](m_prev_inst);
if (PowerPC::ppcState.Exceptions & EXCEPTION_DSI)
{
CheckExceptions();
}
}
else
{
// check if we have to generate a FPU unavailable exception or a program exception.
if (PPCTables::UsesFPU(m_prev_inst))
{
PowerPC::ppcState.Exceptions |= EXCEPTION_FPU_UNAVAILABLE;
CheckExceptions();
}
else
{
m_op_table[m_prev_inst.OPCD](m_prev_inst);
if (PowerPC::ppcState.Exceptions & EXCEPTION_DSI)
{
CheckExceptions();
}
}
}
}
else
{
// Memory exception on instruction fetch
CheckExceptions();
}
UpdatePC();
return PPCTables::GetOpInfo(m_prev_inst)->numCycles;
}
