std::string PPUThread::dump() const
{
std::string ret = "Registers:\n=========\n";
for (uint i = 0; i<32; ++i) ret += fmt::format("GPR[%d] = 0x%llx\n", i, GPR[i]);
for (uint i = 0; i<32; ++i) ret += fmt::format("FPR[%d] = %.6G\n", i, FPR[i]);
for (uint i = 0; i<32; ++i) ret += fmt::format("VR[%d] = 0x%s [%s]\n", i, VR[i].to_hex().c_str(), VR[i].to_xyzw().c_str());
ret += fmt::format("CR = 0x%08x\n", GetCR());
ret += fmt::format("LR = 0x%llx\n", LR);
ret += fmt::format("CTR = 0x%llx\n", CTR);
ret += fmt::format("XER = [CA=%u | OV=%u | SO=%u | CNT=%u]\n", u32{ CA }, u32{ OV }, u32{ SO }, u32{ XCNT });
//ret += fmt::format("FPSCR = 0x%x "
// "[RN=%d | NI=%d | XE=%d | ZE=%d | UE=%d | OE=%d | VE=%d | "
// "VXCVI=%d | VXSQRT=%d | VXSOFT=%d | FPRF=%d | "
// "FI=%d | FR=%d | VXVC=%d | VXIMZ=%d | "
// "VXZDZ=%d | VXIDI=%d | VXISI=%d | VXSNAN=%d | "
// "XX=%d | ZX=%d | UX=%d | OX=%d | VX=%d | FEX=%d | FX=%d]\n",
// FPSCR.FPSCR,
// u32{ FPSCR.RN },
// u32{ FPSCR.NI }, u32{ FPSCR.XE }, u32{ FPSCR.ZE }, u32{ FPSCR.UE }, u32{ FPSCR.OE }, u32{ FPSCR.VE },
// u32{ FPSCR.VXCVI }, u32{ FPSCR.VXSQRT }, u32{ FPSCR.VXSOFT }, u32{ FPSCR.FPRF },
// u32{ FPSCR.FI }, u32{ FPSCR.FR }, u32{ FPSCR.VXVC }, u32{ FPSCR.VXIMZ },
// u32{ FPSCR.VXZDZ }, u32{ FPSCR.VXIDI }, u32{ FPSCR.VXISI }, u32{ FPSCR.VXSNAN },
// u32{ FPSCR.XX }, u32{ FPSCR.ZX }, u32{ FPSCR.UX }, u32{ FPSCR.OX }, u32{ FPSCR.VX }, u32{ FPSCR.FEX }, u32{ FPSCR.FX });
return ret;
}
static u32 GetSpecialRegValue(int reg) {
switch (reg) {
case 0: return PowerPC::ppcState.pc;
case 1: return PowerPC::ppcState.spr[SPR_LR];
case 2: return PowerPC::ppcState.spr[SPR_CTR];
case 3: return GetCR();
case 4: return PowerPC::ppcState.fpscr;
case 5: return PowerPC::ppcState.msr;
case 6: return PowerPC::ppcState.spr[SPR_SRR0];
case 7: return PowerPC::ppcState.spr[SPR_SRR1];
case 8: return PowerPC::ppcState.Exceptions;
case 9: return ProcessorInterface::GetMask();
case 10: return ProcessorInterface::GetCause();
default: return 0;
}
}
u32 CRegTable::GetSpecialRegValue(int reg)
{
switch (reg)
{
case 0:
return PowerPC::ppcState.pc;
case 1:
return PowerPC::ppcState.spr[SPR_LR];
case 2:
return PowerPC::ppcState.spr[SPR_CTR];
case 3:
return GetCR();
case 4:
return PowerPC::ppcState.fpscr;
case 5:
return PowerPC::ppcState.msr;
case 6:
return PowerPC::ppcState.spr[SPR_SRR0];
case 7:
return PowerPC::ppcState.spr[SPR_SRR1];
case 8:
return PowerPC::ppcState.Exceptions;
case 9:
return ProcessorInterface::GetMask();
case 10:
return ProcessorInterface::GetCause();
case 11:
return PowerPC::ppcState.spr[SPR_DSISR];
case 12:
return PowerPC::ppcState.spr[SPR_DAR];
case 13:
return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base;
default:
return 0;
}
}
void displist() {
int x, y;
double z;
double x_min, x_max, y_min, y_max, z_min, z_max;
double a_in, a_out, a;
int xa_win, ya_win;
#define SCRDATA(a,x,y) a[(x)+(y)* xa_win]
struct Shade c, cs, cs_in, cs_out, cs_o;
double xv, yv, zv;
xa_win = ya_win = act;
std::unique_ptr<float[]> sr_buf(new float[xa_win * ya_win]);
std::unique_ptr<float[]> sg_buf(new float[xa_win * ya_win]);
std::unique_ptr<float[]> sb_buf(new float[xa_win * ya_win]);
/* Note, once rotation is possible, the
following code is no longer alpha simple loop */
InterDepth(&x_min, &x_max, &y_min, &y_max, &z_min, &z_max);
#if 0
glNewList(VOL_DATA,GL_COMPILE);
{
glBegin(GL_LINE_LOOP);
{
glColor3f(1.0,1.0,1.0);
glVertex2d(x_min,y_min);
glVertex2d(x_min,y_max);
glVertex2d(x_max,y_max);
glVertex2d(x_max,y_min);
}
glEnd();
}
glEndList();
return;
#endif
x_min += xa;
x_max += xa;
y_min += ya;
y_max += ya;
if (x_min < 0 || x_max > xa_win || y_min < 0 || y_max > ya_win) {
printf("ERROR!\n");
printf("x:%f,%f\n", x_min, x_max);
printf("y:%f,%f\n", y_min, y_max);
exit(-10);
}
for (y = y_min; y < y_max; y++) {
for (x = x_min; x < x_max; x++) {
cs_in.red = 0;
cs_in.green = 0;
cs_in.blue = 0;
cs_in.alpha = 0;
a_in = 0;
#if 0
printf("(%f,%f)(%d,%d)\n",(double)(x-xa) * x_size/xa_win,
(double)(y-ya) * vol_data.size_y()/ya_win,x,y);
#endif
for (z = z_min; z < z_max; z++) {
xv = (double) (x - xa) * (vol_data.size_x() - 1) / x_win;
yv = (double) (y - ya) * (vol_data.size_y() - 1) / y_win;
zv = (double) (z) * (vol_data.size_z() - 1) / z_win;
c = GetCR(xv, yv, zv);
/* if (c.alpha > 0)
{
printf("(%d,%d,%d):(%1.1f,%1.1f,%1.1f,%1.1f)\n",
x,y,z,c.red,c.green,c.blue,c.alpha);
}*/
cs.red = c.red * c.alpha;
cs.green = c.green * c.alpha;
cs.blue = c.blue * c.alpha;
a = c.alpha;
cs_o.red = cs.red * (1 - a_in);
cs_o.green = cs.green * (1 - a_in);
cs_o.blue = cs.blue * (1 - a_in);
cs_out = AddSh(cs_in, cs_o);
a_out = a_in + a * (1 - a_in);
a_in = a_out;
cs_in = cs_out;
if (a_out == 1) {
break;
}
}
cs.red = 0;
cs.green = 0;
cs.blue = 0;
a = 1;
cs_o.red = cs.red * (1 - a_in);
cs_o.green = cs.green * (1 - a_in);
cs_o.blue = cs.blue * (1 - a_in);
cs_out = AddSh(cs_in, cs_o);
a_out = a_in + a * (1 - a_in);
if (a_out > 0) {
c.red = cs_out.red / a_out;
c.green = cs_out.green / a_out;
c.blue = cs_out.blue / a_out;
} else {
c.red = 0;
c.green = 0;
c.blue = 0;
}
/* printf("(%d,%d):(%1.1f,%1.1f,%1.1f)\n",x,y,c.red,c.green,c.blue);*/
SCRDATA(sr_buf,x,y)=c.red;
SCRDATA(sg_buf,x,y)=c.green;
SCRDATA(sb_buf,x,y)=c.blue;
}
}
printf("Data complete \n");
glNewList(VOL_DATA, GL_COMPILE);
{
int xx, yy;
for (y = ((int) y_min) + 1; y < y_max; y++) {
yy = y - ya;
glBegin(GL_QUAD_STRIP);
{
for (x = x_min; x < x_max; x++) {
xx = x - xa;
glColor3f(SCRDATA(sr_buf,x,y-1),
SCRDATA(sg_buf,x,y-1),
SCRDATA(sb_buf,x,y-1));
glVertex2d(xx, yy - 1);
#if 0
printf("(%d,%d)(%d,%d)\n",xx,yy-1,x,y-1);
#endif
glColor3f(SCRDATA(sr_buf,x,y),
SCRDATA(sg_buf,x,y),
SCRDATA(sb_buf,x,y));
glVertex2d(xx, yy);
}
}
glEnd();
}
}
glEndList();
}
void RegisterWidget::PopulateTable()
{
for (int i = 0; i < 32; i++)
{
// General purpose registers (int)
AddRegister(i, 0, RegisterType::gpr, "r" + std::to_string(i), [i] { return GPR(i); },
[i](u64 value) { GPR(i) = value; });
// Floating point registers (double)
AddRegister(i, 2, RegisterType::fpr, "f" + std::to_string(i), [i] { return riPS0(i); },
[i](u64 value) { riPS0(i) = value; });
AddRegister(i, 4, RegisterType::fpr, "", [i] { return riPS1(i); },
[i](u64 value) { riPS1(i) = value; });
}
for (int i = 0; i < 8; i++)
{
// IBAT registers
AddRegister(i, 5, RegisterType::ibat, "IBAT" + std::to_string(i),
[i] {
return (static_cast<u64>(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2]) << 32) +
PowerPC::ppcState.spr[SPR_IBAT0L + i * 2];
},
nullptr);
// DBAT registers
AddRegister(i + 8, 5, RegisterType::dbat, "DBAT" + std::to_string(i),
[i] {
return (static_cast<u64>(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2]) << 32) +
PowerPC::ppcState.spr[SPR_DBAT0L + i * 2];
},
nullptr);
// Graphics quantization registers
AddRegister(i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i),
[i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr);
}
for (int i = 0; i < 16; i++)
{
// SR registers
AddRegister(i, 7, RegisterType::sr, "SR" + std::to_string(i),
[i] { return PowerPC::ppcState.sr[i]; },
[i](u64 value) { PowerPC::ppcState.sr[i] = value; });
}
// Special registers
// TB
AddRegister(16, 5, RegisterType::tb, "TB",
[] {
return static_cast<u64>(PowerPC::ppcState.spr[SPR_TU]) << 32 |
PowerPC::ppcState.spr[SPR_TL];
},
nullptr);
// PC
AddRegister(17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; },
[](u64 value) { PowerPC::ppcState.pc = value; });
// LR
AddRegister(18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; });
// CTR
AddRegister(19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; });
// CR
AddRegister(20, 5, RegisterType::cr, "CR", [] { return GetCR(); },
[](u64 value) { SetCR(value); });
// XER
AddRegister(21, 5, RegisterType::xer, "XER", [] { return GetXER().Hex; },
[](u64 value) { SetXER(UReg_XER(value)); });
// FPSCR
AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr; },
[](u64 value) { PowerPC::ppcState.fpscr = value; });
// MSR
AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr; },
[](u64 value) { PowerPC::ppcState.msr = value; });
// SRR 0-1
AddRegister(24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; });
AddRegister(25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; });
// Exceptions
AddRegister(26, 5, RegisterType::exceptions, "Exceptions",
[] { return PowerPC::ppcState.Exceptions; },
[](u64 value) { PowerPC::ppcState.Exceptions = value; });
// Int Mask
AddRegister(27, 5, RegisterType::int_mask, "Int Mask",
[] { return ProcessorInterface::GetMask(); }, nullptr);
// Int Cause
AddRegister(28, 5, RegisterType::int_cause, "Int Cause",
[] { return ProcessorInterface::GetCause(); }, nullptr);
// DSISR
AddRegister(29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; });
// DAR
AddRegister(30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; },
[](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; });
// Hash Mask
AddRegister(
31, 5, RegisterType::pt_hashmask, "Hash Mask",
[] { return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base; },
nullptr);
emit RequestTableUpdate();
m_table->resizeColumnsToContents();
}
