bool wxExViMacros::SetRegister(const char name, const std::string& value)
{
if (!isalnum(name) && !isdigit(name) &&
name != '%' && name != '_' && name != '*' && name != '.')
{
return false;
}
if (name == '*')
{
wxExClipboardAdd(value);
return true;
}
std::vector<std::string> v;
// The black hole register, everything written to it is discarded.
if (name != '_')
{
if (wxIsupper(name))
{
v.emplace_back(GetRegister(tolower(name)) + value);
}
else
{
v.emplace_back(value);
}
}
m_Macros[std::string(1, (char)tolower(name))] = v;
m_IsModified = true;
return true;
}
void CPU::Reset()
{
Stop();
_interpreter = std::unique_ptr<Interpreter>(new Interpreter(this));
_memory = std::unique_ptr<MMU>(new MMU(this));
_gpu = std::unique_ptr<GPU>(new GPU(this));
_dma = std::unique_ptr<DMA>(new DMA(this));
// Zero-out all the registers
_state.Registers = { };
_state.Registers_FIQ = { };
_state.Registers_svc = { };
_state.Registers_abt = { };
_state.Registers_IRQ = { };
_state.Registers_und = { };
_state.CPSR.Full = 0;
// The GBA boots in System mode
SetCurrentCPUMode(CPUMode::System);
GetRegister(PC) = 0x8000000; // Default entry point
_cycles = 0;
}
/* virtual */ void TownScopeResolver::StorePSA(uint pos, int32 value)
{
if (this->readonly) return;
assert(this->t != NULL);
/* We can't store anything if the caller has no #GRFFile. */
if (this->ro->grffile == NULL) return;
/* Check the persistent storage for the GrfID stored in register 100h. */
uint32 grfid = GetRegister(0x100);
/* A NewGRF can only write in the persistent storage associated to its own GRFID. */
if (grfid == 0xFFFFFFFF) grfid = this->ro->grffile->grfid;
if (grfid != this->ro->grffile->grfid) return;
/* Check if the storage exists. */
std::list<PersistentStorage *>::iterator iter;
for (iter = t->psa_list.begin(); iter != t->psa_list.end(); iter++) {
if ((*iter)->grfid == grfid) {
(*iter)->StoreValue(pos, value);
return;
}
}
/* Create a new storage. */
assert(PersistentStorage::CanAllocateItem());
PersistentStorage *psa = new PersistentStorage(grfid);
psa->StoreValue(pos, value);
t->psa_list.push_back(psa);
}
bool VIRTUALMACHINE::step(bool skip)
{
bool result= false;
VMREGTYPE ip= 0;
OPCODE opcode;
if(GetRegister(IP,ip)
&& GetInstruction((VPVOID)ip,opcode)
&& opcode)
{
INSTRUCTIONMAP::iterator it= instructions.find(opcode);
if(it!=instructions.end())
{
INSTRUCTION* inst= it->second;
int operandlength= inst->GetOperands(opcode,(VPVOID)ip+sizeof(opcode));
if(operandlength>=0)
{
ip+= sizeof(opcode)+operandlength;
if(SetRegister(IP,(VMREGTYPE)ip))
{
result= skip || inst->execute();
}
}
}
else
{
BadOpcodeHandler(opcode,(VPVOID)ip);
}
}
return result;
}
BOOLEAN
GetAddress(
IN PUCHAR String,
IN PFW_EXCEPTION_FRAME Frame,
OUT PULONG Address
)
/*++
Routine Description:
This routine converts an ascii string to an address. The string
is the form:
[@reg | value]
Arguments:
String - Null terminated string that contains the address to convert.
Frame - Address of the exception frame that was passed to Monitor.
Address - Supplies a pointer to where the converted address is stored
Return Value:
Returns TRUE if the string can be converted.
FALSE otherwise.
--*/
{
PUCHAR Terminator;
UCHAR Delimiter;
REGISTER_NAME_ID RegId;
if (*String == '@') {
String++; // skip @
if ((RegId = GetRegister(String)) == invalidregister) {
FwPrint(String);
FwPrint(MON_INVALID_REGISTER_MSG);
return FALSE;
} else {
//
// This is a hack to treat the structure as an array. It
// should have been an array to begin with. RegId is an
// index into the "array".
//
*Address = ((PULONGLONG)Frame)[RegId];
}
} else {
*Address=strtoul(String,&Terminator,16);
if (*Terminator != '\0') {
//
// Not the whole string was converted.
//
FwPrint(Terminator);
FwPrint(MON_NOT_VALID_ADDRESS_MSG);
return FALSE;
}
}
return TRUE;
}
int main()
{
const char *p = "add [ebp-02h], 20";
ASM_DATA *asms = CreateAsmData();
GetOpcode(&p);
GetRegister(&p, &(asms->registers[0]));
}
void CMorphAutomatBuilder::UnregisterNode(CTrieNodeBuild* pNode)
{
if (pNode->m_bRegistered)
{
pNode->m_bRegistered = false;
GetRegister(pNode).erase(pNode->m_pRegister);
RegisterSize --;
};
};
//BeforeEmit : generate any code needed before the main emittion begins (other register allocators may have emited code tho)
virtual void BeforeEmit()
{
for (int i=0;i<16;i++)
{
if (IsRegAllocated(i))
{
GetRegister(EAX,i,RA_DEFAULT);
}
}
}
size_t const RegisterAdmin::GetRegister(const Symbol* const pSym)
{
assert(mpProl16Gen != 0);
if (pSym == 0) {
// return unused register
return GetRegister();
}
if (mRegList.size() > 0) {
// search register assigned to pSym
tRegList::const_iterator itor = mRegList.begin();
for (; itor != mRegList.end(); itor++) {
if (itor->second == pSym) {
// return assigned register
return itor->first;
}
}
}
// if not found allocate new (unused) register and load value
size_t addrRegNr = 0;
size_t regNr = GetRegister();
switch (pSym->GetType()) {
case Symbol::eConst:
// load register with immediate value
mpProl16Gen->LoadI(regNr, *((ConstSym*)pSym)->GetVal());
break;
case Symbol::eVar:
addrRegNr = GetRegister();
// load address register with address
mpProl16Gen->LoadI(addrRegNr, ((VarSym*)pSym)->GetAddr());
mpProl16Gen->Load(regNr, addrRegNr);
FreeRegister(addrRegNr);
break;
default:
assert(false);
break;
}
// assign register
AssignRegister(regNr, pSym);
return regNr;
}
int main(void)
{
//init_USART();
init_SPI();
init_ster();
lcd_init();
LCD_DISPLAY(LCDDISPLAY);
lcd_puts("KAROL");
if(GetRegister(STATUS) == 0x0E)
{
LED_ON;
_delay_ms(1000);
LED_OFF;
_delay_ms(1000);
}
LCD_CLEAR;
NRF24L01_init();
while(1)
{
reset();
receive_payload();
if(((GetRegister(STATUS) & (1<<RX_DR)) != 0))
{
LED_ON;
_delay_ms(10);
//LCD_CLEAR;
receive_buffer=WriteReadToNrf(R,R_RX_PAYLOAD,receive_buffer,5);
X_acc=receive_buffer[0];
Y_acc=receive_buffer[1];
Z_acc=receive_buffer[2];
ster(X_acc,Y_acc);
LCD_LOCATE(0,0);
sprintf(Text_buff,"%3d",X_acc);
lcd_puts(Text_buff);
LCD_LOCATE(0,1);
sprintf(Text_buff,"%3d",Y_acc);
lcd_puts(Text_buff);
LED_OFF;
}
}
}
//BeforeEmit : generate any code needed before the main emittion begins (other register allocators may have emited code tho)
virtual void BeforeEmit()
{
for (int i=0; i<16; i++)
{
if (IsRegAllocated(i+fr_0))
{
GetRegister(XMM0,i+fr_0,RA_DEFAULT);
}
}
}
void CPU::Step()
{
// Update the DMA channels
_dma->Step();
std::shared_ptr<Instruction> instruction;
if (GetCurrentInstructionSet() == InstructionSet::ARM)
{
uint32_t opcode = _memory->ReadUInt32(GetRegister(PC)); // Read the opcode from memory, 4 bytes in ARM mode
GetRegister(PC) += 4; // Increment the PC 4 bytes
// Extract the instruction from it
instruction = _decoder->DecodeARM(opcode);
}
else
{
uint16_t opcode = _memory->ReadUInt16(GetRegister(PC)); // Read the opcode from memory, 2 bytes in Thumb mode
GetRegister(PC) += 2; // Increment the PC 2 bytes
// Extract the instruction from it
instruction = _decoder->DecodeThumb(opcode);
}
ExecuteInstructionCallback(InstructionCallbackTypes::InstructionDecoded, instruction);
if (instruction)
{
_interpreter->RunInstruction(instruction);
_cycles += instruction->GetTiming();
ExecuteInstructionCallback(InstructionCallbackTypes::InstructionExecuted, instruction);
}
else
std::cout << "Unknown Instruction" << std::endl;
// Update the GPU
GetGPU()->Step(_cycles);
// Check for interrupts on every loop
ProcessInterrupts();
}
/**
* Resolve the sprites for custom station foundations.
* @param statspec Station spec
* @param st Station
* @param tile Station tile being drawn
* @param layout Spritelayout as returned by previous callback
* @param edge_info Information about northern tile edges; whether they need foundations or merge into adjacent tile's foundations.
* @return First sprite of a set of foundation sprites for various slopes, or 0 if default foundations shall be drawn.
*/
SpriteID GetCustomStationFoundationRelocation(const StationSpec *statspec, BaseStation *st, TileIndex tile, uint layout, uint edge_info)
{
/* callback_param1 == 2 means we are resolving the foundation sprites. */
StationResolverObject object(statspec, st, tile, CBID_NO_CALLBACK, 2, layout | (edge_info << 16));
const SpriteGroup *group = object.Resolve();
if (group == NULL || group->type != SGT_RESULT) return 0;
/* Note: SpriteGroup::Resolve zeroes all registers, so register 0x100 is initialised to 0. (compatibility) */
return group->GetResult() + GetRegister(0x100);
}
bool VIRTUALMACHINE::pop(VMFLOAT& val)
{
bool result= false;
VMREGTYPE sp= 0;
if(GetRegister(SP,sp))
{
if(SetRegister(SP,sp+sizeof(VMREGTYPE)))
result= ReadMem((VPVOID)sp,&val,sizeof(val));
}
return result;
}
SpriteID GetCustomStationFoundationRelocation(const StationSpec *statspec, const BaseStation *st, TileIndex tile)
{
const SpriteGroup *group;
ResolverObject object;
NewStationResolver(&object, statspec, st, tile);
object.callback_param1 = 2; // Indicate we are resolving the foundation sprites
group = ResolveStation(&object);
if (group == NULL || group->type != SGT_RESULT) return 0;
return group->GetResult() + GetRegister(0x100);
}
virtual void SaveRegister(u32 reg,u32 from)
{
checkvr(reg);
if (!IsRegAllocated(reg))
{
x86e->Emit(op_mov32,GetRegPtr(reg),from);
}
else
{
x86_gpr_reg x86reg=GetRegister(EAX,reg,RA_NODATA);
x86e->Emit(op_mov32,x86reg,from);
}
MarkDirty(reg);
}
// Because GLSL doesn't let me specify registers for samplers
// the way HLSL does, I bind them all to preset names here.
void GL2ShaderProgram::SetSamplerUniforms()
{
glUseProgram( m_ShaderProgram );
for( uint SamplerStage = 0; SamplerStage < MAX_TEXTURE_STAGES; ++SamplerStage )
{
const HashedString TextureName = SimpleString::PrintF( "Texture%d", SamplerStage );
uint Register;
if( GetRegister( TextureName, Register ) )
{
glUniform1i( Register, SamplerStage );
}
}
}
void CPU::TriggerInterrupt(InterruptTypes type)
{
std::swap(GetRegisterForMode(CPUMode::IRQ, SP), GetRegister(SP));
std::swap(GetRegisterForMode(CPUMode::IRQ, LR), GetRegister(LR));
// Save the CPSR into SPSR_irq
_state.SPSR[2] = GetCurrentStatusRegister();
// Disable interrupts
GetCurrentStatusFlags().I = 1;
// Setup the return address
GetRegisterForMode(CPUMode::IRQ, LR) = PC + (GetCurrentInstructionSet() == InstructionSet::ARM ? 4 : 2);
// Set IRQ mode
SetCurrentCPUMode(CPUMode::IRQ);
// Switch to ARM mode
SetInstructionSet(InstructionSet::ARM);
// Jump to the BIOS IRQ handler
GetRegister(PC) = 0x18;
}
bool VIRTUALMACHINE::push(VMFLOAT val)
{
bool result= false;
VMREGTYPE sp= 0;
if(GetRegister(SP,sp))
{
sp-= sizeof(VMREGTYPE);
if(SetRegister(SP,sp))
{
SetFlags(val);
result= WriteMem((VPVOID)sp,&val,sizeof(val));
}
}
return result;
}
std::string Thumb::LoadStoreMultipleInstruction::ToString() const
{
std::stringstream stream;
stream << Thumb::ToString(GetOpcode()) << " R" << GetRegister() << "!, {" ;
std::bitset<8> registersBits(GetRegisterList());
while (registersBits.count() > 0)
{
uint8_t bitIndex = 0;
for (; bitIndex < 8 && !registersBits.test(bitIndex); ++bitIndex);
stream << "R" << +bitIndex;
registersBits[bitIndex] = false;
if (registersBits.count() != 0)
stream << ", ";
}
stream << "}";
return stream.str();
}
CTrieNodeBuild* CMorphAutomatBuilder::ReplaceOrRegister(CTrieNodeBuild* pNode)
{
CTrieRegister& Register = GetRegister(pNode);
CTrieRegister::const_iterator it = Register.find(pNode);
if (it != Register.end())
{
DeleteNode(pNode);
pNode = *it;
assert (pNode->m_bRegistered);
assert (pNode->m_pRegister == it);
}
else
{
pNode->m_pRegister = Register.insert(pNode).first;
pNode->m_bRegistered = true;
RegisterSize++;
}
return pNode;
};
virtual void LoadRegisterGPR(x86_gpr_reg to,u32 from)
{
if (IsRegAllocated(from))
{
fprinfo* r1= GetInfo(from);
if ((x86_caps.sse_2) && (r1->Loaded==true) && (r1->WritenBack==false))
{
x86_sse_reg freg=GetRegister(XMM0,from,RA_DEFAULT);
assert(freg!=XMM0);
x86e->Emit(op_movd_xmm_to_r32,to,freg);
}
else
{
WriteBackRegister(from);
x86e->Emit(op_mov32,to,GetRegPtr(from));
}
}
else
{
x86e->Emit(op_mov32,to,GetRegPtr(from));
}
}
virtual void SaveRegisterGPR(u32 to,x86_gpr_reg from)
{
if (IsRegAllocated(to))
{
if (x86_caps.sse_2)
{
x86_sse_reg freg=GetRegister(XMM0,to,RA_NODATA);
assert(freg!=XMM0);
//x86e->Emit(op_int3);
//x86e->SSE2_MOVD_32R_to_XMM(freg,from);
x86e->Emit(op_movd_xmm_from_r32,freg,from);
}
else
{
x86e->Emit(op_mov32,GetRegPtr(to),from);
ReloadRegister(to);
}
}
else
{
x86e->Emit(op_mov32,GetRegPtr(to),from);
}
}
/**
* Handles the getregisters sub-command.
*
* @returns Suitable exit code.
* @param pArgs The handler arguments.
* @param pDebugger Pointer to the debugger interface.
*/
static RTEXITCODE handleDebugVM_GetRegisters(HandlerArg *pArgs, IMachineDebugger *pDebugger)
{
/*
* We take a list of register names (case insensitive). If 'all' is
* encountered we'll dump all registers.
*/
ULONG idCpu = 0;
unsigned cRegisters = 0;
RTGETOPTSTATE GetState;
RTGETOPTUNION ValueUnion;
static const RTGETOPTDEF s_aOptions[] =
{
{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
};
int rc = RTGetOptInit(&GetState, pArgs->argc, pArgs->argv, s_aOptions, RT_ELEMENTS(s_aOptions), 2, RTGETOPTINIT_FLAGS_OPTS_FIRST);
AssertRCReturn(rc, RTEXITCODE_FAILURE);
while ((rc = RTGetOpt(&GetState, &ValueUnion)) != 0)
{
switch (rc)
{
case 'c':
idCpu = ValueUnion.u32;
break;
case VINF_GETOPT_NOT_OPTION:
if (!RTStrICmp(ValueUnion.psz, "all"))
{
com::SafeArray<BSTR> aBstrNames;
com::SafeArray<BSTR> aBstrValues;
CHECK_ERROR2I_RET(pDebugger, GetRegisters(idCpu, ComSafeArrayAsOutParam(aBstrNames),
ComSafeArrayAsOutParam(aBstrValues)),
RTEXITCODE_FAILURE);
Assert(aBstrNames.size() == aBstrValues.size());
size_t cchMaxName = 8;
for (size_t i = 0; i < aBstrNames.size(); i++)
{
size_t cchName = RTUtf16Len(aBstrNames[i]);
if (cchName > cchMaxName)
cchMaxName = cchName;
}
for (size_t i = 0; i < aBstrNames.size(); i++)
RTPrintf("%-*ls = %ls\n", cchMaxName, aBstrNames[i], aBstrValues[i]);
}
else
{
com::Bstr bstrName = ValueUnion.psz;
com::Bstr bstrValue;
CHECK_ERROR2I_RET(pDebugger, GetRegister(idCpu, bstrName.raw(), bstrValue.asOutParam()), RTEXITCODE_FAILURE);
RTPrintf("%s = %ls\n", ValueUnion.psz, bstrValue.raw());
}
cRegisters++;
break;
default:
return errorGetOpt(rc, &ValueUnion);
}
}
if (!cRegisters)
return errorSyntax("The getregisters sub-command takes at least one register name");
return RTEXITCODE_SUCCESS;
}
static void HandleMemSingle( data32_t insn )
{
data32_t rn, rnv, off, rd;
/* Fetch the offset */
if (insn & INSN_I)
{
off = decodeShift(insn, NULL);
}
else
{
off = insn & INSN_SDT_IMM;
}
/* Calculate Rn, accounting for PC */
rn = (insn & INSN_RN) >> INSN_RN_SHIFT;
// if (rn==0xf) logerror("%08x: Source R15\n",R15);
if (insn & INSN_SDT_P)
{
/* Pre-indexed addressing */
if (insn & INSN_SDT_U)
{
rnv = (GetRegister(rn) + off);
}
else
{
rnv = (GetRegister(rn) - off);
}
if (insn & INSN_SDT_W)
{
SetRegister(rn,rnv);
//check writeback???
}
else if (rn == eR15)
{
rnv = (rnv & ADDRESS_MASK) + 8;
}
}
else
{
/* Post-indexed addressing */
if (rn == eR15)
{
rnv = (R15 & ADDRESS_MASK) + 8;
}
else
{
rnv = GetRegister(rn);
}
}
/* Do the transfer */
rd = (insn & INSN_RD) >> INSN_RD_SHIFT;
if (insn & INSN_SDT_L)
{
/* Load */
if (insn & INSN_SDT_B)
{
SetRegister(rd,(data32_t) READ8(rnv));
}
else
{
if (rd == eR15)
{
if (ARM_DEBUG_CORE)
logerror("%08x: LDR to R15\n",R15);
R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK);
R15 -= 4;
}
else
{
SetRegister(rd,READ32(rnv));
}
}
}
else
{
/* Store */
if (insn & INSN_SDT_B)
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in byte mode\n");
WRITE8(rnv, (data8_t) GetRegister(rd) & 0xffu);
}
else
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in 32bit mode\n");
WRITE32(rnv, rd == eR15 ? R15 + 8 : GetRegister(rd));
}
}
/* Do post-indexing writeback */
if (!(insn & INSN_SDT_P)/* && (insn&INSN_SDT_W)*/)
{
if (insn & INSN_SDT_U)
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn) {
SetRegister(rn,GetRegister(rd));
//todo: check for offs... ?
}
else {
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
SetRegister(rn,(rnv + off));
}
}
else
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn) {
SetRegister(rn,GetRegister(rd));
// logerror("Arm %08x: LDR style with rn==rn\n",R15);
}
else {
SetRegister(rn,(rnv - off));
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackDecrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
}
}
}
// arm_check_irq_state()
} /* HandleMemSingle */
unsigned arm_get_sp(void)
{
return GetRegister(13);
}
/* virtual */ uint32 TownScopeResolver::GetVariable(byte variable, uint32 parameter, bool *available) const
{
switch (variable) {
/* Larger towns */
case 0x40:
if (_settings_game.economy.larger_towns == 0) return 2;
if (this->t->larger_town) return 1;
return 0;
/* Town index */
case 0x41: return this->t->index;
/* Get a variable from the persistent storage */
case 0x7C: {
/* Check the persistent storage for the GrfID stored in register 100h. */
uint32 grfid = GetRegister(0x100);
if (grfid == 0xFFFFFFFF) {
if (this->ro->grffile == NULL) return 0;
grfid = this->ro->grffile->grfid;
}
std::list<PersistentStorage *>::iterator iter;
for (iter = this->t->psa_list.begin(); iter != this->t->psa_list.end(); iter++) {
if ((*iter)->grfid == grfid) return (*iter)->GetValue(parameter);
}
return 0;
}
/* Town properties */
case 0x80: return this->t->xy;
case 0x81: return GB(this->t->xy, 8, 8);
case 0x82: return ClampToU16(this->t->cache.population);
case 0x83: return GB(ClampToU16(this->t->cache.population), 8, 8);
case 0x8A: return this->t->grow_counter;
case 0x92: return this->t->flags; // In original game, 0x92 and 0x93 are really one word. Since flags is a byte, this is to adjust
case 0x93: return 0;
case 0x94: return ClampToU16(this->t->cache.squared_town_zone_radius[0]);
case 0x95: return GB(ClampToU16(this->t->cache.squared_town_zone_radius[0]), 8, 8);
case 0x96: return ClampToU16(this->t->cache.squared_town_zone_radius[1]);
case 0x97: return GB(ClampToU16(this->t->cache.squared_town_zone_radius[1]), 8, 8);
case 0x98: return ClampToU16(this->t->cache.squared_town_zone_radius[2]);
case 0x99: return GB(ClampToU16(this->t->cache.squared_town_zone_radius[2]), 8, 8);
case 0x9A: return ClampToU16(this->t->cache.squared_town_zone_radius[3]);
case 0x9B: return GB(ClampToU16(this->t->cache.squared_town_zone_radius[3]), 8, 8);
case 0x9C: return ClampToU16(this->t->cache.squared_town_zone_radius[4]);
case 0x9D: return GB(ClampToU16(this->t->cache.squared_town_zone_radius[4]), 8, 8);
case 0x9E: return this->t->ratings[0];
case 0x9F: return GB(this->t->ratings[0], 8, 8);
case 0xA0: return this->t->ratings[1];
case 0xA1: return GB(this->t->ratings[1], 8, 8);
case 0xA2: return this->t->ratings[2];
case 0xA3: return GB(this->t->ratings[2], 8, 8);
case 0xA4: return this->t->ratings[3];
case 0xA5: return GB(this->t->ratings[3], 8, 8);
case 0xA6: return this->t->ratings[4];
case 0xA7: return GB(this->t->ratings[4], 8, 8);
case 0xA8: return this->t->ratings[5];
case 0xA9: return GB(this->t->ratings[5], 8, 8);
case 0xAA: return this->t->ratings[6];
case 0xAB: return GB(this->t->ratings[6], 8, 8);
case 0xAC: return this->t->ratings[7];
case 0xAD: return GB(this->t->ratings[7], 8, 8);
case 0xAE: return this->t->have_ratings;
case 0xB2: return this->t->statues;
case 0xB6: return ClampToU16(this->t->cache.num_houses);
case 0xB9: return this->t->growth_rate & (~TOWN_GROW_RATE_CUSTOM);
case 0xBA: return ClampToU16(this->t->supplied[CT_PASSENGERS].new_max);
case 0xBB: return GB(ClampToU16(this->t->supplied[CT_PASSENGERS].new_max), 8, 8);
case 0xBC: return ClampToU16(this->t->supplied[CT_MAIL].new_max);
case 0xBD: return GB(ClampToU16(this->t->supplied[CT_MAIL].new_max), 8, 8);
case 0xBE: return ClampToU16(this->t->supplied[CT_PASSENGERS].new_act);
case 0xBF: return GB(ClampToU16(this->t->supplied[CT_PASSENGERS].new_act), 8, 8);
case 0xC0: return ClampToU16(this->t->supplied[CT_MAIL].new_act);
case 0xC1: return GB(ClampToU16(this->t->supplied[CT_MAIL].new_act), 8, 8);
case 0xC2: return ClampToU16(this->t->supplied[CT_PASSENGERS].old_max);
case 0xC3: return GB(ClampToU16(this->t->supplied[CT_PASSENGERS].old_max), 8, 8);
case 0xC4: return ClampToU16(this->t->supplied[CT_MAIL].old_max);
case 0xC5: return GB(ClampToU16(this->t->supplied[CT_MAIL].old_max), 8, 8);
case 0xC6: return ClampToU16(this->t->supplied[CT_PASSENGERS].old_act);
case 0xC7: return GB(ClampToU16(this->t->supplied[CT_PASSENGERS].old_act), 8, 8);
case 0xC8: return ClampToU16(this->t->supplied[CT_MAIL].old_act);
case 0xC9: return GB(ClampToU16(this->t->supplied[CT_MAIL].old_act), 8, 8);
case 0xCA: return this->t->GetPercentTransported(CT_PASSENGERS);
case 0xCB: return this->t->GetPercentTransported(CT_MAIL);
case 0xCC: return this->t->received[TE_FOOD].new_act;
case 0xCD: return GB(this->t->received[TE_FOOD].new_act, 8, 8);
case 0xCE: return this->t->received[TE_WATER].new_act;
case 0xCF: return GB(this->t->received[TE_WATER].new_act, 8, 8);
case 0xD0: return this->t->received[TE_FOOD].old_act;
case 0xD1: return GB(this->t->received[TE_FOOD].old_act, 8, 8);
case 0xD2: return this->t->received[TE_WATER].old_act;
case 0xD3: return GB(this->t->received[TE_WATER].old_act, 8, 8);
case 0xD4: return this->t->road_build_months;
case 0xD5: return this->t->fund_buildings_months;
}
DEBUG(grf, 1, "Unhandled town variable 0x%X", variable);
*available = false;
return UINT_MAX;
}
/*
// DotCommand
//
// Dot command processor
//
// This is the function where users add their assembler commands
//
// ps - Pointer to source file record
// TermCnt - Number of terms (including the command)
// pTerms - Pointer to the terms
// Src - Buffer to write any resulting assembly line
// MaxSrc - Size of assembly line buffer
//
// Returns:
// >=0 : Success - Length of assemby line (0 to MaxSrc)
// <0 : Illegal command
*/
int DotCommand( SOURCEFILE *ps, int TermCnt, char **pTerms, char *Src, int MaxSrc )
{
int i;
for(i=0; i<=DOTCMD_MAX; i++)
{
if( !stricmp( pTerms[0], DotCmds[i] ) )
break;
}
if( i>DOTCMD_MAX )
{
Report(ps,REP_ERROR,"Unrecognized dot command");
return(-1);
}
if( i==DOTCMD_MAIN )
{
char c,cs;
int quote=0;
int idx=0,nameidx=0;
/*
// .main command
//
// Just print a warning - its only here for compatibility
*/
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
/* If the string is in quotes, skip the first charater */
if( pTerms[1][0]=='"' )
{
quote++;
idx++;
}
c = pTerms[1][idx++];
cs = ps->SourceName[nameidx++];
while( c && c!='"' )
{
if( toupper(c) != toupper(cs) )
{
NO_MATCH:
Report(ps,REP_WARN1,".main name '%s' doesn't match '%s'",
pTerms[1],ps->SourceName);
return(0);
}
c = pTerms[1][idx++];
cs = ps->SourceName[nameidx++];
}
if( cs && cs!='.' )
goto NO_MATCH;
if( c=='"' )
{
quote--;
c = pTerms[1][idx++];
}
if( c )
{ Report(ps,REP_ERROR,"Trailing characters on name"); return(-1); }
if( quote )
{ Report(ps,REP_ERROR,"Unbalanced quotes on name"); return(-1); }
return(0);
}
else if( i==DOTCMD_END )
{
/*
// .end command
//
// Do nothing - its only here for compatibility
*/
if( TermCnt != 1 )
{ Report(ps,REP_ERROR,"Expected no operands"); return(-1); }
return(0);
}
else if( i==DOTCMD_PROC )
{
/*
// .proc command
//
// Create a label from the proc name, with a leading '.'
// (this is for compatibility)
*/
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
sprintf( Src, ".%s:", pTerms[1] );
return(strlen(Src));
}
else if( i==DOTCMD_RET )
{
/*
// .ret command
//
// Generate the line "jmp r30.w0"
// This makes us compatible with "CALL", although inexplicably,
// the CALL command is not a "dot" command.
//
*/
if( TermCnt != 1 )
{ Report(ps,REP_ERROR,"Expected no operands"); return(-1); }
if( Options & OPTION_RETREGSET )
{ Report(ps,REP_ERROR,".ret incompatible with .setcallreg, use ret"); return(-1); }
if( Core > CORE_V1 )
{ Report(ps,REP_ERROR,".ret illegal with specified core version, use ret"); return(-1); }
strcpy( Src, "jmp r30.w0" );
return(strlen(Src));
}
else if( i==DOTCMD_ORIGIN )
{
int val,tmp;
char tstr[TOKEN_MAX_LEN];
/*
// .origin command
//
// Alter the origin for writing code
*/
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
strcpy( tstr, pTerms[1] );
if( Expression(ps, tstr, (uint *)&val, &tmp)<0 )
{ Report(ps,REP_ERROR,"Error in processing .origin value"); return(-1); }
if( Core == CORE_V0 )
{ Report(ps,REP_ERROR,".origin illegal with specified core version"); return(-1); }
if( val<CodeOffset )
{ Report(ps,REP_ERROR,".origin value is less than current offset"); return(-1); }
if( CodeOffset>=0 )
Report(ps,REP_WARN1,"Resetting .origin value after use");
if( EntryPoint<0 )
EntryPoint = val;
CodeOffset = val;
return(0);
}
else if( i==DOTCMD_ENTRYPOINT )
{
int val,tmp;
char tstr[TOKEN_MAX_LEN];
/*
// .entrypoint command
//
// Alter the origin for writing code
*/
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
strcpy( tstr, pTerms[1] );
if( Expression(ps, tstr, (uint *)&val, &tmp)<0 )
{ Report(ps,REP_ERROR,"Error in processing .entrypoint value"); return(-1); }
if( Core == CORE_V0 )
{ Report(ps,REP_ERROR,".entrypoint illegal with specified core version"); return(-1); }
if( HaveEntry )
{ Report(ps,REP_ERROR,"Multiple .entrypoint declarations"); return(-1); }
EntryPoint = val;
HaveEntry = 1;
return(0);
}
else if( i==DOTCMD_STRUCT )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( StructNew(ps,pTerms[1]) );
}
else if( i==DOTCMD_ENDS )
{
if( TermCnt != 1 )
{ Report(ps,REP_ERROR,"Expected no operands"); return(-1); }
return( StructEnd(ps) );
}
else if( i==DOTCMD_U32 )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( StructAddElement( ps, pTerms[1], 4 ) );
}
else if( i==DOTCMD_U16 )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( StructAddElement( ps, pTerms[1], 2 ) );
}
else if( i==DOTCMD_U8 )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( StructAddElement( ps, pTerms[1], 1 ) );
}
else if( i==DOTCMD_ASSIGN )
{
if( TermCnt != 5 )
{ Report(ps,REP_ERROR,"Expected 4 operands"); return(-1); }
return( StructAssign(ps, pTerms[1], pTerms[2], pTerms[3], pTerms[4]) );
}
else if( i==DOTCMD_SETCALLREG )
{
PRU_ARG r;
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
if( Core == CORE_V0 )
{ Report(ps,REP_ERROR,".setcallreg illegal with specified core version"); return(-1); }
if( Pass==1 && (Options & OPTION_RETREGSET) )
{ Report(ps,REP_ERROR,".setcallreg redefinition"); return(-1); }
if( CodeOffset>=0 )
{ Report(ps,REP_ERROR,"Can not use .setcallreg after code generation"); return(-1); }
if( !GetRegister( ps, 1, pTerms[1], &r, 0, 0 ) )
return -1;
switch( r.Field )
{
case FIELDTYPE_15_0:
case FIELDTYPE_23_8:
case FIELDTYPE_31_16:
if( r.Value<31 )
{
RetRegValue = r.Value;
RetRegField = r.Field;
Options |= OPTION_RETREGSET;
return 0;
}
}
Report(ps,REP_ERROR,"Register field must be r0 to r30 and 16 bits wide");
return(-1);
}
else if( i==DOTCMD_ENTER )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( ScopeEnter(ps, pTerms[1]) );
}
else if( i==DOTCMD_LEAVE )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( ScopeLeave(ps, pTerms[1]) );
}
else if( i==DOTCMD_USING )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( ScopeUsing(ps, pTerms[1]) );
}
else if( i==DOTCMD_MACRO )
{
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
return( MacroEnter(ps, pTerms[1]) );
}
else if( i==DOTCMD_MPARAM || i==DOTCMD_ENDM )
{ Report(ps,REP_ERROR,"%s can not be used outside of macro",pTerms[0]); return(-1); }
else if( i==DOTCMD_CODEWORD )
{
uint opcode;
int tmp;
char tstr[TOKEN_MAX_LEN];
/*
// .codeword command
*/
if( TermCnt != 2 )
{ Report(ps,REP_ERROR,"Expected 1 operand"); return(-1); }
strcpy( tstr, pTerms[1] );
if( Expression(ps, tstr, &opcode, &tmp)<0 )
{ Report(ps,REP_ERROR,"Error in processing .codeword value"); return(-1); }
GenOp( ps, TermCnt, pTerms, opcode );
return(0);
}
Report(ps,REP_ERROR,"Dot command - Internal Error");
return(-1);
}
void arm_cpu_device::HandleMemSingle( UINT32 insn )
{
UINT32 rn, rnv, off, rd;
/* Fetch the offset */
if (insn & INSN_I)
{
off = decodeShift(insn, NULL);
}
else
{
off = insn & INSN_SDT_IMM;
}
/* Calculate Rn, accounting for PC */
rn = (insn & INSN_RN) >> INSN_RN_SHIFT;
// if (rn==0xf) logerror("%08x: Source R15\n",R15);
if (insn & INSN_SDT_P)
{
/* Pre-indexed addressing */
if (insn & INSN_SDT_U)
{
if (rn != eR15)
rnv = (GetRegister(rn) + off);
else
rnv = (R15 & ADDRESS_MASK) + off;
}
else
{
if (rn != eR15)
rnv = (GetRegister(rn) - off);
else
rnv = (R15 & ADDRESS_MASK) - off;
}
if (insn & INSN_SDT_W)
{
SetRegister(rn,rnv);
if (ARM_DEBUG_CORE && rn == eR15)
logerror("writeback R15 %08x\n", R15);
}
else if (rn == eR15)
{
rnv = rnv + 8;
}
}
else
{
/* Post-indexed addressing */
if (rn == eR15)
{
rnv = (R15 & ADDRESS_MASK) + 8;
}
else
{
rnv = GetRegister(rn);
}
}
/* Do the transfer */
rd = (insn & INSN_RD) >> INSN_RD_SHIFT;
if (insn & INSN_SDT_L)
{
/* Load */
m_icount -= S_CYCLE + I_CYCLE + N_CYCLE;
if (insn & INSN_SDT_B)
{
if (ARM_DEBUG_CORE && rd == eR15)
logerror("read byte R15 %08x\n", R15);
SetRegister(rd,(UINT32) cpu_read8(rnv) );
}
else
{
if (rd == eR15)
{
R15 = (cpu_read32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK);
/*
The docs are explicit in that the bottom bits should be masked off
when writing to R15 in this way, however World Cup Volleyball 95 has
an example of an unaligned jump (bottom bits = 2) where execution
should definitely continue from the rounded up address.
In other cases, 4 is subracted from R15 here to account for pipelining.
*/
if ((cpu_read32(rnv)&3)==0)
R15 -= 4;
m_icount -= S_CYCLE + N_CYCLE;
}
else
{
SetRegister(rd, cpu_read32(rnv));
}
}
}
else
{
/* Store */
m_icount -= 2 * N_CYCLE;
if (insn & INSN_SDT_B)
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in byte mode\n");
cpu_write8(rnv, (UINT8) GetRegister(rd) & 0xffu);
}
else
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in 32bit mode\n");
cpu_write32(rnv, rd == eR15 ? R15 + 8 : GetRegister(rd));
}
}
/* Do post-indexing writeback */
if (!(insn & INSN_SDT_P)/* && (insn&INSN_SDT_W)*/)
{
if (insn & INSN_SDT_U)
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn)
{
SetRegister(rn,GetRegister(rd));
}
else
{
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
SetRegister(rn,(rnv + off));
}
}
else
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn)
{
SetRegister(rn,GetRegister(rd));
}
else
{
SetRegister(rn,(rnv - off));
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackDecrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
}
}
}
} /* HandleMemSingle */
void arm7_get_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
/* cpu implementation data */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(ARM7); break;
case CPUINFO_INT_INPUT_LINES: info->i = ARM7_NUM_LINES; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 3; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
/* interrupt lines/exceptions */
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = ARM7.pendingIrq; break;
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = ARM7.pendingFiq; break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = ARM7.pendingAbtD; break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = ARM7.pendingAbtP; break;
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = ARM7.pendingUnd; break;
/* registers shared by all operating modes */
case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break;
case CPUINFO_INT_REGISTER + ARM7_R1: info->i = ARM7REG( 1); break;
case CPUINFO_INT_REGISTER + ARM7_R2: info->i = ARM7REG( 2); break;
case CPUINFO_INT_REGISTER + ARM7_R3: info->i = ARM7REG( 3); break;
case CPUINFO_INT_REGISTER + ARM7_R4: info->i = ARM7REG( 4); break;
case CPUINFO_INT_REGISTER + ARM7_R5: info->i = ARM7REG( 5); break;
case CPUINFO_INT_REGISTER + ARM7_R6: info->i = ARM7REG( 6); break;
case CPUINFO_INT_REGISTER + ARM7_R7: info->i = ARM7REG( 7); break;
case CPUINFO_INT_REGISTER + ARM7_R8: info->i = ARM7REG( 8); break;
case CPUINFO_INT_REGISTER + ARM7_R9: info->i = ARM7REG( 9); break;
case CPUINFO_INT_REGISTER + ARM7_R10: info->i = ARM7REG(10); break;
case CPUINFO_INT_REGISTER + ARM7_R11: info->i = ARM7REG(11); break;
case CPUINFO_INT_REGISTER + ARM7_R12: info->i = ARM7REG(12); break;
case CPUINFO_INT_REGISTER + ARM7_R13: info->i = ARM7REG(13); break;
case CPUINFO_INT_REGISTER + ARM7_R14: info->i = ARM7REG(14); break;
case CPUINFO_INT_REGISTER + ARM7_R15: info->i = ARM7REG(15); break;
case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + ARM7_PC: info->i = R15; break;
case CPUINFO_INT_SP: info->i = GetRegister(13); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR9: info->i = ARM7REG(eR9_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR10: info->i = ARM7REG(eR10_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR11: info->i = ARM7REG(eR11_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR12: info->i = ARM7REG(eR12_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR13: info->i = ARM7REG(eR13_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR14: info->i = ARM7REG(eR14_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FSPSR: info->i = ARM7REG(eSPSR_FIQ); break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_IR13: info->i = ARM7REG(eR13_IRQ); break;
case CPUINFO_INT_REGISTER + ARM7_IR14: info->i = ARM7REG(eR14_IRQ); break;
case CPUINFO_INT_REGISTER + ARM7_ISPSR: info->i = ARM7REG(eSPSR_IRQ); break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_SR13: info->i = ARM7REG(eR13_SVC); break;
case CPUINFO_INT_REGISTER + ARM7_SR14: info->i = ARM7REG(eR14_SVC); break;
case CPUINFO_INT_REGISTER + ARM7_SSPSR: info->i = ARM7REG(eSPSR_SVC); break;
/* Abort Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_AR13: info->i = ARM7REG(eR13_ABT); break;
case CPUINFO_INT_REGISTER + ARM7_AR14: info->i = ARM7REG(eR14_ABT); break;
case CPUINFO_INT_REGISTER + ARM7_ASPSR: info->i = ARM7REG(eSPSR_ABT); break;
/* Undefined Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_UR13: info->i = ARM7REG(eR13_UND); break;
case CPUINFO_INT_REGISTER + ARM7_UR14: info->i = ARM7REG(eR14_UND); break;
case CPUINFO_INT_REGISTER + ARM7_USPSR: info->i = ARM7REG(eSPSR_UND); break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = arm7_set_info; break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = arm7_get_context; break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = arm7_set_context; break;
case CPUINFO_PTR_INIT: info->init = arm7_init; break;
case CPUINFO_PTR_RESET: info->reset = arm7_reset; break;
case CPUINFO_PTR_EXIT: info->exit = arm7_exit; break;
case CPUINFO_PTR_EXECUTE: info->execute = arm7_execute; break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
#ifdef MAME_DEBUG
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = arm7_dasm; break;
#endif /* MAME_DEBUG */
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ARM7_ICOUNT; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "ARM7"); break;
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Acorn Risc Machine"); break;
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.3"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright 2004-2006 Steve Ellenoff, [email protected]"); break;
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c %s",
(ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
(ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
(ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
(ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
(ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
(ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
(ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
GetModeText(ARM7REG(eCPSR)));
break;
/* registers shared by all operating modes */
case CPUINFO_STR_REGISTER + ARM7_PC: sprintf(info->s, "PC :%08x", R15 ); break;
case CPUINFO_STR_REGISTER + ARM7_R0: sprintf(info->s, "R0 :%08x", ARM7REG( 0) ); break;
case CPUINFO_STR_REGISTER + ARM7_R1: sprintf(info->s, "R1 :%08x", ARM7REG( 1) ); break;
case CPUINFO_STR_REGISTER + ARM7_R2: sprintf(info->s, "R2 :%08x", ARM7REG( 2) ); break;
case CPUINFO_STR_REGISTER + ARM7_R3: sprintf(info->s, "R3 :%08x", ARM7REG( 3) ); break;
case CPUINFO_STR_REGISTER + ARM7_R4: sprintf(info->s, "R4 :%08x", ARM7REG( 4) ); break;
case CPUINFO_STR_REGISTER + ARM7_R5: sprintf(info->s, "R5 :%08x", ARM7REG( 5) ); break;
case CPUINFO_STR_REGISTER + ARM7_R6: sprintf(info->s, "R6 :%08x", ARM7REG( 6) ); break;
case CPUINFO_STR_REGISTER + ARM7_R7: sprintf(info->s, "R7 :%08x", ARM7REG( 7) ); break;
case CPUINFO_STR_REGISTER + ARM7_R8: sprintf(info->s, "R8 :%08x", ARM7REG( 8) ); break;
case CPUINFO_STR_REGISTER + ARM7_R9: sprintf(info->s, "R9 :%08x", ARM7REG( 9) ); break;
case CPUINFO_STR_REGISTER + ARM7_R10: sprintf(info->s, "R10 :%08x", ARM7REG(10) ); break;
case CPUINFO_STR_REGISTER + ARM7_R11: sprintf(info->s, "R11 :%08x", ARM7REG(11) ); break;
case CPUINFO_STR_REGISTER + ARM7_R12: sprintf(info->s, "R12 :%08x", ARM7REG(12) ); break;
case CPUINFO_STR_REGISTER + ARM7_R13: sprintf(info->s, "R13 :%08x", ARM7REG(13) ); break;
case CPUINFO_STR_REGISTER + ARM7_R14: sprintf(info->s, "R14 :%08x", ARM7REG(14) ); break;
case CPUINFO_STR_REGISTER + ARM7_R15: sprintf(info->s, "R15 :%08x", ARM7REG(15) ); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_FR8: sprintf(info->s, "FR8 :%08x", ARM7REG(eR8_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR9: sprintf(info->s, "FR9 :%08x", ARM7REG(eR9_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR10: sprintf(info->s, "FR10:%08x", ARM7REG(eR10_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR11: sprintf(info->s, "FR11:%08x", ARM7REG(eR11_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR12: sprintf(info->s, "FR12:%08x", ARM7REG(eR12_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR13: sprintf(info->s, "FR13:%08x", ARM7REG(eR13_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR14: sprintf(info->s, "FR14:%08x", ARM7REG(eR14_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FSPSR: sprintf(info->s, "FR16:%08x", ARM7REG(eSPSR_FIQ)); break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_IR13: sprintf(info->s, "IR13:%08x", ARM7REG(eR13_IRQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_IR14: sprintf(info->s, "IR14:%08x", ARM7REG(eR14_IRQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_ISPSR: sprintf(info->s, "IR16:%08x", ARM7REG(eSPSR_IRQ)); break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_SR13: sprintf(info->s, "SR13:%08x", ARM7REG(eR13_SVC) ); break;
case CPUINFO_STR_REGISTER + ARM7_SR14: sprintf(info->s, "SR14:%08x", ARM7REG(eR14_SVC) ); break;
case CPUINFO_STR_REGISTER + ARM7_SSPSR: sprintf(info->s, "SR16:%08x", ARM7REG(eSPSR_SVC)); break;
/* Abort Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_AR13: sprintf(info->s, "AR13:%08x", ARM7REG(eR13_ABT) ); break;
case CPUINFO_STR_REGISTER + ARM7_AR14: sprintf(info->s, "AR14:%08x", ARM7REG(eR14_ABT) ); break;
case CPUINFO_STR_REGISTER + ARM7_ASPSR: sprintf(info->s, "AR16:%08x", ARM7REG(eSPSR_ABT)); break;
/* Undefined Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_UR13: sprintf(info->s, "UR13:%08x", ARM7REG(eR13_UND) ); break;
case CPUINFO_STR_REGISTER + ARM7_UR14: sprintf(info->s, "UR14:%08x", ARM7REG(eR14_UND) ); break;
case CPUINFO_STR_REGISTER + ARM7_USPSR: sprintf(info->s, "UR16:%08x", ARM7REG(eSPSR_UND)); break;
}
}
