C++ (Cpp) Get_ChannelPS_Cfg0_D Examples

Example #1

void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
			 struct DCTStatStruc *pDCTstat, u32 dct)
{
	print_tx("dct: ", dct);
	print_tx("Speed: ", pDCTstat->Speed);

	Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
				pDCTstat->MAload[dct], pDCTstat->DATAload[dct],
				&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
				&pDCTstat->_2Tmode);

	if (pDCTstat->MAdimms[dct] == 1)
		pDCTstat->CH_ODC_CTL[dct] |= 0x20000000;	/* 75ohms */
	else
		pDCTstat->CH_ODC_CTL[dct] |= 0x10000000;	/* 150ohms */


	/*
	 * Overrides and/or workarounds
	 */
	pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]);

	print_tx("4 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]);
	print_tx("4 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]);
}

Example #2

File: mctardk6.c Project: 0ida/coreboot

void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
			 struct DCTStatStruc *pDCTstat, u32 dct)
{
	Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
				pDCTstat->MAload[dct], pDCTstat->DATAload[dct],
				&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
				&pDCTstat->_2Tmode);

	if (pDCTstat->GangedMode == 1 && dct == 0)
		Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[1], pDCTstat->Speed,
				     pDCTstat->MAload[1], pDCTstat->DATAload[1],
				     &(pDCTstat->CH_ADDR_TMG[1]), &(pDCTstat->CH_ODC_CTL[1]),
				     &pDCTstat->_2Tmode);

	pDCTstat->CH_EccDQSLike[0]  = 0x0302;
	pDCTstat->CH_EccDQSLike[1]  = 0x0302;

}

Example #3

File: mctardk5.c Project: 0ida/coreboot

void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
			 struct DCTStatStruc *pDCTstat, u32 dct)
{
	Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
				pDCTstat->MAload[dct],
				&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
				&pDCTstat->_2Tmode);

	pDCTstat->CH_EccDQSLike[0]  = 0x0403;
	pDCTstat->CH_EccDQSScale[0] = 0x70;
	pDCTstat->CH_EccDQSLike[1]  = 0x0403;
	pDCTstat->CH_EccDQSScale[1] = 0x70;

	pDCTstat->CH_ODC_CTL[dct] |= 0x20000000;	/* 60ohms */
}

Example #4

File: mctardk3.c Project: canistation/coreboot

void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
			 struct DCTStatStruc *pDCTstat, u32 dct)
{
	u16 val, valx;

	print_tx("dct: ", dct);
	print_tx("Speed: ", pDCTstat->Speed);

	Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
				pDCTstat->MAload[dct], pDCTstat->DATAload[dct],
				&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]));


	if (pDCTstat->MAdimms[dct] == 1)
		pDCTstat->CH_ODC_CTL[dct] |= 0x20000000;	/* 75ohms */
	else
		pDCTstat->CH_ODC_CTL[dct] |= 0x10000000;	/* 150ohms */

	pDCTstat->_2Tmode = 1;

	/* use byte lane 4 delay for ECC lane */
	pDCTstat->CH_EccDQSLike[0] = 0x0504;
	pDCTstat->CH_EccDQSScale[0] = 0;	/* 100% byte lane 4 */
	pDCTstat->CH_EccDQSLike[1] = 0x0504;
	pDCTstat->CH_EccDQSScale[1] = 0;	/* 100% byte lane 4 */


	/*
	 Overrides and/or exceptions
	*/

	/* 1) QRx4 needs to adjust CS/ODT setup time */
	// FIXME: Add Ax support?
	if (mctGet_NVbits(NV_MAX_DIMMS) == 4) {
		if (pDCTstat->DimmQRPresent != 0) {
			pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF;
			pDCTstat->CH_ADDR_TMG[dct] |= 0x00000000;
			if (pDCTstat->MAdimms[dct] == 4) {
				pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF;
				pDCTstat->CH_ADDR_TMG[dct] |= 0x002F0000;
				if (pDCTstat->Speed == 3 || pDCTstat->Speed == 4) {
					pDCTstat->CH_ADDR_TMG[dct] &= 0xFF00FFFF;
					pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00;
					if (pDCTstat->MAdimms[dct] == 4)
						pDCTstat->CH_ODC_CTL[dct] = 0x00331222;
				}
			}
		}
	}


	/* 2) DRx4 (R/C-J) @ DDR667 needs to adjust CS/ODT setup time */
	if (pDCTstat->Speed == 3 || pDCTstat->Speed == 4) {
		val = pDCTstat->Dimmx4Present;
		if (dct == 0) {
			val &= 0x55;
		} else {
			val &= 0xAA;
			val >>= 1;
		}
		val &= pDCTstat->DIMMValid;
		if (val) {
			//FIXME: skip for Ax
			valx = pDCTstat->DimmDRPresent;
			if (dct == 0) {
				valx &= 0x55;
			} else {
				valx &= 0xAA;
				valx >>= 1;
			}
			if (mctGet_NVbits(NV_MAX_DIMMS) == 8) {
				val &= valx;
				if (val != 0) {
					pDCTstat->CH_ADDR_TMG[dct] &= 0xFFFF00FF;
					pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00;
				}
			} else {
				val &= valx;
				if (val != 0) {
					if (pDCTstat->Speed == 3 || pDCTstat->Speed == 3) {
						pDCTstat->CH_ADDR_TMG[dct] &= 0xFFFF00FF;
						pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00;
					}
				}

			}
		}
	}