/**Function*************************************************************
Synopsis [Determines the failed PO when its exact frame is not known.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManSetFailedPoCex( Gia_Man_t * pAig, Abc_Cex_t * p )
{
Gia_Obj_t * pObj, * pObjRi, * pObjRo;
int i, k, iBit = 0;
assert( Gia_ManPiNum(pAig) == p->nPis );
Gia_ManCleanMark0(pAig);
p->iPo = -1;
// Gia_ManForEachRo( pAig, pObj, i )
// pObj->fMark0 = Abc_InfoHasBit(p->pData, iBit++);
iBit = p->nRegs;
for ( i = 0; i <= p->iFrame; i++ )
{
Gia_ManForEachPi( pAig, pObj, k )
pObj->fMark0 = Abc_InfoHasBit(p->pData, iBit++);
Gia_ManForEachAnd( pAig, pObj, k )
pObj->fMark0 = (Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj)) &
(Gia_ObjFanin1(pObj)->fMark0 ^ Gia_ObjFaninC1(pObj));
Gia_ManForEachCo( pAig, pObj, k )
pObj->fMark0 = Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj);
Gia_ManForEachRiRo( pAig, pObjRi, pObjRo, k )
pObjRo->fMark0 = pObjRi->fMark0;
// check the POs
Gia_ManForEachPo( pAig, pObj, k )
{
if ( !pObj->fMark0 )
continue;
p->iPo = k;
p->iFrame = i;
p->nBits = iBit;
break;
}
}
Gia_ManCleanMark0(pAig);
return p->iPo;
}
/**Function*************************************************************
Synopsis [Count the number of internal nodes in the leaf-DAG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManSatPartPrint( Gia_Man_t * p, Gia_Obj_t * pObj, int Step )
{
Gia_Obj_t * pFanin;
assert( Gia_ObjIsAnd(pObj) );
assert( pObj->fMark0 == 0 );
pFanin = Gia_ObjFanin0(pObj);
if ( pFanin->fMark0 )
printf( "%s%d", Gia_ObjFaninC0(pObj)?"!":"", Gia_ObjId(p,pFanin) );
else
{
if ( Gia_ObjFaninC0(pObj) )
printf( "(" );
Gia_ManSatPartPrint(p, pFanin, Step + Gia_ObjFaninC0(pObj));
if ( Gia_ObjFaninC0(pObj) )
printf( ")" );
}
printf( "%s", (Step & 1)? " + " : "*" );
pFanin = Gia_ObjFanin1(pObj);
if ( pFanin->fMark0 )
printf( "%s%d", Gia_ObjFaninC1(pObj)?"!":"", Gia_ObjId(p,pFanin) );
else
{
if ( Gia_ObjFaninC1(pObj) )
printf( "(" );
Gia_ManSatPartPrint(p, pFanin, Step + Gia_ObjFaninC1(pObj));
if ( Gia_ObjFaninC1(pObj) )
printf( ")" );
}
}
/**Function*************************************************************
Synopsis [Starts the process of returning values for internal nodes.]
Description [Should be called when pCex is available, before probing
any object for its value using Gia_ManCounterExampleValueLookup().]
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManCounterExampleValueStart( Gia_Man_t * pGia, Abc_Cex_t * pCex )
{
Gia_Obj_t * pObj, * pObjRi, * pObjRo;
int Val0, Val1, nObjs, i, k, iBit = 0;
assert( Gia_ManRegNum(pGia) > 0 ); // makes sense only for sequential AIGs
assert( pGia->pData2 == NULL ); // if this fail, there may be a memory leak
// allocate memory to store simulation bits for internal nodes
pGia->pData2 = ABC_CALLOC( unsigned, Abc_BitWordNum( (pCex->iFrame + 1) * Gia_ManObjNum(pGia) ) );
// the register values in the counter-example should be zero
Gia_ManForEachRo( pGia, pObj, k )
assert( Abc_InfoHasBit(pCex->pData, iBit++) == 0 );
// iterate through the timeframes
nObjs = Gia_ManObjNum(pGia);
for ( i = 0; i <= pCex->iFrame; i++ )
{
// no need to set constant-0 node
// set primary inputs according to the counter-example
Gia_ManForEachPi( pGia, pObj, k )
if ( Abc_InfoHasBit(pCex->pData, iBit++) )
Abc_InfoSetBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjId(pGia, pObj) );
// compute values for each node
Gia_ManForEachAnd( pGia, pObj, k )
{
Val0 = Abc_InfoHasBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjFaninId0p(pGia, pObj) );
Val1 = Abc_InfoHasBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjFaninId1p(pGia, pObj) );
if ( (Val0 ^ Gia_ObjFaninC0(pObj)) & (Val1 ^ Gia_ObjFaninC1(pObj)) )
Abc_InfoSetBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjId(pGia, pObj) );
}
// derive values for combinational outputs
Gia_ManForEachCo( pGia, pObj, k )
{
Val0 = Abc_InfoHasBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjFaninId0p(pGia, pObj) );
if ( Val0 ^ Gia_ObjFaninC0(pObj) )
Abc_InfoSetBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjId(pGia, pObj) );
}
/**Function*************************************************************
Synopsis [Creates logic network isomorphic to the given AIG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Cof_Man_t * Cof_ManCreateLogicSimple( Gia_Man_t * pGia )
{
Cof_Man_t * p;
Cof_Obj_t * pObjLog, * pFanLog;
Gia_Obj_t * pObj;
int * pMuxRefs;
int i, iHandle = 0;
p = ABC_CALLOC( Cof_Man_t, 1 );
p->pGia = pGia;
p->vCis = Vec_IntAlloc( Gia_ManCiNum(pGia) );
p->vCos = Vec_IntAlloc( Gia_ManCoNum(pGia) );
p->nObjData = (sizeof(Cof_Obj_t) / 4) * Gia_ManObjNum(pGia) + 4 * Gia_ManAndNum(pGia) + 2 * Gia_ManCoNum(pGia);
p->pObjData = ABC_CALLOC( int, p->nObjData );
ABC_FREE( pGia->pRefs );
Gia_ManCreateRefs( pGia );
Gia_ManForEachObj( pGia, pObj, i )
{
pObj->Value = iHandle;
pObjLog = Cof_ManObj( p, iHandle );
pObjLog->nFanins = 0;
pObjLog->nFanouts = Gia_ObjRefNum( pGia, pObj );
pObjLog->Id = i;
pObjLog->Value = 0;
if ( Gia_ObjIsAnd(pObj) )
{
pFanLog = Cof_ManObj( p, Gia_ObjHandle(Gia_ObjFanin0(pObj)) );
pFanLog->Fanios[pFanLog->nFanins + pFanLog->Value++].iFan =
pObjLog->Fanios[pObjLog->nFanins].iFan = Cof_ObjHandleDiff( pObjLog, pFanLog );
pObjLog->Fanios[pObjLog->nFanins++].fCompl = Gia_ObjFaninC0(pObj);
pFanLog = Cof_ManObj( p, Gia_ObjHandle(Gia_ObjFanin1(pObj)) );
pFanLog->Fanios[pFanLog->nFanins + pFanLog->Value++].iFan =
pObjLog->Fanios[pObjLog->nFanins].iFan = Cof_ObjHandleDiff( pObjLog, pFanLog );
pObjLog->Fanios[pObjLog->nFanins++].fCompl = Gia_ObjFaninC1(pObj);
p->nNodes++;
}
else if ( Gia_ObjIsCo(pObj) )
{
pFanLog = Cof_ManObj( p, Gia_ObjHandle(Gia_ObjFanin0(pObj)) );
pFanLog->Fanios[pFanLog->nFanins + pFanLog->Value++].iFan =
pObjLog->Fanios[pObjLog->nFanins].iFan = Cof_ObjHandleDiff( pObjLog, pFanLog );
pObjLog->Fanios[pObjLog->nFanins++].fCompl = Gia_ObjFaninC0(pObj);
pObjLog->fTerm = 1;
Vec_IntPush( p->vCos, iHandle );
}
else if ( Gia_ObjIsCi(pObj) )
{
pObjLog->fTerm = 1;
Vec_IntPush( p->vCis, iHandle );
}
iHandle += Cof_ObjSize( pObjLog );
p->nObjs++;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Resimulates the counter-example.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManVerifyCex( Gia_Man_t * pAig, Abc_Cex_t * p, int fDualOut )
{
Gia_Obj_t * pObj, * pObjRi, * pObjRo;
int RetValue, i, k, iBit = 0;
Gia_ManCleanMark0(pAig);
Gia_ManForEachRo( pAig, pObj, i )
pObj->fMark0 = Abc_InfoHasBit(p->pData, iBit++);
for ( i = 0; i <= p->iFrame; i++ )
{
Gia_ManForEachPi( pAig, pObj, k )
pObj->fMark0 = Abc_InfoHasBit(p->pData, iBit++);
Gia_ManForEachAnd( pAig, pObj, k )
pObj->fMark0 = (Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj)) &
(Gia_ObjFanin1(pObj)->fMark0 ^ Gia_ObjFaninC1(pObj));
Gia_ManForEachCo( pAig, pObj, k )
pObj->fMark0 = Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj);
if ( i == p->iFrame )
break;
Gia_ManForEachRiRo( pAig, pObjRi, pObjRo, k )
{
pObjRo->fMark0 = pObjRi->fMark0;
}
}
assert( iBit == p->nBits );
if ( fDualOut )
RetValue = Gia_ManPo(pAig, 2*p->iPo)->fMark0 ^ Gia_ManPo(pAig, 2*p->iPo+1)->fMark0;
else
RetValue = Gia_ManPo(pAig, p->iPo)->fMark0;
Gia_ManCleanMark0(pAig);
return RetValue;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_ManHandleSpecialCases( Gia_Man_t * p, Cec_ParCec_t * pPars )
{
Gia_Obj_t * pObj1, * pObj2;
Gia_Obj_t * pDri1, * pDri2;
int i;
abctime clk = Abc_Clock();
Gia_ManSetPhase( p );
Gia_ManForEachPo( p, pObj1, i )
{
pObj2 = Gia_ManPo( p, ++i );
// check if they different on all-0 pattern
// (for example, when they have the same driver but complemented)
if ( Gia_ObjPhase(pObj1) != Gia_ObjPhase(pObj2) )
{
Abc_Print( 1, "Networks are NOT EQUIVALENT. Output %d trivially differs (different phase). ", i/2 );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
pPars->iOutFail = i/2;
Cec_ManTransformPattern( p, i/2, NULL );
return 0;
}
// get the drivers
pDri1 = Gia_ObjFanin0(pObj1);
pDri2 = Gia_ObjFanin0(pObj2);
// drivers are different PIs
if ( Gia_ObjIsPi(p, pDri1) && Gia_ObjIsPi(p, pDri2) && pDri1 != pDri2 )
{
Abc_Print( 1, "Networks are NOT EQUIVALENT. Output %d trivially differs (different PIs). ", i/2 );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
pPars->iOutFail = i/2;
Cec_ManTransformPattern( p, i/2, NULL );
// if their compl attributes are the same - one should be complemented
assert( Gia_ObjFaninC0(pObj1) == Gia_ObjFaninC0(pObj2) );
Abc_InfoSetBit( p->pCexComb->pData, Gia_ObjCioId(pDri1) );
return 0;
}
// one of the drivers is a PI; another is a constant 0
if ( (Gia_ObjIsPi(p, pDri1) && Gia_ObjIsConst0(pDri2)) ||
(Gia_ObjIsPi(p, pDri2) && Gia_ObjIsConst0(pDri1)) )
{
Abc_Print( 1, "Networks are NOT EQUIVALENT. Output %d trivially differs (PI vs. constant). ", i/2 );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
pPars->iOutFail = i/2;
Cec_ManTransformPattern( p, i/2, NULL );
// the compl attributes are the same - the PI should be complemented
assert( Gia_ObjFaninC0(pObj1) == Gia_ObjFaninC0(pObj2) );
if ( Gia_ObjIsPi(p, pDri1) )
Abc_InfoSetBit( p->pCexComb->pData, Gia_ObjCioId(pDri1) );
else
Abc_InfoSetBit( p->pCexComb->pData, Gia_ObjCioId(pDri2) );
return 0;
}
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManDetectSeqSignals( Gia_Man_t * p, int fSetReset, int fVerbose )
{
Vec_Int_t * vSuper;
Gia_Obj_t * pFlop, * pObjC, * pObj0, * pObj1, * pNode, * pTemp;
int i, k, Ent, * pSets, * pResets, * pEnables;
int nHaveSetReset = 0, nHaveEnable = 0;
assert( Gia_ManRegNum(p) > 0 );
pSets = ABC_CALLOC( int, Gia_ManObjNum(p) );
pResets = ABC_CALLOC( int, Gia_ManObjNum(p) );
pEnables = ABC_CALLOC( int, Gia_ManObjNum(p) );
vSuper = Vec_IntAlloc( 100 );
Gia_ManForEachRi( p, pFlop, i )
{
pNode = Gia_ObjFanin0(pFlop);
if ( !Gia_ObjIsAnd(pNode) )
continue;
// detect sets/resets
Gia_CollectSuper( p, pNode, vSuper );
if ( Gia_ObjFaninC0(pFlop) )
Vec_IntForEachEntry( vSuper, Ent, k )
pSets[Ent]++;
else
Vec_IntForEachEntry( vSuper, Ent, k )
pResets[Ent]++;
// detect enables
if ( !Gia_ObjIsMuxType(pNode) )
continue;
pObjC = Gia_ObjRecognizeMux( pNode, &pObj0, &pObj1 );
pTemp = Gia_ObjRiToRo( p, pFlop );
if ( Gia_Regular(pObj0) != pTemp && Gia_Regular(pObj1) != pTemp )
continue;
if ( !Gia_ObjFaninC0(pFlop) )
{
pObj0 = Gia_Not(pObj0);
pObj1 = Gia_Not(pObj1);
}
if ( Gia_IsComplement(pObjC) )
{
pObjC = Gia_Not(pObjC);
pTemp = pObj0;
pObj0 = pObj1;
pObj1 = pTemp;
}
// detect controls
// Gia_CollectSuper( p, pObjC, vSuper );
// Vec_IntForEachEntry( vSuper, Ent, k )
// pEnables[Ent]++;
pEnables[Gia_ObjId(p, pObjC)]++;
nHaveEnable++;
}
/**Function*************************************************************
Synopsis [Collects the supergate rooted at this ]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManSatPartCollectSuper( Gia_Man_t * p, Gia_Obj_t * pObj, int * pLits, int * pnLits )
{
Gia_Obj_t * pFanin;
assert( Gia_ObjIsAnd(pObj) );
assert( pObj->fMark0 == 0 );
pFanin = Gia_ObjFanin0(pObj);
if ( pFanin->fMark0 || Gia_ObjFaninC0(pObj) )
pLits[(*pnLits)++] = Gia_Var2Lit(Gia_ObjId(p, pFanin), Gia_ObjFaninC0(pObj));
else
Gia_ManSatPartCollectSuper(p, pFanin, pLits, pnLits);
pFanin = Gia_ObjFanin1(pObj);
if ( pFanin->fMark0 || Gia_ObjFaninC1(pObj) )
pLits[(*pnLits)++] = Gia_Var2Lit(Gia_ObjId(p, pFanin), Gia_ObjFaninC1(pObj));
else
Gia_ManSatPartCollectSuper(p, pFanin, pLits, pnLits);
}
/**Function*************************************************************
Synopsis [Count the number of internal nodes in the leaf-DAG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManSatPartCountClauses( Gia_Man_t * p, Gia_Obj_t * pObj, int * pnOnset, int * pnOffset )
{
Gia_Obj_t * pFanin;
int nOnset0, nOnset1, nOffset0, nOffset1;
assert( Gia_ObjIsAnd(pObj) );
pFanin = Gia_ObjFanin0(pObj);
if ( pFanin->fMark0 )
nOnset0 = 1, nOffset0 = 1;
else
{
Gia_ManSatPartCountClauses(p, pFanin, &nOnset0, &nOffset0);
if ( Gia_ObjFaninC0(pObj) )
{
int Temp = nOnset0;
nOnset0 = nOffset0;
nOffset0 = Temp;
}
}
pFanin = Gia_ObjFanin1(pObj);
if ( pFanin->fMark0 )
nOnset1 = 1, nOffset1 = 1;
else
{
Gia_ManSatPartCountClauses(p, pFanin, &nOnset1, &nOffset1);
if ( Gia_ObjFaninC1(pObj) )
{
int Temp = nOnset1;
nOnset1 = nOffset1;
nOffset1 = Temp;
}
}
*pnOnset = nOnset0 * nOnset1;
*pnOffset = nOffset0 + nOffset1;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Bmc_LoadTest( Gia_Man_t * pGia, int fLoadCnf, int fVerbose )
{
int nConfLimit = 0;
Bmc_Load_t * p;
Gia_Obj_t * pObj;
int i, status, Lit;
abctime clk = Abc_Clock();
// create the loading manager
p = Bmc_LoadStart( pGia );
// add callback for CNF loading
if ( fLoadCnf )
{
p->pSat->pCnfMan = p;
p->pSat->pCnfFunc = Bmc_LoadAddCnf;
}
// solve SAT problem for each PO
Gia_ManForEachPo( pGia, pObj, i )
{
if ( fLoadCnf )
Lit = Abc_Var2Lit( Bmc_LoadGetSatVar(p, Gia_ObjFaninId0p(pGia, pObj)), Gia_ObjFaninC0(pObj) );
else
Lit = Abc_Var2Lit( Bmc_LoadAddCnf_rec(p, Gia_ObjFaninId0p(pGia, pObj)), Gia_ObjFaninC0(pObj) );
if ( fVerbose )
{
printf( "Frame%4d : ", i );
printf( "Vars = %6d ", Vec_IntSize(p->vSat2Id) );
printf( "Clas = %6d ", sat_solver_nclauses(p->pSat) );
}
status = sat_solver_solve( p->pSat, &Lit, &Lit + 1, (ABC_INT64_T)nConfLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
if ( fVerbose )
{
printf( "Conf = %6d ", sat_solver_nconflicts(p->pSat) );
if ( status == l_False )
printf( "UNSAT " );
else if ( status == l_True )
printf( "SAT " );
else // if ( status == l_Undec )
printf( "UNDEC " );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
}
}
printf( "Callbacks = %d. Loadings = %d.\n", p->nCallBacks1, p->nCallBacks2 );
Bmc_LoadStop( p );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static inline unsigned Gia_Iso3Node( Gia_Obj_t * pObj )
{
if ( Gia_ObjIsAnd(pObj) )
return Iso_Nodes[Gia_ObjFaninC0(pObj) + Gia_ObjFaninC1(pObj)];
if ( Gia_ObjIsCi(pObj) )
return Iso_Nodes[3];
if ( Gia_ObjIsCo(pObj) )
return Iso_Nodes[4];
return Iso_Nodes[5];
}
static inline void Wlc_ObjSimAnd( Gia_Man_t * p, int iObj )
{
int w;
Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
word * pSim = Wlc_ObjSim( p, iObj );
word * pSim0 = Wlc_ObjSim( p, Gia_ObjFaninId0(pObj, iObj) );
word * pSim1 = Wlc_ObjSim( p, Gia_ObjFaninId1(pObj, iObj) );
if ( Gia_ObjFaninC0(pObj) && Gia_ObjFaninC1(pObj) )
for ( w = 0; w < p->iPatsPi; w++ )
pSim[w] = ~pSim0[w] & ~pSim1[w];
else if ( Gia_ObjFaninC0(pObj) && !Gia_ObjFaninC1(pObj) )
for ( w = 0; w < p->iPatsPi; w++ )
pSim[w] = ~pSim0[w] & pSim1[w];
else if ( !Gia_ObjFaninC0(pObj) && Gia_ObjFaninC1(pObj) )
for ( w = 0; w < p->iPatsPi; w++ )
pSim[w] = pSim0[w] & ~pSim1[w];
else
for ( w = 0; w < p->iPatsPi; w++ )
pSim[w] = pSim0[w] & pSim1[w];
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Backward propagation.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Bmc_CexCarePropagateFwdOne( Gia_Man_t * p, Abc_Cex_t * pCex, int f, int fGrow )
{
Gia_Obj_t * pObj;
int Prio, Prio0, Prio1;
int i, Phase0, Phase1;
if ( (fGrow & 2) )
{
Gia_ManForEachPi( p, pObj, i )
pObj->Value = Abc_Var2Lit( f * pCex->nPis + (pCex->nPis-1-i) + 1, Abc_InfoHasBit(pCex->pData, pCex->nRegs + pCex->nPis * f + i) );
}
else
{
Gia_ManForEachPi( p, pObj, i )
pObj->Value = Abc_Var2Lit( f * pCex->nPis + i + 1, Abc_InfoHasBit(pCex->pData, pCex->nRegs + pCex->nPis * f + i) );
}
Gia_ManForEachAnd( p, pObj, i )
{
Prio0 = Abc_Lit2Var(Gia_ObjFanin0(pObj)->Value);
Prio1 = Abc_Lit2Var(Gia_ObjFanin1(pObj)->Value);
Phase0 = Abc_LitIsCompl(Gia_ObjFanin0(pObj)->Value) ^ Gia_ObjFaninC0(pObj);
Phase1 = Abc_LitIsCompl(Gia_ObjFanin1(pObj)->Value) ^ Gia_ObjFaninC1(pObj);
if ( Phase0 && Phase1 )
Prio = (fGrow & 1) ? Abc_MinInt(Prio0, Prio1) : Abc_MaxInt(Prio0, Prio1);
else if ( Phase0 && !Phase1 )
Prio = Prio1;
else if ( !Phase0 && Phase1 )
Prio = Prio0;
else // if ( !Phase0 && !Phase1 )
Prio = (fGrow & 1) ? Abc_MaxInt(Prio0, Prio1) : Abc_MinInt(Prio0, Prio1);
pObj->Value = Abc_Var2Lit( Prio, Phase0 & Phase1 );
}
void Gia_Iso3Compute( Gia_Man_t * p, Vec_Int_t * vSign )
{
Gia_Obj_t * pObj;
int i;
Gia_ManForEachObj( p, pObj, i )
{
if ( Gia_ObjIsAnd(pObj) || Gia_ObjIsCo(pObj) )
Gia_Iso3ComputeEdge( p, pObj, Gia_ObjFanin0(pObj), Gia_ObjFaninC0(pObj), vSign );
if ( Gia_ObjIsAnd(pObj) )
Gia_Iso3ComputeEdge( p, pObj, Gia_ObjFanin1(pObj), Gia_ObjFaninC1(pObj), vSign );
}
}
/**Function*************************************************************
Synopsis [Refine one class by resimulating one pattern.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Ssc_GiaSimulatePatternFraig_rec( Ssc_Man_t * p, int iFraigObj )
{
Gia_Obj_t * pObj;
int Res0, Res1;
if ( Ssc_ObjSatVar(p, iFraigObj) )
return sat_solver_var_value( p->pSat, Ssc_ObjSatVar(p, iFraigObj) );
pObj = Gia_ManObj( p->pFraig, iFraigObj );
assert( Gia_ObjIsAnd(pObj) );
Res0 = Ssc_GiaSimulatePatternFraig_rec( p, Gia_ObjFaninId0(pObj, iFraigObj) );
Res1 = Ssc_GiaSimulatePatternFraig_rec( p, Gia_ObjFaninId1(pObj, iFraigObj) );
pObj->fMark0 = (Res0 ^ Gia_ObjFaninC0(pObj)) & (Res1 ^ Gia_ObjFaninC1(pObj));
return pObj->fMark0;
}
static inline void Wlc_ObjSimCo( Gia_Man_t * p, int iObj )
{
int w;
Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
word * pSimCo = Wlc_ObjSim( p, iObj );
word * pSimDri = Wlc_ObjSim( p, Gia_ObjFaninId0(pObj, iObj) );
if ( Gia_ObjFaninC0(pObj) )
for ( w = 0; w < p->iPatsPi; w++ )
pSimCo[w] = ~pSimDri[w];
else
for ( w = 0; w < p->iPatsPi; w++ )
pSimCo[w] = pSimDri[w];
}
/**Function*************************************************************
Synopsis [Computes truth table of a 6-LUT.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ObjComputeTruthTable6Lut_rec( Gia_Man_t * p, int iObj, Vec_Wrd_t * vTemp )
{
word uTruth0, uTruth1;
Gia_Obj_t * pObj = Gia_ManObj( p, iObj );
if ( !Gia_ObjIsAnd(pObj) )
return;
Gia_ObjComputeTruthTable6Lut_rec( p, Gia_ObjFaninId0p(p, pObj), vTemp );
Gia_ObjComputeTruthTable6Lut_rec( p, Gia_ObjFaninId1p(p, pObj), vTemp );
uTruth0 = Vec_WrdEntry( vTemp, Gia_ObjFanin0(pObj)->Value );
uTruth0 = Gia_ObjFaninC0(pObj) ? ~uTruth0 : uTruth0;
uTruth1 = Vec_WrdEntry( vTemp, Gia_ObjFanin1(pObj)->Value );
uTruth1 = Gia_ObjFaninC1(pObj) ? ~uTruth1 : uTruth1;
Vec_WrdWriteEntry( vTemp, iObj, uTruth0 & uTruth1 );
}
/**Function*************************************************************
Synopsis [Resimulates the counter-example.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManFindFailedPoCex( Gia_Man_t * pAig, Abc_Cex_t * p, int nOutputs )
{
Gia_Obj_t * pObj, * pObjRi, * pObjRo;
int RetValue, i, k, iBit = 0;
assert( Gia_ManPiNum(pAig) == p->nPis );
Gia_ManCleanMark0(pAig);
// Gia_ManForEachRo( pAig, pObj, i )
// pObj->fMark0 = Abc_InfoHasBit(p->pData, iBit++);
iBit = p->nRegs;
for ( i = 0; i <= p->iFrame; i++ )
{
Gia_ManForEachPi( pAig, pObj, k )
pObj->fMark0 = Abc_InfoHasBit(p->pData, iBit++);
Gia_ManForEachAnd( pAig, pObj, k )
pObj->fMark0 = (Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj)) &
(Gia_ObjFanin1(pObj)->fMark0 ^ Gia_ObjFaninC1(pObj));
Gia_ManForEachCo( pAig, pObj, k )
pObj->fMark0 = Gia_ObjFanin0(pObj)->fMark0 ^ Gia_ObjFaninC0(pObj);
Gia_ManForEachRiRo( pAig, pObjRi, pObjRo, k )
pObjRo->fMark0 = pObjRi->fMark0;
}
assert( iBit == p->nBits );
// figure out the number of failed output
RetValue = -1;
// for ( i = Gia_ManPoNum(pAig) - 1; i >= nOutputs; i-- )
for ( i = nOutputs; i < Gia_ManPoNum(pAig); i++ )
{
if ( Gia_ManPo(pAig, i)->fMark0 )
{
RetValue = i;
break;
}
}
Gia_ManCleanMark0(pAig);
return RetValue;
}
/**Function*************************************************************
Synopsis [Computes truth table up to 6 inputs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ObjComputeTruthTable6_rec( Gia_Man_t * p, Gia_Obj_t * pObj, Vec_Wrd_t * vTruths )
{
word uTruth0, uTruth1;
if ( Gia_ObjIsTravIdCurrent(p, pObj) )
return;
Gia_ObjSetTravIdCurrent(p, pObj);
assert( !pObj->fMark0 );
assert( Gia_ObjIsAnd(pObj) );
Gia_ObjComputeTruthTable6_rec( p, Gia_ObjFanin0(pObj), vTruths );
Gia_ObjComputeTruthTable6_rec( p, Gia_ObjFanin1(pObj), vTruths );
uTruth0 = Vec_WrdEntry( vTruths, Gia_ObjFanin0(pObj)->Value );
uTruth0 = Gia_ObjFaninC0(pObj) ? ~uTruth0 : uTruth0;
uTruth1 = Vec_WrdEntry( vTruths, Gia_ObjFanin1(pObj)->Value );
uTruth1 = Gia_ObjFaninC1(pObj) ? ~uTruth1 : uTruth1;
pObj->Value = Vec_WrdSize(vTruths);
Vec_WrdPush( vTruths, uTruth0 & uTruth1 );
}
int Ssc_GiaSimulatePattern_rec( Ssc_Man_t * p, Gia_Obj_t * pObj )
{
int Res0, Res1;
if ( Gia_ObjIsTravIdCurrent(p->pAig, pObj) )
return pObj->fMark0;
Gia_ObjSetTravIdCurrent(p->pAig, pObj);
if ( ~pObj->Value ) // mapping into FRAIG exists - simulate FRAIG
{
Res0 = Ssc_GiaSimulatePatternFraig_rec( p, Abc_Lit2Var(pObj->Value) );
pObj->fMark0 = Res0 ^ Abc_LitIsCompl(pObj->Value);
}
else // mapping into FRAIG does not exist - simulate AIG
{
Res0 = Ssc_GiaSimulatePattern_rec( p, Gia_ObjFanin0(pObj) );
Res1 = Ssc_GiaSimulatePattern_rec( p, Gia_ObjFanin1(pObj) );
pObj->fMark0 = (Res0 ^ Gia_ObjFaninC0(pObj)) & (Res1 ^ Gia_ObjFaninC1(pObj));
}
return pObj->fMark0;
}
/**Function*************************************************************
Synopsis [Count the number of internal nodes in the leaf-DAG.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_ManSatPartCount( Gia_Man_t * p, Gia_Obj_t * pObj, int * pnLeaves, int * pnNodes )
{
Gia_Obj_t * pFanin;
int Level0 = 0, Level1 = 0;
assert( Gia_ObjIsAnd(pObj) );
assert( pObj->fMark0 == 0 );
(*pnNodes)++;
pFanin = Gia_ObjFanin0(pObj);
if ( pFanin->fMark0 )
(*pnLeaves)++;
else
Level0 = Gia_ManSatPartCount(p, pFanin, pnLeaves, pnNodes) + Gia_ObjFaninC0(pObj);
pFanin = Gia_ObjFanin1(pObj);
if ( pFanin->fMark0 )
(*pnLeaves)++;
else
Level1 = Gia_ManSatPartCount(p, pFanin, pnLeaves, pnNodes) + Gia_ObjFaninC1(pObj);
return Abc_MaxInt( Level0, Level1 );
}
/**Function*************************************************************
Synopsis [Returns 1 if AIG has transition into init state.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Int2_ManCheckInit( Gia_Man_t * p )
{
sat_solver * pSat;
Cnf_Dat_t * pCnf;
Gia_Man_t * pNew;
Gia_Obj_t * pObj;
Vec_Int_t * vLits;
int i, Lit, RetValue = 0;
assert( Gia_ManRegNum(p) > 0 );
pNew = Jf_ManDeriveCnf( p, 0 );
pCnf = (Cnf_Dat_t *)pNew->pData; pNew->pData = NULL;
pSat = (sat_solver *)Cnf_DataWriteIntoSolver( pCnf, 1, 0 );
if ( pSat != NULL )
{
vLits = Vec_IntAlloc( Gia_ManRegNum(p) );
Gia_ManForEachRi( pNew, pObj, i )
{
Lit = pCnf->pVarNums[ Gia_ObjId(pNew, Gia_ObjFanin0(pObj)) ];
Lit = Abc_Var2Lit( Lit, Gia_ObjFaninC0(pObj) );
Vec_IntPush( vLits, Abc_LitNot(Lit) );
}
int Bmc_LoadAddCnf( void * pMan, int iLit )
{
Bmc_Load_t * p = (Bmc_Load_t *)pMan;
int Lits[3], iVar = Abc_Lit2Var(iLit);
Gia_Obj_t * pObj = Gia_ManObj( p->pGia, Vec_IntEntry(p->vSat2Id, iVar) );
p->nCallBacks1++;
if ( Gia_ObjIsCi(pObj) || Gia_ObjIsConst0(pObj) )
return 0;
assert( Gia_ObjIsAnd(pObj) );
if ( (Abc_LitIsCompl(iLit) ? pObj->fMark1 : pObj->fMark0) )
return 0;
Lits[0] = Abc_LitNot(iLit);
if ( Abc_LitIsCompl(iLit) )
{
Lits[1] = Abc_Var2Lit( Bmc_LoadGetSatVar(p, Gia_ObjFaninId0p(p->pGia, pObj)), !Gia_ObjFaninC0(pObj) );
Lits[2] = Abc_Var2Lit( Bmc_LoadGetSatVar(p, Gia_ObjFaninId1p(p->pGia, pObj)), !Gia_ObjFaninC1(pObj) );
sat_solver_clause_new( p->pSat, Lits, Lits + 3, 0 );
pObj->fMark1 = 1;
}
else
{
Lits[1] = Abc_Var2Lit( Bmc_LoadGetSatVar(p, Gia_ObjFaninId0p(p->pGia, pObj)), Gia_ObjFaninC0(pObj) );
sat_solver_clause_new( p->pSat, Lits, Lits + 2, 0 );
Lits[1] = Abc_Var2Lit( Bmc_LoadGetSatVar(p, Gia_ObjFaninId1p(p->pGia, pObj)), Gia_ObjFaninC1(pObj) );
sat_solver_clause_new( p->pSat, Lits, Lits + 2, 0 );
pObj->fMark0 = 1;
}
p->nCallBacks2++;
return 1;
}
/**Function*************************************************************
Synopsis [Checks if the give cut is satisfied.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_SatPathCheckCutSat_rec( Gia_Obj_t * p, int fCompl )
{
if ( Gia_SatObjIsRoot(p) )
return Gia_ObjIsAssigned(p) && Gia_SatObjValue(p) == fCompl;
if ( Gia_SatObjPath0(p) && !Gia_SatPathCheckCutSat_rec( Gia_ObjFanin0(p), fCompl ^ Gia_ObjFaninC0(p) ) )
return 0;
if ( Gia_SatObjPath1(p) && !Gia_SatPathCheckCutSat_rec( Gia_ObjFanin1(p), fCompl ^ Gia_ObjFaninC1(p) ) )
return 0;
return 1;
}
/**Function*************************************************************
Synopsis [Creates a feasible path from the node to a terminal.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Gia_SatPathStart_rec( Gia_Obj_t * p, int fDiffs, int fCompl )
{
if ( Gia_SatObjIsRoot(p) )
return fDiffs && (!Gia_ObjIsAssigned(p) || Gia_SatObjValue(p) != fCompl);
if ( fCompl == 0 )
{
if ( Gia_SatPathStart_rec( Gia_ObjFanin0(p), fDiffs + !Gia_SatObjPath0(p), fCompl ^ Gia_ObjFaninC0(p) ) &&
Gia_SatPathStart_rec( Gia_ObjFanin1(p), fDiffs + !Gia_SatObjPath1(p), fCompl ^ Gia_ObjFaninC1(p) ) )
return Gia_ObjSetDraftPath0(p) + Gia_ObjSetDraftPath1(p);
}
else
{
if ( Gia_SatPathStart_rec( Gia_ObjFanin0(p), fDiffs + !Gia_SatObjPath0(p), fCompl ^ Gia_ObjFaninC0(p) ) )
{
Gia_ObjUnsetDraftPath1(p);
return Gia_ObjSetDraftPath0(p);
}
if ( Gia_SatPathStart_rec( Gia_ObjFanin1(p), fDiffs + !Gia_SatObjPath1(p), fCompl ^ Gia_ObjFaninC1(p) ) )
{
Gia_ObjUnsetDraftPath0(p);
return Gia_ObjSetDraftPath1(p);
}
}
return 0;
}
static inline Aig_Obj_t * Gia_ObjChild0Copy2( Aig_Obj_t ** ppNodes, Gia_Obj_t * pObj, int Id ) { return Aig_NotCond( ppNodes[Gia_ObjFaninId0(pObj, Id)], Gia_ObjFaninC0(pObj) ); }
static inline int Cbs0_VarFanin0Value( Gia_Obj_t * pVar ) { return !Cbs0_VarIsAssigned(Gia_ObjFanin0(pVar)) ? 2 : (Cbs0_VarValue(Gia_ObjFanin0(pVar)) ^ Gia_ObjFaninC0(pVar)); }
Prio0 = Abc_Lit2Var(Gia_ObjFanin0(pObj)->Value);
Prio1 = Abc_Lit2Var(Gia_ObjFanin1(pObj)->Value);
Phase0 = Abc_LitIsCompl(Gia_ObjFanin0(pObj)->Value) ^ Gia_ObjFaninC0(pObj);
Phase1 = Abc_LitIsCompl(Gia_ObjFanin1(pObj)->Value) ^ Gia_ObjFaninC1(pObj);
if ( Phase0 && Phase1 )
Prio = (fGrow & 1) ? Abc_MinInt(Prio0, Prio1) : Abc_MaxInt(Prio0, Prio1);
else if ( Phase0 && !Phase1 )
Prio = Prio1;
else if ( !Phase0 && Phase1 )
Prio = Prio0;
else // if ( !Phase0 && !Phase1 )
Prio = (fGrow & 1) ? Abc_MaxInt(Prio0, Prio1) : Abc_MinInt(Prio0, Prio1);
pObj->Value = Abc_Var2Lit( Prio, Phase0 & Phase1 );
}
Gia_ManForEachCo( p, pObj, i )
pObj->Value = Abc_LitNotCond( Gia_ObjFanin0(pObj)->Value, Gia_ObjFaninC0(pObj) );
}
void Bmc_CexCarePropagateFwd( Gia_Man_t * p, Abc_Cex_t * pCex, int fGrow, Vec_Int_t * vPrios )
{
Gia_Obj_t * pObj, * pObjRo, * pObjRi;
int f, i;
Gia_ManConst0( p )->Value = 0;
Gia_ManForEachRi( p, pObj, i )
pObj->Value = 0;
Vec_IntClear( vPrios );
for ( f = 0; f <= pCex->iFrame; f++ )
{
Gia_ManForEachRiRo( p, pObjRi, pObjRo, i )
Vec_IntPush( vPrios, (pObjRo->Value = pObjRi->Value) );
Bmc_CexCarePropagateFwdOne( p, pCex, f, fGrow );
}
static inline int Tas_VarFanin0Value( Tas_Var_t * pVar ) { return !Tas_VarIsAssigned(Gia_ObjFanin0(pVar)) ? 2 : (Tas_VarValue(Gia_ObjFanin0(pVar)) ^ Gia_ObjFaninC0(pVar)); }
