/**
* Family specific code for writing normalizer.
*
* @param[in] FiveBitExponent The current CPU's family services.
* @param[in] FiveBitMantissa Timepoint designator.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F16MlWriteNormalizer (
IN UINT8 FiveBitExponent,
IN UINT8 FiveBitMantissa,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
D0F0xBC_x3F98C_STRUCT D0F0xBC_x3F98C;
C001_1073_MSR LocalMsrRegister;
LibAmdMsrRead (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);
//Write normalizer as 5-bit exponent and 5 bit mantissa to MSRC001_1073[Exp/Man] and D0F0xBC_x3F98C[Exp/Man]
LocalMsrRegister.Exponent = FiveBitExponent;
LocalMsrRegister.Mantissa = FiveBitMantissa;
LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);
GnbRegisterReadML (GnbGetHandle (StdHeader), D0F0xBC_x3F98C_TYPE, D0F0xBC_x3F98C_ADDRESS, &D0F0xBC_x3F98C, 0, StdHeader);
D0F0xBC_x3F98C.Field.Exponent = FiveBitExponent;
D0F0xBC_x3F98C.Field.Mantissa = FiveBitMantissa;
GnbRegisterWriteML (GnbGetHandle (StdHeader), D0F0xBC_x3F98C_TYPE, D0F0xBC_x3F98C_ADDRESS, &D0F0xBC_x3F98C, 0, StdHeader);
// Toggle the Ready bit to ensure proper operation.
LocalMsrRegister.Ready = 0;
LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);
LocalMsrRegister.Ready = 1;
LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);
IDS_SKIP_HOOK (IDS_MSR_ACCESS_OVERRIDE, NULL, StdHeader) {
LocalMsrRegister.Lock = 1;
LibAmdMsrWrite (MSR_C001_1073, (UINT64 *) (&LocalMsrRegister), StdHeader);
}
AGESA_STATUS
PcieEdpPortPowerCheckCZ (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
GMMx1206C_STRUCT GMMx1206C;
BOOLEAN EdpPresent;
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEdpPortPowerCheckCZ Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
EdpPresent = FALSE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
DdiEdpPortDetectCallbackCZ,
(VOID *)&EdpPresent,
Pcie
);
if (EdpPresent == FALSE) {
// Power off
GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx1206C_TYPE, GMMx1206C_ADDRESS, &GMMx1206C.Value, 0, GnbLibGetHeader (Pcie));
GMMx1206C.Field.LVTMA_PWRSEQ_EN = 0;
GMMx1206C.Field.LVTMA_PWRSEQ_TARGET_STATE = 0;
GMMx1206C.Field.LVTMA_BLON_OVRD = 0;
GnbRegisterWriteCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx1206C_TYPE, GMMx1206C_ADDRESS, &GMMx1206C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidBeforeGfxInitCZ Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* GNB Scs interface
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
GnbScsInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINTN ScsDataAddress;
UINTN ScsDataSize;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = AGESA_SUCCESS;
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
if ((GnbBuildOptionData->CfgUseSMUServices == TRUE) &&
(GnbBuildOptionData->GnbCommonOptions.CfgScsSupport == TRUE)) {
IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Supported\n");
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbGetScsDataML (&ScsDataAddress, &ScsDataSize);
ASSERT (ScsDataAddress != NULL);
Status = GnbSmuLoadScsDataV7 (GnbHandle, (UINT8 *)ScsDataAddress, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Exit [0x%x]\n", Status);
return AgesaStatus;
}
AGESA_STATUS
GfxGBifEnableML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
D0F0xD4_x01301486_STRUCT D0F0xD4_x1301486;
D0F0xD4_x01091518_STRUCT D0F0xD4_x1091518;
D0F0xBC_xC00C0000_STRUCT D0F0xBC_xC00C0000;
GNB_HANDLE *GnbHandle;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxGBifEnableML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xBC_xC00C0000_TYPE, D0F0xBC_xC00C0000_ADDRESS, &D0F0xBC_xC00C0000.Value, 0, StdHeader);
if (D0F0xBC_xC00C0000.Field.GPU_DIS != 1) {
GfxStrapsEarlyInitML (StdHeader);
}
GnbRegisterReadML (GnbHandle, D0F0xD4_x01301486_TYPE, D0F0xD4_x01301486_ADDRESS, &D0F0xD4_x1301486.Value, 0, StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x01091518_TYPE, D0F0xD4_x01091518_ADDRESS, &D0F0xD4_x1091518.Value, 0, StdHeader);
D0F0xD4_x1301486.Field.LinkTrainEn = 0x1;
D0F0xD4_x1091518.Field.LinkTrainEn = 0x1;
GnbRegisterWriteML (GnbHandle, D0F0xD4_x01091518_TYPE, D0F0xD4_x01091518_ADDRESS, &D0F0xD4_x1091518.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbRegisterWriteML (GnbHandle, D0F0xD4_x01301486_TYPE, D0F0xD4_x01301486_ADDRESS, &D0F0xD4_x1301486.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxGBifEnableML Exit\n");
return AGESA_SUCCESS;
}
/**
* Power Up/Down iGPU
*
*
*
* @param[in,out] Gfx Pointer to GFX configuration
* @param[in,out] PowerControl Control power Up/Down iGPU, 0, power down iGPU, 1, power on iGPU
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxRequestGPUPowerV3 (
IN OUT GFX_PLATFORM_CONFIG *Gfx,
IN UINT8 PowerControl
)
{
GNB_HANDLE *GnbHandle;
DEV_OBJECT DevObject;
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
DevObject.GnbHandle = GnbHandle;
DevObject.StdHeader = GnbLibGetHeader (Gfx);
if (PowerControl == 0) {
GnbSmuServiceRequestV7 (
&DevObject,
SMC_MSG_POWERDOWNGPU,
0,
GNB_REG_ACC_FLAG_S3SAVE
);
} else {
GnbSmuServiceRequestV7 (
&DevObject,
SMC_MSG_POWERUPGPU,
0,
GNB_REG_ACC_FLAG_S3SAVE
);
}
return AGESA_SUCCESS;
}
AGESA_STATUS
GnbEarlierInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT32 D0F0xBC_xC00C002C;
FIRMWARE_HEADER_V7 *SmuFwHeader;
UINTN SmuFwSize;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
UINT32 PspMBox;
AgesaStatus = AGESA_SUCCESS;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEarlierInitTableBeforeSmuML,
0,
0,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
SmuFwHeader = NULL;
GnbRegisterReadML (GnbHandle, D0F0xBC_xC00C002C_TYPE, D0F0xBC_xC00C002C_ADDRESS, &D0F0xBC_xC00C002C, 0, StdHeader);
D0F0xBC_xC00C002C &= (BIT1 + BIT2 + BIT3 + BIT4 + BIT5);
IDS_HDT_CONSOLE (GNB_TRACE, " D0F0xBC_xC00C002C = 0x%x\n", D0F0xBC_xC00C002C);
Status = GnbLoadBuildOptionDataML (StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
//Load the SMU for non secure part & blank part
if ((D0F0xBC_xC00C002C == 0) || (D0F0xBC_xC00C002C == BIT5 + BIT3)) {
Status = GnbGetSmuFirmwareML ((UINTN *)&SmuFwHeader, &SmuFwSize);
ASSERT (SmuFwHeader != NULL);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GnbSmuFirmwareLoadV7 (GnbHandle, SmuFwHeader, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
} else {
Status = GnbPspMBoxRead (&PspMBox, GnbHandle, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, " PSP Mailbox Status = 0x%x\n", PspMBox);
if (Status == AGESA_SUCCESS) {
if ((PspMBox & MBOX_STATUS_RECOVERY) == MBOX_STATUS_RECOVERY) {
/// SET CfgUseSMUServices flag for recovery mode
GnbBuildOptionData->CfgUseSMUServices = FALSE;
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Exit [0x%x]\n", Status);
return AgesaStatus;
}
/**
* Get system PLL COF
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval System PLL COF
*/
UINT32
GfxLibGetSystemPllCofKB (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 v0;
GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0500000, &v0, 0, StdHeader);
return 100 * (((v0 >> 1) & 0x3F) + 0x10);
}
BOOLEAN
GfxIsVbiosPostedKB (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
UINT32 D0F0xBC_xC0200000;
GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Gfx)), 0x4, 0xC0200000, &D0F0xBC_xC0200000, 0, GnbLibGetHeader (Gfx));
return (((D0F0xBC_xC0200000 >> 16) & 1) == 0) ? TRUE : FALSE;
}
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Kabini core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 HtcTempLimit;
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
UINT32 D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0107097, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = (D0F0xBC_xC0107097 >> 3) & 0x7F;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
if ((PlatformConfig->HtcTemperatureLimit >= 520) && (PlatformConfig->LhtcTemperatureLimit != 0)) {
HtcTempLimit = ((PlatformConfig->HtcTemperatureLimit - 520) / 5);
if (HtcTempLimit < HtcReg.HtcTmpLmt) {
HtcReg.HtcTmpLmt = HtcTempLimit;
}
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
/**
* Initialize GFX straps.
*
*
* @param[in] StdHeader Standard configuration header
*/
VOID
GfxStrapsEarlyInitML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_EARLY_PARAMS *EarlyParamsPtr;
D0F0xD4_x013014AC_STRUCT D0F0xD4_x13014AC;
D0F0xD4_x013014B6_STRUCT D0F0xD4_x13014B6;
D0F0xD4_x013014B8_STRUCT D0F0xD4_x013014B8;
D0F0xD4_x013014BA_STRUCT D0F0xD4_x013014BA;
D0F0xD4_x013014BE_STRUCT D0F0xD4_x13014BE;
GNB_HANDLE *GnbHandle;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEarlyInitML Enter\n");
EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader;
GnbHandle = GnbGetHandle (StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014AC_TYPE, D0F0xD4_x013014AC_ADDRESS, &D0F0xD4_x13014AC.Value, 0, StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014B6_TYPE, D0F0xD4_x013014B6_ADDRESS, &D0F0xD4_x13014B6.Value, 0, StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014B8_TYPE, D0F0xD4_x013014B8_ADDRESS, &D0F0xD4_x013014B8.Value, 0, StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014BA_TYPE, D0F0xD4_x013014BA_ADDRESS, &D0F0xD4_x013014BA.Value, 0, StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014BE_TYPE, D0F0xD4_x013014BE_ADDRESS, &D0F0xD4_x13014BE.Value, 0, StdHeader);
D0F0xD4_x13014B6.Field.StrapBifAzLegacyDeviceTypeDis = 0x0;
D0F0xD4_x13014B6.Field.StrapBifF0LegacyDeviceTypeDis = 0x0;
D0F0xD4_x13014AC.Field.StrapBifAudioEnPin = EarlyParamsPtr->PlatformConfig.GnbHdAudio;
D0F0xD4_x13014B6.Field.StrapBifAudioEn = EarlyParamsPtr->PlatformConfig.GnbHdAudio;
// Enable PCI Vendor Specific Capabilities
D0F0xD4_x13014BE.Field.StrapBifSymalignHwDebug = 1;
D0F0xD4_x013014B8.Field.STRAP_BIF_F0_ATS_EN = 1;
D0F0xD4_x013014B8.Field.STRAP_BIF_MAX_PASID_WIDTH = 0x10;
D0F0xD4_x013014B8.Field.STRAP_BIF_PASID_PREFIX_SUPPORTED = 1;
D0F0xD4_x013014B8.Field.STRAP_BIF_EXTENDED_FMT_SUPPORTED_A = 1;
D0F0xD4_x013014B8.Field.STRAP_BIF_E2E_PREFIX_EN_A = 1;
D0F0xD4_x013014BA.Field.STRAP_BIF_F0_PAGE_REQ_EN = 1;
D0F0xD4_x013014BA.Field.STRAP_BIF_F0_PASID_EN = 1;
D0F0xD4_x013014BA.Field.STRAP_BIF_PASID_EXE_PERMISSION_SUP = 1;
D0F0xD4_x013014BA.Field.STRAP_BIF_PASID_PRIV_MODE_SUP = 1;
D0F0xD4_x013014BA.Field.STRAP_BIF_PASID_GLOBAL_INVALID_SUP = 1;
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014AC_TYPE, D0F0xD4_x013014AC_ADDRESS, &D0F0xD4_x13014AC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014B6_TYPE, D0F0xD4_x013014B6_ADDRESS, &D0F0xD4_x13014B6.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014B8_TYPE, D0F0xD4_x013014B8_ADDRESS, &D0F0xD4_x013014B8.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014BA_TYPE, D0F0xD4_x013014BA_ADDRESS, &D0F0xD4_x013014BA.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014BE_TYPE, D0F0xD4_x013014BE_ADDRESS, &D0F0xD4_x13014BE.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEarlyInitML Exit\n");
}
/**
* Callback to Enable IOAPIC on GNB
*
*
*
* @param[in] Descriptor Silicon descriptor
* @param[in] Buffer Pointer to buffer
* @param[in] Pcie Pointer to global PCIe configuration
* @retval AGESA_STATUS
*/
AGESA_STATUS
IoapicEnableCallbackV5 (
IN PCIe_DESCRIPTOR_HEADER *Descriptor,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCI_ADDR GnbPciAddress;
D0F0xFC_x00_STRUCT D0F0xFC_x00;
UINT32 *AddressPtr;
UINT32 AddressLow;
UINT32 AddressHigh;
D0F0xFC_x00.Value = 0x0;
D0F0xFC_x00.Field.IoapicEnable = 1;
// Set the extended ID enable (default)
D0F0xFC_x00.Field.IoapicIdExtEn = 1;
// Enable SB feature for every APIC. ACPI OS may disable this once the OS boots
D0F0xFC_x00.Field.IoapicSbFeatureEn = 1;
AddressPtr = (UINT32*) Buffer;
AddressLow = AddressPtr[0] & 0xFFFFFF00;
AddressHigh = AddressPtr[1];
// Get the PCI address of the GNB
GnbPciAddress = GnbGetHostPciAddress (GnbGetHandle (GnbLibGetHeader (Pcie)));
// If the BLDCFG base address is null, assume that the base address of the APIC has already been programmed
// If base address is defined in BLDCFG, program it here
if ((AddressLow != NULL) || (AddressHigh != NULL)) {
GnbLibPciIndirectWrite (
GnbPciAddress.AddressValue | D0F0xF8_ADDRESS,
D0F0xFC_x01_ADDRESS,
AccessS3SaveWidth32,
&AddressLow,
GnbLibGetHeader (Pcie)
);
GnbLibPciIndirectWrite (
GnbPciAddress.AddressValue | D0F0xF8_ADDRESS,
D0F0xFC_x02_ADDRESS,
AccessS3SaveWidth32,
&AddressHigh,
GnbLibGetHeader (Pcie)
);
IDS_HDT_CONSOLE (GNB_TRACE, "GNB IOAPIC base address is at high %x, low %x\n", AddressHigh, AddressLow);
// Enable the IOAPIC.
GnbLibPciIndirectWrite (
GnbPciAddress.AddressValue | D0F0xF8_ADDRESS,
D0F0xFC_x00_ADDRESS,
AccessS3SaveWidth32,
&D0F0xFC_x00.Value,
GnbLibGetHeader (Pcie)
);
}
return AGESA_SUCCESS;
}
/**
* Callback to power up panel on DDI ports with eDP connectors
*
*
*
*
* @param[in] Engine Pointer to engine config descriptor
* @param[in, out] Buffer Not used
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
DdiPostPortInitCallbackML (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
GMMx6464_STRUCT GMMx6464;
GMMx5C6C_STRUCT GMMx5C6C;
GMMx5C90_STRUCT GMMx5C90;
IDS_HDT_CONSOLE (GNB_TRACE, "DdiPostPortInitCallbackML Enter\n");
if ((Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ||
(Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDpToLvds) ||
(Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) ||
(Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvdsSwInit)) {
IDS_HDT_CONSOLE (GNB_TRACE, "Found eDP/LVDS Connector\n");
GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx6464_TYPE, GMMx6464_ADDRESS, &GMMx6464.Value, 0, GnbLibGetHeader (Pcie));
GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx5C90_TYPE, GMMx5C90_ADDRESS, &GMMx5C90.Value, 0, GnbLibGetHeader (Pcie));
GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx5C6C_TYPE, GMMx5C6C_ADDRESS, &GMMx5C6C.Value, 0, GnbLibGetHeader (Pcie));
GMMx6464.Field.LVTMA_PWRSEQ_EN = 1;
GMMx6464.Field.LVTMA_PWRSEQ_TARGET_STATE = 1;
GMMx6464.Field.LVTMA_BLON_OVRD = 1;
GMMx5C90.Field.PLL_SPARE = 1;
GMMx5C6C.Field.PLL_REFCLK_SEL = 1;
GnbRegisterWriteML (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx6464_TYPE, GMMx6464_ADDRESS, &GMMx6464.Value, 0, GnbLibGetHeader (Pcie));
GnbRegisterWriteML (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx5C90_TYPE, GMMx5C90_ADDRESS, &GMMx5C90.Value, 0, GnbLibGetHeader (Pcie));
GnbRegisterWriteML (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx5C6C_TYPE, GMMx5C6C_ADDRESS, &GMMx5C6C.Value, 0, GnbLibGetHeader (Pcie));
}
IDS_HDT_CONSOLE (GNB_TRACE, "DdiPostPortInitCallbackML Exit\n");
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyExecuteReconfigV5 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
PCIe_SILICON_CONFIG *Silicon;
DEV_OBJECT DevObject;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Enter\n");
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
D0F0xE4_WRAP_8062.Field.ResetPeriod = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
DevObject.StdHeader = GnbLibGetHeader (Pcie);
DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue;
GnbSmuServiceRequestV7 (
&DevObject,
SMC_MSG_RECONFIGURE,
Wrapper->WrapId,
0
);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Exit\n");
}
}
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Mullins core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16MlInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
D0F0xBC_xC0107097_STRUCT D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadML (GnbGetHandle (StdHeader), D0F0xBC_xC0107097_TYPE, D0F0xBC_xC0107097_ADDRESS, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = D0F0xBC_xC0107097.Field.HtcTmpLmt;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
}
return AGESA_SUCCESS;
}
VOID
GfxFmDisableController (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GFX_FAM_SERVICES *GfxFamilyService;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), &GfxFamilyService, StdHeader);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
GfxFamilyService->GfxDisableController (StdHeader);
}
}
BOOLEAN
GfxFmIsVbiosPosted (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS Status;
GFX_FAM_SERVICES *GfxFamilyService;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), &GfxFamilyService, GnbLibGetHeader (Gfx));
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
return GfxFamilyService->GfxIsVbiosPosted (Gfx);
}
return TRUE;
}
UINT32
GfxFmCalculateClock (
IN UINT8 Did,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GFX_FAM_SERVICES *GfxFamilyService;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), &GfxFamilyService, StdHeader);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
return GfxFamilyService->GfxCalculateClock (Did, StdHeader);
}
return 200*100;
}
AGESA_STATUS
GfxPostInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_POST_PARAMS *PostParamsPtr;
AGESA_STATUS Status;
GFX_PLATFORM_CONFIG *Gfx;
D0F0xBC_xC00C0000_STRUCT D0F0xBC_xC00C0000;
D0F0xD4_x013014AC_STRUCT D0F0xD4_x13014AC;
D0F0xD4_x013014B6_STRUCT D0F0xD4_x13014B6;
GNB_HANDLE *GnbHandle;
PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
ASSERT (GnbHandle != NULL);
GnbRegisterReadML (GnbHandle, D0F0xBC_xC00C0000_TYPE,
D0F0xBC_xC00C0000_ADDRESS, &D0F0xBC_xC00C0000.Value, 0, StdHeader);
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
if (D0F0xBC_xC00C0000.Field.GPU_DIS == 1) {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
Gfx->GfxFusedOff = TRUE;
}
} else {
PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
}
if (PostParamsPtr->MemConfig.UmaMode == UMA_NONE) {
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014AC_TYPE, D0F0xD4_x013014AC_ADDRESS, &D0F0xD4_x13014AC.Value, 0, StdHeader);
GnbRegisterReadML (GnbHandle, D0F0xD4_x013014B6_TYPE, D0F0xD4_x013014B6_ADDRESS, &D0F0xD4_x13014B6.Value, 0, StdHeader);
D0F0xD4_x13014AC.Field.StrapBifAudioEnPin = FALSE;
D0F0xD4_x13014B6.Field.StrapBifAudioEn = FALSE;
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014AC_TYPE, D0F0xD4_x013014AC_ADDRESS, &D0F0xD4_x13014AC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
GnbRegisterWriteML (GnbHandle, D0F0xD4_x013014B6_TYPE, D0F0xD4_x013014B6_ADDRESS, &D0F0xD4_x13014B6.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
if (D0F0xBC_xC00C0000.Field.GPU_DIS != 1) {
// Power down iGPU
GfxRequestGPUPowerV3 (Gfx, 0);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceML Exit [0x%x]\n", Status);
return Status;
}
/**
* Family specific time stamp function
*
*
* @param[in] StdHeader Standard configuration header
* @retval Count
*/
UINT32
GnbFmTimeStamp (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GNB_FAM_TS_SERVICES *GnbFamTsFunc;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbLibLocateService (GnbFamTsService, GnbGetSocketId (GnbHandle), &GnbFamTsFunc, StdHeader);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
return GnbFamTsFunc->GnbFmTimeStamp (StdHeader);
}
return 0;
}
/**
* Map graphics engine to display path
*
*
*
*
* @param[in] Engine Engine configuration info
* @param[out] DisplayPathList Display path list
* @param[in] Gfx Pointer to global GFX configuration
*
*/
AGESA_STATUS
GfxFmMapEngineToDisplayPath (
IN PCIe_ENGINE_CONFIG *Engine,
OUT EXT_DISPLAY_PATH *DisplayPathList,
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS Status;
GFX_FAM_SERVICES *GfxFamilyService;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), &GfxFamilyService, GnbLibGetHeader (Gfx));
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
return GfxFamilyService->GfxMapEngineToDisplayPath (Engine, DisplayPathList, Gfx);
}
return Status;
}
AGESA_STATUS
GfxEnableGmmAccessV5 (
IN OUT GFX_PLATFORM_CONFIG *Gfx
)
{
UINT32 Value;
GNB_HANDLE *GnbHandle;
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
ASSERT (GnbHandle != NULL);
// GmmBase should be 0 before enable.
ASSERT (GnbHandle->GmmBase == 0);
if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for GMM allocated by reading D1F0x24 Graphics Memory Mapped Base Address
Gfx->GmmBase = 0;
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x24, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
Gfx->GmmBase |= (Value & 0xfffffff0);
if (Gfx->GmmBase == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
// Check if base address for FB allocated
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
if ((Value & 0xfffffff0) == 0) {
IDS_ERROR_TRAP;
return AGESA_ERROR;
}
//Push CPU MMIO pci config to S3 script
GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
// Turn on memory decoding on GFX to enable access to GMM register space
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
//Push iGPU pci config to S3 script
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
GnbHandle->GmmBase = Gfx->GmmBase;
return AGESA_SUCCESS;
}
/**
* Get GnbBuildOptionsCommon Structure
*
*
*
* @param[in] StdHeader Standard Configuration Header
* @retval pointer to SSTD table
*/
VOID *
GnbFmGnbBuildOptions (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GNB_FAM_BUILDOPTIONS_POINTERS *GnbFamilyBuildOptionsService;
GNB_HANDLE *GnbHandle;
VOID *GnbBuildOptionsPtr;
GnbBuildOptionsPtr = NULL;
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbLibLocateService (GnbFamBuildOptionPointer, GnbGetSocketId (GnbHandle), &GnbFamilyBuildOptionsService, StdHeader);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
GnbBuildOptionsPtr = GnbFamilyBuildOptionsService->GnbFmGetBuildOptions (StdHeader);
}
return GnbBuildOptionsPtr;
}
/**
* Get base SSDT table
*
*
*
* @param[in] StdHeader Standard Configuration Header
* @retval pointer to SSTD table
*/
VOID *
GnbFmAlibGetBaseTable (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GNB_FAM_ALIB_SERVICES *GnbFamilyAlibService;
GNB_HANDLE *GnbHandle;
VOID *AlibSsdtTable;
AlibSsdtTable = NULL;
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbLibLocateService (GnbFamAlibService, GnbGetSocketId (GnbHandle), &GnbFamilyAlibService, StdHeader);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
AlibSsdtTable = GnbFamilyAlibService->GnbFmAlibGetBaseTable (StdHeader);
}
return AlibSsdtTable;
}
AGESA_STATUS
GnbEarlyInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT32 Property;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
Property = TABLE_PROPERTY_DEFAULT;
Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? TABLE_PROPERTY_NMI_SYNCFLOOD : 0;
IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG, GnbHandle, StdHeader);
GnbInitSmuBiosTableML (StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEarlyInitTableML,
Property,
0,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (GnbBuildOptionData->CfgUseSMUServices == TRUE) {
GnbRequestVddNbPminML (GnbHandle, StdHeader);
}
Status = GfxGBifEnableML (StdHeader);
ASSERT (Status == AGESA_SUCCESS);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Set Dll Cap based on fuses
*
*
*
* @param[in] Wrapper Pointer to Wrapper configuration data area
* @param[in] Pcie Pointer to PCIe configuration data area
*/
VOID
PcieSetDllCapTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D18F3x1FC_STRUCT D18F3x1FC;
D0F0xE4_PHY_500F_STRUCT D0F0xE4_PHY_500F;
D0F0xE4_PHY_4010_STRUCT D0F0xE4_PHY_4010;
D0F0xE4_PHY_4011_STRUCT D0F0xE4_PHY_4011;
UINT32 Gen1Index;
UINT32 Gen2Index;
CPU_LOGICAL_ID LogicalId;
GNB_HANDLE *GnbHandle;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n");
D0F0xE4_PHY_500F.Value = 0;
GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
ASSERT (GnbHandle != NULL);
GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie));
//Read SWDllCapTableEn
GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie));
IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value);
if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & AMD_F15_TN_A0) != AMD_F15_TN_A0 )) {
IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n");
// Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0])
IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS));
D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value);
// Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0])
IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS));
D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value);
// If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0
// Else...
// If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical
// If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast
// If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow
IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl);
if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) {
IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp);
Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1;
} else {
IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case...");
switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) {
case 0:
IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n");
Gen1Index = 0xd;
break;
case 1:
IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n");
Gen1Index = 0xf;
break;
case 2:
IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n");
Gen1Index = 0xa;
break;
default:
IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n");
Gen1Index = 0xd; //Use typical for default case
break;
}
}
D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index;
IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index);
// Bits 3:0 = Gen1Index[3:0]
// Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0]
if (D18F3x1FC.Field.SWDllCapTableEn != 0) {
IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50);
Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50;
} else {
Gen2Index = 0x03; // Hard coded default
}
D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index;
IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index);
PcieRegisterWrite (
Wrapper,
PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
D0F0xE4_PHY_500F.Value,
FALSE,
Pcie
);
// Set DllProcessFreqCtlOverride on second write
D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
PcieRegisterWrite (
Wrapper,
PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
D0F0xE4_PHY_500F.Value,
FALSE,
Pcie
);
if (Wrapper->WrapId == 1) {
// For Wrapper 1, configure PHY0 and PHY1
D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0;
PcieRegisterWrite (
Wrapper,
PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
D0F0xE4_PHY_500F.Value,
FALSE,
Pcie
);
// Set DllProcessFreqCtlOverride on second write
D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
PcieRegisterWrite (
Wrapper,
PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
D0F0xE4_PHY_500F.Value,
FALSE,
Pcie
);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n");
}
AGESA_STATUS
GfxMidInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GFX_PLATFORM_CONFIG *Gfx;
UINT8 AudioEPCount;
GMMx5F50_STRUCT GMMx5F50;
AMD_MID_PARAMS *MidParamsPtr;
UINT8 MaxAudioEndpoints;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_FATAL) {
GfxFmDisableController (StdHeader);
} else {
if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
Status = GfxEnableGmmAccessV3 (Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status != AGESA_SUCCESS) {
// Can not initialize GMM registers going to disable GFX controller
IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n");
Gfx->UmaInfo.UmaMode = UMA_NONE;
GfxFmDisableController (StdHeader);
} else {
MidParamsPtr = (AMD_MID_PARAMS *) StdHeader;
MaxAudioEndpoints = MidParamsPtr->GnbMidConfiguration.MaxNumAudioEndpoints;
Status = GfxGmcInitML (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxSamuInit (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxInitSsid (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
AudioEPCount = 0;
Status = GfxIntAudioEPEnumV3 (Gfx, &AudioEPCount);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (AudioEPCount > MaxAudioEndpoints) {
AudioEPCount = MaxAudioEndpoints;
}
if (AudioEPCount > GnbBuildOptionsML.GnbCommonOptions.CfgGnbNumDisplayStreamPipes) {
AudioEPCount = GnbBuildOptionsML.GnbCommonOptions.CfgGnbNumDisplayStreamPipes;
}
AudioEPCount = 7 - AudioEPCount;
GnbRegisterReadML (GnbGetHandle (StdHeader), GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, 0, StdHeader);
GMMx5F50.Field.PORT_CONNECTIVITY = AudioEPCount;
GMMx5F50.Field.PORT_CONNECTIVITY_OVERRIDE_ENABLE = 1;
GnbRegisterWriteML (GnbGetHandle (StdHeader), GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GfxSamuInit (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
UINT32 D0F0xBC_xC00C0000;
GNB_HANDLE *GnbHandle;
VOID *ControlXBuffer;
VOID *AlignedControlXBuffer;
VOID *PatchYBuffer;
VOID *AlignedPatchYBuffer;
SAMU_BOOT_CONTROL *SamuBootControl;
UINT32 D0F0xBC_x800000A4;
UINT32 GMMx22000;
UINT32 GMMx22004;
UINT32 GMMx22008;
UINT32 GMMx2200C;
UINT32 LoopCount;
BOOLEAN SamuUseF1dPatch;
BOOLEAN SamuPatchEnabled;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbSamuInit Enter\n");
GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
ASSERT (GnbHandle != NULL);
GnbRegisterReadKB (GnbHandle, 0x4, 0xc00c0000,
&D0F0xBC_xC00C0000, 0, GnbLibGetHeader (Gfx));
SamuPatchEnabled = GnbBuildOptions.CfgSamuPatchEnabled;
IDS_OPTION_HOOK (IDS_GNB_LOAD_SAMU_PATCH, &SamuPatchEnabled, GnbLibGetHeader (Gfx));
if ((((D0F0xBC_xC00C0000) & BIT24) == 0) &&
(SamuPatchEnabled == TRUE)) {
// Decide which version of the patch to use
SamuUseF1dPatch = TRUE;
GMMx22008 = 0x29;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008,
&GMMx22008, 0, GnbLibGetHeader (Gfx));
GnbRegisterReadKB (GnbHandle, 0x12, 0x2200C,
&GMMx2200C, 0, GnbLibGetHeader (Gfx));
IDS_HDT_CONSOLE (GNB_TRACE, " SAMSAB:29=%08x\n", GMMx2200C);
if (GMMx2200C == 0x80000001) {
SamuUseF1dPatch = FALSE;
}
ControlXBuffer = GnbAllocateHeapBufferAndClear (AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
ASSERT (ControlXBuffer != NULL);
if (ControlXBuffer == NULL) {
return AGESA_ERROR;
}
AlignedControlXBuffer = (VOID *) (((UINTN)ControlXBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE));
PatchYBuffer = GnbAllocateHeapBuffer (AMD_GNB_SAMU_PATCH_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
ASSERT (PatchYBuffer != NULL);
if (PatchYBuffer == NULL) {
return AGESA_ERROR;
}
AlignedPatchYBuffer = (VOID *) (((UINTN)PatchYBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE));
// Copy samu firmware patch to PatchYBuffer
if (SamuUseF1dPatch == TRUE) {
LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKB[0],
SamuPatchKBHeader[1], GnbLibGetHeader (Gfx));
} else {
LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKBUnf1[0],
SamuPatchKBHeaderUnf1[1], GnbLibGetHeader (Gfx));
}
// WBINVD
LibAmdWriteBackInvalidateCache ();
// Load boot control structure
SamuBootControl = (SAMU_BOOT_CONTROL *)AlignedControlXBuffer;
SamuBootControl->BootControl = 0x3;
SamuBootControl->KernelAddrLo = (UINTN)AlignedPatchYBuffer;
SamuBootControl->KernelAddrHi = ((((UINT64)(UINTN)AlignedPatchYBuffer) >> 32) & 0xFF);
if (SamuUseF1dPatch == TRUE) {
SamuBootControl->TweakSelect = 0xBB027E1F;
SamuBootControl->KeySelect = 0x8E174F83;
} else {
SamuBootControl->TweakSelect = 0x0;
SamuBootControl->KeySelect = 0x0;
}
// Write 0x0 to SAM_CGC_HOST_CTRL to release the clock-gating of SAMU
GMMx22000 = 0x3;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GMMx22004 = 0x0;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
// Write (physical address of boot control structure)>>8 into SAM_SAB_INIT_TLB_CONFIG (Location X >> 8)
GMMx22008 = 0x4;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, &GMMx22008, 0, GnbLibGetHeader (Gfx));
GMMx2200C = ((UINTN) AlignedControlXBuffer) >> 8;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x2200C, &GMMx2200C, 0, GnbLibGetHeader (Gfx));
// Write 0x0 to SAM_RST_HOST_SOFT_RESET
GMMx22000 = 0x1;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GMMx22004 = 0x0;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
// Write 0x2 to SAM_SCRATCH_0 to start the firmware boot
GMMx22000 = 0x38;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GMMx22004 = 0x2;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
// Poll SAM_RST_HOST_SOFT_RST_RDY and wait for HOST_RDY
do {
// Write 0x2 to SAM_SCRATCH_0 to start the firmware boot
GMMx22000 = 0x51;
GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx));
GnbRegisterReadKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx));
} while ((GMMx22004 & BIT0) == 0);
// Clear the allocated memory ranges, locations X and Y (write 0), issue WBINVD
LibAmdMemFill (ControlXBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
LibAmdMemFill (PatchYBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx));
LibAmdWriteBackInvalidateCache ();
// Confirm read of SMC_DRAM_ACCESS_CNTL is 0x1
D0F0xBC_x800000A4 = 0;
for (LoopCount = 0; LoopCount < 0x00FFFFFF; LoopCount++) {
GnbRegisterReadKB (GnbHandle, 0x4, 0x800000A4, &D0F0xBC_x800000A4, 0, GnbLibGetHeader (Gfx));
if ((D0F0xBC_x800000A4 & BIT0) != 0) {
break;
}
}
ASSERT ((D0F0xBC_x800000A4 & BIT0) != 0);
}
AGESA_STATUS
GnbLoadBuildOptionDataML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
GNB_HANDLE *GnbHandle;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
UINT32 D0F0xBC_xC01040D0;
CPU_LOGICAL_ID LogicalCpuid;
D18F3xA0_STRUCT D18F3xA0;
Status = AGESA_SUCCESS;
GnbBuildOptionData = (GNB_BUILD_OPTIONS_ML *) GnbAllocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, sizeof (GNB_BUILD_OPTIONS_ML), StdHeader);
ASSERT (GnbBuildOptionData != NULL);
GnbHandle = GnbGetHandle (StdHeader);
GnbBuildOptionData->GnbCommonOptions.CfgScsSupport = GnbBuildOptionsML.GnbCommonOptions.CfgScsSupport;
GnbBuildOptionData->GnbCommonOptions.CfgUmaSteering = GnbBuildOptionsML.GnbCommonOptions.CfgUmaSteering;
GnbBuildOptionData->GnbCommonOptions.GmcPowerGating = GnbBuildOptionsML.GnbCommonOptions.GmcPowerGating;
GnbBuildOptionData->GnbCommonOptions.CfgGmcClockGating = GnbBuildOptionsML.GnbCommonOptions.CfgGmcClockGating;
GnbBuildOptionData->GnbCommonOptions.CfgOrbDynWakeEnable = GnbBuildOptionsML.GnbCommonOptions.CfgOrbDynWakeEnable;
GnbBuildOptionData->GnbCommonOptions.CfgOrbClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgOrbClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.CfgIommuL1ClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgIommuL1ClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.CfgIommuL2ClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgIommuL2ClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.LclkDeepSleepEn = GnbBuildOptionsML.GnbCommonOptions.LclkDeepSleepEn;
GnbBuildOptionData->GnbCommonOptions.LclkDpmEn = GnbBuildOptionsML.GnbCommonOptions.LclkDpmEn;
GnbBuildOptionData->GnbCommonOptions.CfgIocLclkClockGatingEnable = GnbBuildOptionsML.GnbCommonOptions.CfgIocLclkClockGatingEnable;
GnbBuildOptionData->GnbCommonOptions.CfgBapmSupport = GnbBuildOptionsML.GnbCommonOptions.CfgBapmSupport;
GnbBuildOptionData->GnbCommonOptions.CfgDcTdpEnable = GnbBuildOptionsML.GnbCommonOptions.CfgDcTdpEnable;
GnbBuildOptionData->CfgLhtcSupport = GnbBuildOptionsML.CfgLhtcSupport;
GnbBuildOptionData->CfgSviRevision = GnbBuildOptionsML.CfgSviRevision;
GnbBuildOptionData->CfgSamuPatchEnabled = GnbBuildOptionsML.CfgSamuPatchEnabled;
GnbBuildOptionData->CfgTdcSupport = GnbBuildOptionsML.CfgTdcSupport;
GnbBuildOptionData->CfgNativeGen1PLL = GnbBuildOptionsML.CfgNativeGen1PLL;
GnbBuildOptionData->CfgPciePhyIsolationEnable = GnbBuildOptionsML.CfgPciePhyIsolationEnable;
GnbBuildOptionData->CfgLinkBwNotificationEn = GnbBuildOptionsML.CfgLinkBwNotificationEn;
GnbBuildOptionData->CfgBatteryBoostEn = UserOptions.CfgBatteryBoostEn;
GnbBuildOptionData->CfgSpgClockGatingEnable = GnbBuildOptionsML.CfgSpgClockGatingEnable;
GnbBuildOptionData->CfgPspDpmEn = GnbBuildOptionsML.CfgPspDpmEn;
GnbBuildOptionData->CfgSMUServiceEnablementBitMap = GnbBuildOptionsML.CfgSMUServiceEnablementBitMap;
GnbBuildOptionData->CfgUseSMUServices = GnbBuildOptionsML.CfgUseSMUServices;
// Check for BAPM capability
GnbRegisterReadML (GnbHandle, D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0, 0, StdHeader);
GetLogicalIdOfCurrentCore (&LogicalCpuid, StdHeader);
if (((LogicalCpuid.Family & AMD_FAMILY_16_ML) != 0)
&& ((LogicalCpuid.Revision & AMD_F16_ML_A0) != 0)
&& (D18F3xA0.Field.ConfigId < 35)) {
// BAPM is not supported on A0 ES1 config IDs
// Reduce SMU service enablement to supported services
GnbBuildOptionData->CfgSMUServiceEnablementBitMap = 0x003C0040ul;
}
IDS_HDT_CONSOLE (GNB_TRACE, "SMUServiceEnablementBitMap = 0x%x\n", GnbBuildOptionData->CfgSMUServiceEnablementBitMap);
IDS_OPTION_HOOK (IDS_GNB_LOAD_BUILD_OPTIONS, GnbBuildOptionData, StdHeader);
// Check fuse state of BBB feature.
GnbRegisterReadML (GnbHandle, D0F0xBC_xC01040D0_TYPE, D0F0xBC_xC01040D0_ADDRESS, &D0F0xBC_xC01040D0, 0, StdHeader);
if ((D0F0xBC_xC01040D0 & BIT15) == 0) {
GnbBuildOptionData->CfgBatteryBoostEn = FALSE;
}
GnbDumpBuildOptionDataML (GnbBuildOptionData);
return Status;
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PcieTopologyExecuteReconfigCZ (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_CORE_0101_STRUCT D0F0xE4_CORE_0101;
PCIe_SILICON_CONFIG *Silicon;
DEV_OBJECT DevObject;
UINT32 SmuArg[6];
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Enter\n");
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x1;
D0F0xE4_CORE_0101.Field.RESET_PERIOD = 0x2;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
Silicon = PcieConfigGetParentSilicon (Wrapper);
DevObject.StdHeader = GnbLibGetHeader (Pcie);
DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue;
LibAmdMemFill (SmuArg, 0x00, sizeof (SmuArg), GnbLibGetHeader (Pcie));
SmuArg [0] = Wrapper->WrapId;
GnbSmuServiceRequestV8 (
&DevObject,
SMC_MSG_RECONFIGURE_SB,
SmuArg,
0
);
D0F0xE4_CORE_0101.Value = PcieRegisterRead (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
Pcie
);
D0F0xE4_CORE_0101.Field.RECONFIGURE_EN = 0x0;
PcieRegisterWrite (
Wrapper,
CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_0101_ADDRESS),
D0F0xE4_CORE_0101.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigCZ Exit\n");
}
}
/**
* Request boot up voltage
*
*
*
* @param[in] LinkCap Global GEN capability
* @param[in] Pcie Pointer to PCIe configuration data area
*/
VOID
PcieSetVoltageML (
IN PCIE_LINK_SPEED_CAP LinkCap,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 TargetVid;
UINT8 MinVidIndex;
UINT8 VddNbVid[5];
UINT8 Index;
PP_FUSE_ARRAY_V2 *PpFuseArray;
UINT32 Millivolt;
D0F0xBC_xC0104007_STRUCT D0F0xBC_xC0104007;
D0F0xBC_xC0104008_STRUCT D0F0xBC_xC0104008;
D0F0xBC_xC010407C_STRUCT D0F0xBC_xC010407C;
D0F0xBC_xC0107064_STRUCT D0F0xBC_xC0107064;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageML Enter\n");
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie));
if (PpFuseArray == NULL) {
IDS_HDT_CONSOLE (GNB_TRACE, " PpFuseArray is NULL\n");
GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0104007_TYPE, D0F0xBC_xC0104007_ADDRESS, &D0F0xBC_xC0104007, 0, GnbLibGetHeader (Pcie));
GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0104008_TYPE, D0F0xBC_xC0104008_ADDRESS, &D0F0xBC_xC0104008, 0, GnbLibGetHeader (Pcie));
GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC010407C_TYPE, D0F0xBC_xC010407C_ADDRESS, &D0F0xBC_xC010407C, 0, GnbLibGetHeader (Pcie));
GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0107064_TYPE, D0F0xBC_xC0107064_ADDRESS, &D0F0xBC_xC0107064, 0, GnbLibGetHeader (Pcie));
VddNbVid[0] = (UINT8) D0F0xBC_xC0104007.Field.VddNbVid0;
VddNbVid[1] = (UINT8) D0F0xBC_xC0104008.Field.VddNbVid1;
VddNbVid[2] = (UINT8) D0F0xBC_xC0104008.Field.VddNbVid2;
VddNbVid[3] = (UINT8) D0F0xBC_xC0104008.Field.VddNbVid3;
VddNbVid[4] = (UINT8) D0F0xBC_xC010407C.Field.VddNbVid4;
Index = (UINT8) D0F0xBC_xC0107064.Field.PcieGen2Vid;
} else {
IDS_HDT_CONSOLE (GNB_TRACE, " PpFuseArray is Active\n");
VddNbVid[0] = PpFuseArray->VddNbVid[0];
VddNbVid[1] = PpFuseArray->VddNbVid[1];
VddNbVid[2] = PpFuseArray->VddNbVid[2];
VddNbVid[3] = PpFuseArray->VddNbVid[3];
VddNbVid[4] = PpFuseArray->VddNbVid[4];
Index = PpFuseArray->PcieGen2Vid;
}
IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 0 - %x\n", VddNbVid[0]);
IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 1 - %x\n", VddNbVid[1]);
IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 2 - %x\n", VddNbVid[2]);
IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 3 - %x\n", VddNbVid[3]);
IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 4 - %x\n", VddNbVid[4]);
IDS_HDT_CONSOLE (GNB_TRACE, " PcieGen2Vid Index - %x\n", Index);
if (LinkCap > PcieGen1) {
ASSERT (VddNbVid[Index] != 0);
TargetVid = VddNbVid[Index];
IDS_HDT_CONSOLE (GNB_TRACE, " Gen2 TargetVid - %x\n", TargetVid);
} else {
MinVidIndex = 0;
for (Index = 0; Index < 5; Index++) {
if (VddNbVid[Index] > VddNbVid[MinVidIndex]) {
MinVidIndex = (UINT8) Index;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, " MinVidIndex - %x\n", MinVidIndex);
ASSERT (VddNbVid[MinVidIndex] != 0);
TargetVid = VddNbVid[MinVidIndex];
IDS_HDT_CONSOLE (GNB_TRACE, " Gen1 TargetVid - %x\n", TargetVid);
}
IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid);
Millivolt = GnbTranslateVidCodeToMillivoltV5 (TargetVid, GnbLibGetHeader (Pcie)) * 4 / 100;
GnbRegisterWriteML (GnbGetHandle (GnbLibGetHeader (Pcie)), TYPE_SMU_MSG, SMC_MSG_VDDNB_REQUEST, &Millivolt, 0, GnbLibGetHeader (Pcie));
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageML Exit\n");
}
