void LPC1756_Timer1_Require(const T_LPC1756_Timer_Settings *aSettings)
{
static const T_LPC1756_IOCON_ConfigList pinsCAP0[] = {
{GPIO_P1_18, IOCON_D_DEFAULT(3)}, // T1_CAP0
};
static const T_LPC1756_IOCON_ConfigList pinsCAP1[] = {
{GPIO_P1_19, IOCON_D_DEFAULT(3)}, // T1_CAP1
};
static const T_LPC1756_IOCON_ConfigList pinsMAT0[] = {
{GPIO_P1_22, IOCON_D_DEFAULT(3)}, // T1_MAT0
};
static const T_LPC1756_IOCON_ConfigList pinsMAT1[] = {
{GPIO_P1_25, IOCON_D_DEFAULT(3)}, // T1_MAT1
};
HAL_DEVICE_REQUIRE_ONCE();
// Register Timer1
HALInterfaceRegister("Timer1", (T_halInterface *)&LPC1756_Timer1_Interface,
0, 0);
LPC1756_IOCON_ConfigPinOrNone(aSettings->iCAP[0], pinsCAP0,
ARRAY_COUNT(pinsCAP0));
LPC1756_IOCON_ConfigPinOrNone(aSettings->iCAP[1], pinsCAP1,
ARRAY_COUNT(pinsCAP1));
LPC1756_IOCON_ConfigPinOrNone(aSettings->iMAT[0], pinsMAT0,
ARRAY_COUNT(pinsMAT0));
LPC1756_IOCON_ConfigPinOrNone(aSettings->iMAT[1], pinsMAT1,
ARRAY_COUNT(pinsMAT1));
LPC1756_IOCON_ConfigPinOrNone(aSettings->iMAT[3], 0, 0);
}
void LPC17xx_40xx_SSP2_Require(
T_uezGPIOPortPin aPinSCK2,
T_uezGPIOPortPin aPinMISO2,
T_uezGPIOPortPin aPinMOSI2,
T_uezGPIOPortPin aPinSSEL2)
{
static const T_LPC17xx_40xx_IOCON_ConfigList sck2[] = {
{GPIO_P1_0, IOCON_D_DEFAULT(4)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList ssel2[] = {
{GPIO_P1_8, IOCON_D_DEFAULT(4)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList miso2[] = {
{GPIO_P1_4, IOCON_D_DEFAULT(4)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList mosi2[] = {
{GPIO_P1_1, IOCON_D_DEFAULT(4)},
};
HAL_DEVICE_REQUIRE_ONCE();
// Register SSP2
HALInterfaceRegister("SSP2",
(T_halInterface *)&SSP_LPC17xx_40xx_Port2_Interface, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSCK2, sck2, ARRAY_COUNT(sck2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSSEL2, ssel2, ARRAY_COUNT(ssel2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMISO2, miso2, ARRAY_COUNT(miso2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMOSI2, mosi2, ARRAY_COUNT(mosi2));
LPC17xx_40xxPowerOn(1<<20);
// Setup interrupt, but do not enable
InterruptRegister(SSP2_IRQn, ISSP2IRQ, INTERRUPT_PRIORITY_HIGH, "SSP2");
InterruptDisable(SSP2_IRQn);
}
void LPC2478_UART2_Require(
T_uezGPIOPortPin aPinTXD2,
T_uezGPIOPortPin aPinRXD2)
{
static const T_LPC2478_PINSEL_ConfigList txd2[] = {
{GPIO_P0_10, 1},
{GPIO_P2_8, 2},
{GPIO_P4_22, 2},
};
static const T_LPC2478_PINSEL_ConfigList rxd2[] = {
{GPIO_P0_11, 1},
{GPIO_P2_9, 2},
{GPIO_P4_23, 2},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART2", (T_halInterface *)&G_LPC2478_Serial_UART2, 0,
0);
LPC2478_PINSEL_ConfigPinOrNone(aPinTXD2, txd2, ARRAY_COUNT(txd2));
LPC2478_PINSEL_ConfigPinOrNone(aPinRXD2, rxd2, ARRAY_COUNT(rxd2));
// Setup clk speed for UART2 to be divide 1, not divide 4
PCLKSEL1 &= ~(3 << 16);
PCLKSEL1 |= (1 << 16);
}
/*---------------------------------------------------------------------------*
* Requirement routines:
*---------------------------------------------------------------------------*/
void LPC17xx_40xx_Timer0_Require(const T_LPC17xx_40xx_Timer_Settings *aSettings)
{
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP0[] = {
{GPIO_P1_26, IOCON_D_DEFAULT(3)}, // T0_CAP0
{GPIO_P3_23, IOCON_D_DEFAULT(3)}, // T0_CAP0
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP1[] = {
{GPIO_P1_27, IOCON_D_DEFAULT(3)}, // T0_CAP1
{GPIO_P3_24, IOCON_D_DEFAULT(3)}, // T0_CAP1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT0[] = {
{GPIO_P1_28, IOCON_D_DEFAULT(3)}, // T0_MAT0
{GPIO_P3_25, IOCON_D_DEFAULT(3)}, // T0_MAT0
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT1[] = {
{GPIO_P1_29, IOCON_D_DEFAULT(3)}, // T0_MAT1
{GPIO_P3_26, IOCON_D_DEFAULT(3)}, // T0_MAT0
};
HAL_DEVICE_REQUIRE_ONCE();
// Register Timer0
HALInterfaceRegister("Timer0", (T_halInterface *)&LPC17xx_40xx_Timer0_Interface,
0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[0], pinsCAP0,
ARRAY_COUNT(pinsCAP0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[1], pinsCAP1,
ARRAY_COUNT(pinsCAP1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[0], pinsMAT0,
ARRAY_COUNT(pinsMAT0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[1], pinsMAT1,
ARRAY_COUNT(pinsMAT1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[3], 0, 0);
}
/*---------------------------------------------------------------------------*
* Requirement routines:
*---------------------------------------------------------------------------*/
void LPC1768_I2S_Require(const T_LPC1768_I2S_Settings *aSettings)
{
static const T_LPC1768_IOCON_ConfigList pinsRX_SCK[] = {
{GPIO_P0_4, IOCON_D_DEFAULT(1)},
{GPIO_P0_23, IOCON_A_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList pinsRX_SDA[] = {
{GPIO_P0_6, IOCON_D_DEFAULT(1)},
{GPIO_P0_25, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList pinsRX_WS[] = {
{GPIO_P0_5, IOCON_D_DEFAULT(1)},
{GPIO_P0_24, IOCON_A_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList pinsRX_MCLK[] = {
{GPIO_P4_28, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList pinsTX_SCK[] = {
{GPIO_P2_11, IOCON_D_DEFAULT(3)},
{GPIO_P0_7, IOCON_W_DEFAULT(1)},
};
static const T_LPC1768_IOCON_ConfigList pinsTX_SDA[] = {
{GPIO_P2_13, IOCON_D_DEFAULT(3)},
{GPIO_P0_9, IOCON_W_DEFAULT(1)},
};
static const T_LPC1768_IOCON_ConfigList pinsTX_WS[] = {
{GPIO_P2_12, IOCON_D_DEFAULT(3)},
{GPIO_P0_8, IOCON_W_DEFAULT(1)},
};
static const T_LPC1768_IOCON_ConfigList pinsTX_MCLK[] = {
{GPIO_P4_29, IOCON_D_DEFAULT(2)},
};
HAL_DEVICE_REQUIRE_ONCE();
// Register I2S Bus drivers
HALInterfaceRegister("I2S", (T_halInterface *)&G_LPC1768_I2S_Interface, 0,
0);
LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_SCK, pinsRX_SCK,
ARRAY_COUNT(pinsRX_SCK));
LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_SDA, pinsRX_SDA,
ARRAY_COUNT(pinsRX_SDA));
LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_WS, pinsRX_WS,
ARRAY_COUNT(pinsRX_WS));
LPC1768_IOCON_ConfigPinOrNone(aSettings->iRX_MCLK, pinsRX_MCLK,
ARRAY_COUNT(pinsRX_MCLK));
LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_SCK, pinsTX_SCK,
ARRAY_COUNT(pinsTX_SCK));
LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_SDA, pinsTX_SDA,
ARRAY_COUNT(pinsTX_SDA));
LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_WS, pinsTX_WS,
ARRAY_COUNT(pinsTX_WS));
LPC1768_IOCON_ConfigPinOrNone(aSettings->iTX_MCLK, pinsTX_MCLK,
ARRAY_COUNT(pinsTX_MCLK));
}
/*---------------------------------------------------------------------------*
* Requirement routines:
*---------------------------------------------------------------------------*/
void RX62N_RTC_Require(void)
{
void *workspace;
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("RTC", (T_halInterface *)&RTC_RX62N_RTC_Interface, 0,
(T_halWorkspace **)&workspace);
RX62N_RTC_Configure(workspace);
}
void LPC17xx_40xx_USBHost_PortB_Require(const T_LPC17xx_40xx_USBHost_Settings *aSettings)
{
static const T_LPC17xx_40xx_IOCON_ConfigList pinsDP2[] = {
{GPIO_P0_31, IOCON_U_DEFAULT(1)}, // USB_D+2
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCONNECT2[] = {
{GPIO_P0_14, IOCON_D_DEFAULT(3)}, // USB_CONNECT2
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsUP_LED2[] = {
{GPIO_P0_13, IOCON_A_DEFAULT(1)}, // USB_UP_LED2
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsPPWR2[] = {
{GPIO_P0_12, IOCON_A_DEFAULT(1)}, // USB_PPWR2n
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsPWRD2[] = {
{GPIO_P1_30, IOCON_A_DEFAULT(1)}, // USB_PWRD2
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsOVRCR2[] = {
{GPIO_P1_31, IOCON_A_DEFAULT(1)}, // USB_OVRCR2n
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsHSTEN2[] = {
{GPIO_P0_14, IOCON_D_DEFAULT(1)}, // USB_HSTEN2n
};
HAL_DEVICE_REQUIRE_ONCE();
// Register USB Host driver ports for LPC24xx
HALInterfaceRegister("USBHost:PortB",
(T_halInterface *)&G_LPC17xx_40xx_USBHost_Interface_PortB, 0, 0);
// LPC17xx_40xx_USBHost_VBUS_Require(aSettings->iVBUS);
LPC17xx_40xx_IOCON_ConfigPin(aSettings->iDP, pinsDP2, ARRAY_COUNT(pinsDP2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iDM, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCONNECT, pinsCONNECT2,
ARRAY_COUNT(pinsCONNECT2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iUP_LED, pinsUP_LED2,
ARRAY_COUNT(pinsUP_LED2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iINTn, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iSCL, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iSDA, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iTX_E, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iTX_DP, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iTX_DM, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iRCV, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iRX_DP, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iRX_DM, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iLSn, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iSSPNDn, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iPPWRn, pinsPPWR2,
ARRAY_COUNT(pinsPPWR2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iPWRDn, pinsPWRD2,
ARRAY_COUNT(pinsPWRD2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iOVRCRn, pinsOVRCR2,
ARRAY_COUNT(pinsOVRCR2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iHSTENn, pinsHSTEN2,
ARRAY_COUNT(pinsHSTEN2));
}
void LPC1768_UART1_Require(
T_uezGPIOPortPin aPinTXD1,
T_uezGPIOPortPin aPinRXD1,
T_uezGPIOPortPin aPinCTS,
T_uezGPIOPortPin aPinDCD,
T_uezGPIOPortPin aPinDSR,
T_uezGPIOPortPin aPinDTR,
T_uezGPIOPortPin aPinRI,
T_uezGPIOPortPin aPinRTS)
{
static const T_LPC1768_IOCON_ConfigList txd1[] = {
{GPIO_P0_15, IOCON_D_DEFAULT(1)},
{GPIO_P2_0, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList rxd1[] = {
{GPIO_P0_16, IOCON_D_DEFAULT(1)},
{GPIO_P2_1, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList cts[] = {
{GPIO_P0_17, IOCON_D_DEFAULT(1)},
{GPIO_P2_2, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList dcd[] = {
{GPIO_P0_18, IOCON_D_DEFAULT(1)},
{GPIO_P2_3, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList dsr[] = {
{GPIO_P0_19, IOCON_D_DEFAULT(1)},
{GPIO_P2_4, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList dtr[] = {
{GPIO_P0_20, IOCON_D_DEFAULT(1)},
{GPIO_P2_5, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList ri[] = {
{GPIO_P0_21, IOCON_D_DEFAULT(1)},
{GPIO_P2_6, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList rts[] = {
{GPIO_P0_22, IOCON_D_DEFAULT(1)},
{GPIO_P2_7, IOCON_D_DEFAULT(2)},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART1", (T_halInterface *)&G_LPC1768_Serial_UART1, 0,
0);
LPC1768_IOCON_ConfigPinOrNone(aPinTXD1, txd1, ARRAY_COUNT(txd1));
LPC1768_IOCON_ConfigPinOrNone(aPinRXD1, rxd1, ARRAY_COUNT(rxd1));
LPC1768_IOCON_ConfigPinOrNone(aPinCTS, cts, ARRAY_COUNT(cts));
LPC1768_IOCON_ConfigPinOrNone(aPinDCD, dcd, ARRAY_COUNT(dcd));
LPC1768_IOCON_ConfigPinOrNone(aPinDSR, dsr, ARRAY_COUNT(dsr));
LPC1768_IOCON_ConfigPinOrNone(aPinDTR, dtr, ARRAY_COUNT(dtr));
LPC1768_IOCON_ConfigPinOrNone(aPinRI, ri, ARRAY_COUNT(ri));
LPC1768_IOCON_ConfigPinOrNone(aPinRTS, rts, ARRAY_COUNT(rts));
}
void RX63N_DirectDrive_LCDController_Require(T_uezGPIOPortPin *pins)
{
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister(
"LCDController",
(T_halInterface *)&LCDController_RX63N_DirectDrive_Interface,
0,
0);
RX63N_PinsLock(pins, ARRAY_COUNT(pins));
}
void LPC17xx_40xx_Timer2_Require(const T_LPC17xx_40xx_Timer_Settings *aSettings)
{
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP0[] = {
{GPIO_P0_4, IOCON_D_DEFAULT(3)}, // T2_CAP0
{GPIO_P1_14, IOCON_D_DEFAULT(3)}, // T2_CAP0
{GPIO_P2_6, IOCON_D_DEFAULT(3)}, // T2_CAP0
{GPIO_P2_14, IOCON_D_DEFAULT(3)}, // T2_CAP0
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP1[] = {
{GPIO_P0_5, IOCON_D_DEFAULT(3)}, // T2_CAP1
{GPIO_P2_15, IOCON_D_DEFAULT(3)}, // T2_CAP1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT0[] = {
{GPIO_P0_6, IOCON_D_DEFAULT(3)}, // T2_MAT0
{GPIO_P2_5, IOCON_D_DEFAULT(3)}, // T2_MAT0
{GPIO_P4_28, IOCON_D_DEFAULT(3)}, // T2_MAT0
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT1[] = {
{GPIO_P0_7, IOCON_W_DEFAULT(3)}, // T2_MAT1
{GPIO_P2_4, IOCON_D_DEFAULT(3)}, // T2_MAT1
{GPIO_P4_29, IOCON_D_DEFAULT(3)}, // T2_MAT1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT2[] = {
{GPIO_P0_8, IOCON_W_DEFAULT(3)}, // T2_MAT2
{GPIO_P2_3, IOCON_D_DEFAULT(3)}, // T2_MAT2
{GPIO_P5_0, IOCON_D_DEFAULT(3)}, // T2_MAT2
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT3[] = {
{GPIO_P0_9, IOCON_W_DEFAULT(3)}, // T2_MAT3
{GPIO_P2_2, IOCON_D_DEFAULT(3)}, // T2_MAT3
{GPIO_P5_1, IOCON_D_DEFAULT(3)}, // T2_MAT3
};
HAL_DEVICE_REQUIRE_ONCE();
// Register Timer2
HALInterfaceRegister("Timer2", (T_halInterface *)&LPC17xx_40xx_Timer2_Interface,
0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[0], pinsCAP0,
ARRAY_COUNT(pinsCAP0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[1], pinsCAP1,
ARRAY_COUNT(pinsCAP1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[0], pinsMAT0,
ARRAY_COUNT(pinsMAT0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[1], pinsMAT1,
ARRAY_COUNT(pinsMAT1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT2,
ARRAY_COUNT(pinsMAT2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT3,
ARRAY_COUNT(pinsMAT3));
}
void LPC17xx_40xx_Timer3_Require(const T_LPC17xx_40xx_Timer_Settings *aSettings)
{
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP0[] = {
{GPIO_P1_10, IOCON_D_DEFAULT(3)}, // T3_CAP0
{GPIO_P2_22, IOCON_D_DEFAULT(3)}, // T3_CAP0
{GPIO_P0_23, IOCON_W_DEFAULT(3)}, // T3_CAP0
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCAP1[] = {
{GPIO_P1_0, IOCON_D_DEFAULT(3)}, // T3_CAP1
{GPIO_P2_23, IOCON_D_DEFAULT(3)}, // T3_CAP1
{GPIO_P0_24, IOCON_W_DEFAULT(3)}, // T3_CAP1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT0[] = {
{GPIO_P0_10, IOCON_D_DEFAULT(3)}, // T3_MAT0
{GPIO_P1_9, IOCON_D_DEFAULT(3)}, // T3_MAT0
{GPIO_P2_26, IOCON_D_DEFAULT(3)}, // T3_MAT0
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT1[] = {
{GPIO_P0_11, IOCON_D_DEFAULT(3)}, // T3_MAT1
{GPIO_P1_8, IOCON_D_DEFAULT(3)}, // T3_MAT1
{GPIO_P2_27, IOCON_D_DEFAULT(3)}, // T3_MAT1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT2[] = {
{GPIO_P1_4, IOCON_D_DEFAULT(3)}, // T3_MAT2
{GPIO_P2_30, IOCON_D_DEFAULT(3)}, // T3_MAT2
{GPIO_P5_2, IOCON_I_DEFAULT(3)}, // T3_MAT2
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsMAT3[] = {
{GPIO_P1_1, IOCON_D_DEFAULT(3)}, // T3_MAT3
{GPIO_P2_31, IOCON_D_DEFAULT(3)}, // T3_MAT3
{GPIO_P5_4, IOCON_D_DEFAULT(3)}, // T3_MAT3
};
HAL_DEVICE_REQUIRE_ONCE();
// Register Timer3
HALInterfaceRegister("Timer3", (T_halInterface *)&LPC17xx_40xx_Timer3_Interface,
0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[0], pinsCAP0,
ARRAY_COUNT(pinsCAP0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCAP[1], pinsCAP1,
ARRAY_COUNT(pinsCAP1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[0], pinsMAT0,
ARRAY_COUNT(pinsMAT0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[1], pinsMAT1,
ARRAY_COUNT(pinsMAT1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT2,
ARRAY_COUNT(pinsMAT2));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iMAT[2], pinsMAT3,
ARRAY_COUNT(pinsMAT3));
}
/*---------------------------------------------------------------------------*
* Requirement routines:
*---------------------------------------------------------------------------*/
void LPC1768_UART0_Require(
T_uezGPIOPortPin aPinTXD0,
T_uezGPIOPortPin aPinRXD0)
{
static const T_LPC1768_IOCON_ConfigList txd0[] = {
{GPIO_P0_2, IOCON_D_DEFAULT(1)},
};
static const T_LPC1768_IOCON_ConfigList rxd0[] = {
{GPIO_P0_3, IOCON_D_DEFAULT(1)},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART0", (T_halInterface *)&G_LPC1768_Serial_UART0, 0,
0);
LPC1768_IOCON_ConfigPinOrNone(aPinTXD0, txd0, ARRAY_COUNT(txd0));
LPC1768_IOCON_ConfigPinOrNone(aPinRXD0, rxd0, ARRAY_COUNT(rxd0));
}
void LPC17xx_40xx_SSP1_Require(
T_uezGPIOPortPin aPinSCK1,
T_uezGPIOPortPin aPinMISO1,
T_uezGPIOPortPin aPinMOSI1,
T_uezGPIOPortPin aPinSSEL1)
{
static const T_LPC17xx_40xx_IOCON_ConfigList sck1[] = {
{GPIO_P0_7, IOCON_W_DEFAULT(2)},
{GPIO_P1_19, IOCON_D_DEFAULT(5)},
{GPIO_P1_31, IOCON_A_DEFAULT(2)},
{GPIO_P4_20, IOCON_D_DEFAULT(3)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList ssel1[] = {
{GPIO_P0_6, IOCON_D_DEFAULT(2)},
{GPIO_P0_14, IOCON_D_DEFAULT(2)},
{GPIO_P4_21, IOCON_D_DEFAULT(3)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList miso1[] = {
{GPIO_P0_8, IOCON_W_DEFAULT(2)},
{GPIO_P0_12, IOCON_A_DEFAULT(2)},
{GPIO_P1_18, IOCON_D_DEFAULT(5)},
{GPIO_P4_22, IOCON_D_DEFAULT(3)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList mosi1[] = {
{GPIO_P0_9, IOCON_W_DEFAULT(2)},
{GPIO_P0_13, IOCON_A_DEFAULT(2)},
{GPIO_P1_22, IOCON_D_DEFAULT(5)},
{GPIO_P4_23, IOCON_D_DEFAULT(3)},
};
HAL_DEVICE_REQUIRE_ONCE();
// Register SSP1
HALInterfaceRegister("SSP1",
(T_halInterface *)&SSP_LPC17xx_40xx_Port1_Interface, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSCK1, sck1, ARRAY_COUNT(sck1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSSEL1, ssel1, ARRAY_COUNT(ssel1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMISO1, miso1, ARRAY_COUNT(miso1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMOSI1, mosi1, ARRAY_COUNT(mosi1));
LPC17xx_40xxPowerOn(1<<10);
// Setup interrupt, but do not enable
InterruptRegister(SSP1_IRQn, ISSP1IRQ, INTERRUPT_PRIORITY_HIGH, "SSP1");
InterruptDisable(SSP1_IRQn);
}
void LPC17xx_40xx_UART4_Require(
T_uezGPIOPortPin aPinTXD4,
T_uezGPIOPortPin aPinRXD4)
{
static const T_LPC17xx_40xx_IOCON_ConfigList txd4[] = {
{GPIO_P0_22, IOCON_D_DEFAULT(3)},
{GPIO_P1_29, IOCON_D_DEFAULT(5)},
{GPIO_P5_4, IOCON_A_DEFAULT(4)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList rxd4[] = {
{GPIO_P2_9, IOCON_D_DEFAULT(3)},
{GPIO_P5_3, IOCON_D_DEFAULT(4)},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART4", (T_halInterface *)&G_LPC17xx_40xx_Serial_UART4, 0,
0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinTXD4, txd4, ARRAY_COUNT(txd4));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinRXD4, rxd4, ARRAY_COUNT(rxd4));
}
void LPC1768_UART2_Require(
T_uezGPIOPortPin aPinTXD2,
T_uezGPIOPortPin aPinRXD2)
{
static const T_LPC1768_IOCON_ConfigList txd2[] = {
{GPIO_P0_10, IOCON_D_DEFAULT(1)},
{GPIO_P2_8, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList rxd2[] = {
{GPIO_P0_11, IOCON_D_DEFAULT(1)},
{GPIO_P2_9, IOCON_D_DEFAULT(2)},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART2", (T_halInterface *)&G_LPC1768_Serial_UART2, 0,
0);
LPC1768_IOCON_ConfigPinOrNone(aPinTXD2, txd2, ARRAY_COUNT(txd2));
LPC1768_IOCON_ConfigPinOrNone(aPinRXD2, rxd2, ARRAY_COUNT(rxd2));
}
/*---------------------------------------------------------------------------*
* Requirement routines:
*---------------------------------------------------------------------------*/
void LPC17xx_40xx_SSP0_Require(
T_uezGPIOPortPin aPinSCK0,
T_uezGPIOPortPin aPinMISO0,
T_uezGPIOPortPin aPinMOSI0,
T_uezGPIOPortPin aPinSSEL0)
{
static const T_LPC17xx_40xx_IOCON_ConfigList sck0[] = {
{GPIO_P0_15, IOCON_D_DEFAULT(2)},
{GPIO_P1_20, IOCON_D_DEFAULT(5)},
{GPIO_P2_22, IOCON_D_DEFAULT(2)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList ssel0[] = {
{GPIO_P0_16, IOCON_D_DEFAULT(2)},
{GPIO_P1_21, IOCON_D_DEFAULT(3)},
{GPIO_P1_28, IOCON_D_DEFAULT(5)},
{GPIO_P2_23, IOCON_D_DEFAULT(2)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList miso0[] = {
{GPIO_P0_17, IOCON_D_DEFAULT(2)},
{GPIO_P1_23, IOCON_D_DEFAULT(5)},
{GPIO_P2_26, IOCON_D_DEFAULT(2)},
};
static const T_LPC17xx_40xx_IOCON_ConfigList mosi0[] = {
{GPIO_P0_18, IOCON_D_DEFAULT(2)},
{GPIO_P1_24, IOCON_D_DEFAULT(5)},
{GPIO_P2_27, IOCON_D_DEFAULT(2)},
};
HAL_DEVICE_REQUIRE_ONCE();
// Register SSP0
HALInterfaceRegister("SSP0",
(T_halInterface *)&SSP_LPC17xx_40xx_Port0_Interface, 0, 0);
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSCK0, sck0, ARRAY_COUNT(sck0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinSSEL0, ssel0, ARRAY_COUNT(ssel0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMISO0, miso0, ARRAY_COUNT(miso0));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aPinMOSI0, mosi0, ARRAY_COUNT(mosi0));
LPC17xx_40xxPowerOn(1<<21);
// Setup interrupt, but do not enable
InterruptRegister(SSP0_IRQn, ISSP0IRQ, INTERRUPT_PRIORITY_HIGH, "SSP0");
InterruptDisable(SSP0_IRQn);
}
void LPC1768_UART3_Require(
T_uezGPIOPortPin aPinTXD3,
T_uezGPIOPortPin aPinRXD3)
{
static const T_LPC1768_IOCON_ConfigList txd3[] = {
{GPIO_P0_0, IOCON_D_DEFAULT(2)},
{GPIO_P0_25, IOCON_A_DEFAULT(3)},
{GPIO_P4_28, IOCON_D_DEFAULT(2)},
};
static const T_LPC1768_IOCON_ConfigList rxd3[] = {
{GPIO_P0_1, IOCON_D_DEFAULT(2)},
{GPIO_P0_26, IOCON_A_DEFAULT(3)},
{GPIO_P4_29, IOCON_D_DEFAULT(2)},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART3", (T_halInterface *)&G_LPC1768_Serial_UART3, 0,
0);
LPC1768_IOCON_ConfigPinOrNone(aPinTXD3, txd3, ARRAY_COUNT(txd3));
LPC1768_IOCON_ConfigPinOrNone(aPinRXD3, rxd3, ARRAY_COUNT(rxd3));
}
/*---------------------------------------------------------------------------*
* Requirement routines:
*---------------------------------------------------------------------------*/
void LPC2478_UART0_Require(
T_uezGPIOPortPin aPinTXD0,
T_uezGPIOPortPin aPinRXD0)
{
static const T_LPC2478_PINSEL_ConfigList txd0[] = {
{GPIO_P0_2, 1},
};
static const T_LPC2478_PINSEL_ConfigList rxd0[] = {
{GPIO_P0_3, 1},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART0", (T_halInterface *)&G_LPC2478_Serial_UART0, 0,
0);
LPC2478_PINSEL_ConfigPinOrNone(aPinTXD0, txd0, ARRAY_COUNT(txd0));
LPC2478_PINSEL_ConfigPinOrNone(aPinRXD0, rxd0, ARRAY_COUNT(rxd0));
// Setup clk speed for UART0 to be divide 1, not divide 4
PCLKSEL0 &= ~(3 << 6);
PCLKSEL0 |= (1 << 6);
}
void RX63N_S12AD_Require(TUInt32 channelMask)
{
TUInt8 i;
static const T_uezGPIOPortPin pins[] = {
GPIO_P40, // AN000
GPIO_P41, // AN001
GPIO_P42, // AN002
GPIO_P43, // AN003
GPIO_P44, // AN004
GPIO_P45, // AN005
GPIO_P46, // AN006
GPIO_P47, // AN007
GPIO_PD0, // AN008
GPIO_PD1, // AN009
GPIO_PD2, // AN010
GPIO_PD3, // AN011
GPIO_PD4, // AN012
GPIO_PD5, // AN013
GPIO_P90, // AN014
GPIO_P91, // AN015
GPIO_P92, // AN016
GPIO_P93, // AN017
GPIO_P00, // AN018
GPIO_P01, // AN019
GPIO_P02, // AN020
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("ADC_S12AD", (T_halInterface *)&RX63N_ADC_S12AD_Interface,
0, 0);
for(i=0; i<21; i++) {
if(channelMask & (1<<i)) {
*G_ADC_PFS[i] = 1; // Set ADC i to Analog Input
UEZGPIOLock(pins[i]);
}
}
}
void LPC2478_UART3_Require(
T_uezGPIOPortPin aPinTXD3,
T_uezGPIOPortPin aPinRXD3)
{
static const T_LPC2478_PINSEL_ConfigList txd3[] = {
{GPIO_P0_0, 2},
{GPIO_P0_25, 3},
{GPIO_P4_28, 3},
};
static const T_LPC2478_PINSEL_ConfigList rxd3[] = {
{GPIO_P0_1, 2},
{GPIO_P0_26, 3},
{GPIO_P4_29, 3},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART3", (T_halInterface *)&G_LPC2478_Serial_UART3, 0,
0);
LPC2478_PINSEL_ConfigPinOrNone(aPinTXD3, txd3, ARRAY_COUNT(txd3));
LPC2478_PINSEL_ConfigPinOrNone(aPinRXD3, rxd3, ARRAY_COUNT(rxd3));
// Setup clk speed for UART3 to be divide 1, not divide 4
PCLKSEL1 &= ~(3 << 18);
PCLKSEL1 |= (1 << 18);
}
/*---------------------------------------------------------------------------*
* Requirement routines:
*---------------------------------------------------------------------------*/
void LPC1756_BatteryRAM_Require(void)
{
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("BatteryRAM",
(T_halInterface *)&LPC1756_BatteryRAM_Interface, 0, 0);
}
void LPC2478_UART1_Require(
T_uezGPIOPortPin aPinTXD1,
T_uezGPIOPortPin aPinRXD1,
T_uezGPIOPortPin aPinCTS,
T_uezGPIOPortPin aPinDCD,
T_uezGPIOPortPin aPinDSR,
T_uezGPIOPortPin aPinDTR,
T_uezGPIOPortPin aPinRI,
T_uezGPIOPortPin aPinRTS)
{
static const T_LPC2478_PINSEL_ConfigList txd1[] = {
{GPIO_P0_15, 1},
{GPIO_P2_0, 2},
{GPIO_P3_16, 3},
};
static const T_LPC2478_PINSEL_ConfigList rxd1[] = {
{GPIO_P0_16, 1},
{GPIO_P2_1, 2},
{GPIO_P3_17, 3},
};
static const T_LPC2478_PINSEL_ConfigList cts[] = {
{GPIO_P0_17, 1},
{GPIO_P2_2, 2},
{GPIO_P3_18, 3},
};
static const T_LPC2478_PINSEL_ConfigList dcd[] = {
{GPIO_P0_18, 1},
{GPIO_P2_3, 2},
{GPIO_P3_19, 3},
};
static const T_LPC2478_PINSEL_ConfigList dsr[] = {
{GPIO_P0_19, 1},
{GPIO_P2_4, 2},
{GPIO_P3_20, 3},
};
static const T_LPC2478_PINSEL_ConfigList dtr[] = {
{GPIO_P0_20, 1},
{GPIO_P2_5, 2},
{GPIO_P3_21, 3},
};
static const T_LPC2478_PINSEL_ConfigList ri[] = {
{GPIO_P0_21, 1},
{GPIO_P2_6, 2},
{GPIO_P3_22, 3},
};
static const T_LPC2478_PINSEL_ConfigList rts[] = {
{GPIO_P0_22, 1},
{GPIO_P2_7, 2},
{GPIO_P3_30, 3},
};
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("UART1", (T_halInterface *)&G_LPC2478_Serial_UART1, 0,
0);
LPC2478_PINSEL_ConfigPinOrNone(aPinTXD1, txd1, ARRAY_COUNT(txd1));
LPC2478_PINSEL_ConfigPinOrNone(aPinRXD1, rxd1, ARRAY_COUNT(rxd1));
LPC2478_PINSEL_ConfigPinOrNone(aPinCTS, cts, ARRAY_COUNT(cts));
LPC2478_PINSEL_ConfigPinOrNone(aPinDCD, dcd, ARRAY_COUNT(dcd));
LPC2478_PINSEL_ConfigPinOrNone(aPinDSR, dsr, ARRAY_COUNT(dsr));
LPC2478_PINSEL_ConfigPinOrNone(aPinDTR, dtr, ARRAY_COUNT(dtr));
LPC2478_PINSEL_ConfigPinOrNone(aPinRI, ri, ARRAY_COUNT(ri));
LPC2478_PINSEL_ConfigPinOrNone(aPinRTS, rts, ARRAY_COUNT(rts));
// Setup clk speed for UART1 to be divide 1, not divide 4
PCLKSEL0 &= ~(3 << 8);
PCLKSEL0 |= (1 << 8);
}
void RX62N_ExternalInterrupts_Require(void)
{
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("EINT", (T_halInterface *)&ExternalInterrupt_Renesas_RX62N_Interface, 0, 0);
}
void RX62N_PWM_MTU10_Require(void)
{
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("PWM_MTU10", (T_halInterface *)&PWM_RX62N_MTU10_Interface, 0, 0);
}
void LPC1756_GPDMA7_Require(void)
{
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("GPDMA7",
(T_halInterface *)&LPC1756_GPDMA_Channel7_Interface, 0, 0);
}
//void LPC17xx_40xx_USBHost_VBUS_Require(T_uezGPIOPortPin aPin)
//{
// static const T_LPC17xx_40xx_IOCON_ConfigList pins[] = {
// {GPIO_P1_30, IOCON_A_DEFAULT(2)}, // USB_VBUS
// };
// HAL_DEVICE_REQUIRE_ONCE();
// LPC17xx_40xx_IOCON_ConfigPinOrNone(aPin, pins, ARRAY_COUNT(pins));
//
//}
void LPC17xx_40xx_USBHost_PortA_Require(const T_LPC17xx_40xx_USBHost_Settings *aSettings)
{
static const T_LPC17xx_40xx_IOCON_ConfigList pinsDP1[] = {
{GPIO_P0_29, IOCON_U_DEFAULT(1)}, // USB_D+1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsDM1[] = {
{GPIO_P0_30, IOCON_U_DEFAULT(1)}, // USB_D-1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsCONNECT1[] = {
{GPIO_P2_9, IOCON_D_DEFAULT(1)}, // USB_CONNECT1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsUP_LED1[] = {
{GPIO_P1_18, IOCON_D_DEFAULT(1)}, // USB_UP_LED1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsINT1[] = {
{GPIO_P1_27, IOCON_D_DEFAULT(1)}, // USB_INT1n
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsSCL1[] = {
{GPIO_P1_28, IOCON_D_DEFAULT(1)}, // USB_SCL1
{GPIO_P0_28, IOCON_I_DEFAULT(2)}, // USB_SCL1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsSDA1[] = {
{GPIO_P1_29, IOCON_D_DEFAULT(1)}, // USB_SDA1
{GPIO_P0_27, IOCON_I_DEFAULT(2)}, // USB_SDA1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsTX_E1[] = {
{GPIO_P1_19, IOCON_D_DEFAULT(1)}, // USB_TX_E1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsTX_DP1[] = {
{GPIO_P1_20, IOCON_D_DEFAULT(1)}, // USB_TX_DP1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsTX_DM1[] = {
{GPIO_P1_21, IOCON_D_DEFAULT(1)}, // USB_TX_DM1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsRCV1[] = {
{GPIO_P1_22, IOCON_D_DEFAULT(1)}, // USB_RCV1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsRX_DP1[] = {
{GPIO_P1_23, IOCON_D_DEFAULT(1)}, // USB_RX_DP1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsRX_DM1[] = {
{GPIO_P1_24, IOCON_D_DEFAULT(1)}, // USB_RX_DM1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsRX_LS1[] = {
{GPIO_P1_25, IOCON_D_DEFAULT(1)}, // USB_LS1n
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsSSPND1[] = {
{GPIO_P1_26, IOCON_D_DEFAULT(1)}, // USB_SSPND1n
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsPPWR1[] = {
{GPIO_P1_19, IOCON_D_DEFAULT(2)}, // USB_PPWR1n
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsPWRD1[] = {
{GPIO_P1_22, IOCON_D_DEFAULT(2)}, // USB_PWRD1
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsOVRCR1[] = {
{GPIO_P1_22, IOCON_D_DEFAULT(2)}, // USB_OVRCR1n
{GPIO_P1_27, IOCON_D_DEFAULT(2)}, // USB_OVRCR1n
};
static const T_LPC17xx_40xx_IOCON_ConfigList pinsHSTEN1[] = {
{GPIO_P1_25, IOCON_D_DEFAULT(2)}, // USB_HSTEN1n
};
HAL_DEVICE_REQUIRE_ONCE();
// Register USB Host driver ports for LPC24xx
HALInterfaceRegister("USBHost:PortA",
(T_halInterface *)&G_LPC17xx_40xx_USBHost_Interface_PortA, 0, 0);
// LPC17xx_40xx_USBHost_VBUS_Require(aSettings->iVBUS);
LPC17xx_40xx_IOCON_ConfigPin(aSettings->iDP, pinsDP1, ARRAY_COUNT(pinsDP1));
LPC17xx_40xx_IOCON_ConfigPin(aSettings->iDM, pinsDM1, ARRAY_COUNT(pinsDM1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iCONNECT, pinsCONNECT1,
ARRAY_COUNT(pinsCONNECT1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iUP_LED, pinsUP_LED1,
ARRAY_COUNT(pinsUP_LED1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iINTn, pinsINT1,
ARRAY_COUNT(pinsINT1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iSCL, pinsSCL1,
ARRAY_COUNT(pinsSCL1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iSDA, pinsSDA1,
ARRAY_COUNT(pinsSDA1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iTX_E, pinsTX_E1,
ARRAY_COUNT(pinsTX_E1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iTX_DP, pinsTX_DP1,
ARRAY_COUNT(pinsTX_DP1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iTX_DM, pinsTX_DM1,
ARRAY_COUNT(pinsTX_DM1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iRCV, pinsRCV1,
ARRAY_COUNT(pinsRCV1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iRX_DP, pinsRX_DP1,
ARRAY_COUNT(pinsRX_DP1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iRX_DM, pinsRX_DM1,
ARRAY_COUNT(pinsRX_DM1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iLSn, pinsRX_LS1,
ARRAY_COUNT(pinsRX_LS1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iSSPNDn, pinsSSPND1,
ARRAY_COUNT(pinsSSPND1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iPPWRn, pinsPPWR1,
ARRAY_COUNT(pinsPPWR1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iPWRDn, pinsPWRD1,
ARRAY_COUNT(pinsPWRD1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iOVRCRn, pinsOVRCR1,
ARRAY_COUNT(pinsOVRCR1));
LPC17xx_40xx_IOCON_ConfigPinOrNone(aSettings->iHSTENn, pinsHSTEN1,
ARRAY_COUNT(pinsHSTEN1));
}
void LPC2478_GPDMA1_Require(void)
{
HAL_DEVICE_REQUIRE_ONCE();
HALInterfaceRegister("GPDMA1",
(T_halInterface *)&LPC2478_GPDMA_Channel1_Interface, 0, 0);
}
