// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
mpc8xxx_scc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
mpc8xxx_sxx_serial_info *scc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
volatile struct scc_regs_8260 *regs = (volatile struct scc_regs_8260*)scc_chan->ctl;
if (baud_divisor == 0) return false;
// Set baud rate generator
*scc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Disable channel during setup
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->gsmr_l = 0;
regs->psmr = MPC8XXX_SCC_PSMR_ASYNC |
scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
scc_select_stop_bits[new_config->stop] |
scc_select_parity[new_config->parity];
// Enable channel with new configuration
regs->gsmr_h = 0x20; // 8bit FIFO
regs->gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART
/*
* Init Rx & Tx params for SCCX
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS | scc_chan->channel | CPCR_FLG;
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR; // Enable Rx, Tx
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
mpc8xxx_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
cyg_uint32 _lcr;
volatile struct smc_regs_8260 *ctl = (volatile struct smc_regs_8260*)smc_chan->ctl;
if (baud_divisor == 0) return false;
// Disable channel during setup
ctl->smc_smcmr = MPC8XXX_SMCMR_UART; // Disabled, UART mode
HAL_IO_BARRIER(); // Inforce I/O ordering
// Disable port interrupts while changing hardware
_lcr = smc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
smc_select_stop_bits[new_config->stop] |
smc_select_parity[new_config->parity];
// Stop transmitter while changing baud rate
IMM->cpm_cpcr = smc_chan->channel | CPCR_STOP_TX | CPCR_FLG;
HAL_IO_BARRIER(); // Inforce I/O ordering
// Set baud rate generator
*smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Enable channel with new configuration
ctl->smc_smcmr = MPC8XXX_SMCMR_UART|MPC8XXX_SMCMR_TEN|MPC8XXX_SMCMR_REN|_lcr;
HAL_IO_BARRIER(); // Inforce I/O ordering
IMM->cpm_cpcr = smc_chan->channel | CPCR_INIT_TX_RX_PARAMS | CPCR_FLG;
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
quicc_scc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
quicc_sxx_serial_info *scc_chan = (quicc_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
EPPC *eppc = eppc_base();
volatile struct scc_regs *regs = (volatile struct scc_regs *)scc_chan->ctl;
if (baud_divisor == 0) return false;
// Set baud rate generator
*scc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Disable channel during setup
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->scc_gsmr_l = 0;
regs->scc_psmr = QUICC_SCC_PSMR_ASYNC |
scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
scc_select_stop_bits[new_config->stop] |
scc_select_parity[new_config->parity];
// Enable channel with new configuration
regs->scc_gsmr_h = 0x20; // 8bit FIFO
regs->scc_gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART
/*
* Init Rx & Tx params for SCCX
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY;
while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
continue;
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx); // Enable Rx, Tx
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
quicc_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
cyg_uint32 _lcr;
EPPC *eppc = eppc_base();
volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl;
if (baud_divisor == 0) return false;
// Stop transmitter while changing baud rate
eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
while (eppc->cp_cr & QUICC_SMC_CMD_Go )
continue;
HAL_IO_BARRIER(); // Inforce I/O ordering
// Disable channel during setup
ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
HAL_IO_BARRIER(); // Inforce I/O ordering
// Disable port interrupts while changing hardware
_lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
smc_select_stop_bits[new_config->stop] |
smc_select_parity[new_config->parity];
HAL_IO_BARRIER(); // Inforce I/O ordering
// Set baud rate generator
*smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Enable channel with new configuration
ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr;
HAL_IO_BARRIER(); // Inforce I/O ordering
eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx;
while (eppc->cp_cr & QUICC_SMC_CMD_Go )
continue;
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
// Function to set up internal tables for device.
static void
mpc8xxx_scc_serial_init_info(mpc8xxx_sxx_serial_info *scc_chan,
volatile t_Scc_Pram *uart_pram,
volatile struct scc_regs_8260 *ctl,
unsigned long *brg,
int TxBD, int TxNUM, int TxSIZE,
cyg_uint8 *TxBUF,
int RxBD, int RxNUM, int RxSIZE,
cyg_uint8 *RxBUF)
{
struct cp_bufdesc *txbd, *rxbd;
int i;
// Disable channel during setup
ctl->gsmr_l = 0;
scc_chan->pram = (void *)uart_pram;
scc_chan->ctl = (void *)ctl;
// Set up baud rate generator
scc_chan->brg = brg;
/*
* Set Rx and Tx function code
* (Section 16.15.4.2)
*/
uart_pram->rfcr = 0x18;
uart_pram->tfcr = 0x18;
/*
* Set pointers to buffer descriptors.
* (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
*/
uart_pram->rbase = RxBD;
uart_pram->tbase = TxBD;
/* tx and rx buffer descriptors */
txbd = (struct cp_bufdesc *)((char *)IMM + TxBD);
rxbd = (struct cp_bufdesc *)((char *)IMM + RxBD);
scc_chan->txbd = txbd;
scc_chan->tbase = txbd;
scc_chan->txsize = TxSIZE;
scc_chan->rxbd = rxbd;
scc_chan->rbase = rxbd;
scc_chan->rxsize = RxSIZE;
/* max receive buffer length */
uart_pram->mrblr = RxSIZE;
/* set max_idle feature - generate interrupt after 4 chars idle period */
uart_pram->SpecificProtocol.u.max_idl = 4;
/* no last brk char received */
uart_pram->SpecificProtocol.u.brkln = 0;
/* no break condition occurred */
uart_pram->SpecificProtocol.u.brkec = 0;
/* 1 break char sent on top XMIT */
uart_pram->SpecificProtocol.u.brkcr = 1;
/* character mask */
uart_pram->SpecificProtocol.u.rccm = 0xC0FF;
/* control characters */
for (i = 0; i < 8; i++) {
uart_pram->SpecificProtocol.u.cc[i] = 0x8000; // Mark unused
}
/* setup RX buffer descriptors */
for (i = 0; i < RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = _BD_CTL_Ready | _BD_CTL_Int;
if (i == (RxNUM-1)) rxbd->ctrl |= _BD_CTL_Wrap; // Last buffer
RxBUF += RxSIZE;
rxbd++;
}
/* setup TX buffer descriptors */
for (i = 0; i < TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
if (i == (TxNUM-1)) txbd->ctrl |= _BD_CTL_Wrap; // Last buffer
TxBUF += TxSIZE;
txbd++;
}
/*
* Reset Rx & Tx params
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
IMM->cpm_cpcr = scc_chan->channel | CPCR_INIT_TX_RX_PARAMS | CPCR_FLG;
/*
* Clear any previous events. Enable interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
ctl->scce = 0xFFFF;
ctl->sccm = (SCCE_Bsy | SCCE_Tx | SCCE_Rx);
}
// Function to set up internal tables for device.
static void
mpc8xxx_smc_serial_init_info(mpc8xxx_sxx_serial_info *smc_chan,
t_Smc_Pram *uart_pram,
volatile struct smc_regs_8260 *ctl,
unsigned long *brg,
int TxBD, int TxNUM, int TxSIZE,
cyg_uint8 *TxBUF,
int RxBD, int RxNUM, int RxSIZE,
cyg_uint8 *RxBUF)
{
struct cp_bufdesc *txbd, *rxbd;
int i;
smc_chan->pram = (void *)uart_pram;
smc_chan->ctl = (void *)ctl;
// Set up baud rate generator
smc_chan->brg = (void *)brg;
// Disable channel during setup
ctl->smc_smcmr = MPC8XXX_SMCMR_UART; // Disabled, UART mode
// Rx, Tx function codes (used for access)
uart_pram->rfcr = 0x18;
uart_pram->tfcr = 0x18;
// Pointers to Rx & Tx buffer descriptor rings
uart_pram->rbase = RxBD;
uart_pram->tbase = TxBD;
/* tx and rx buffer descriptors */
txbd = (struct cp_bufdesc *)((char *)IMM + TxBD);
rxbd = (struct cp_bufdesc *)((char *)IMM + RxBD);
smc_chan->txbd = txbd;
smc_chan->tbase = txbd;
smc_chan->txsize = TxSIZE;
smc_chan->rxbd = rxbd;
smc_chan->rbase = rxbd;
smc_chan->rxsize = RxSIZE;
/* set max_idle feature - generate interrupt after 4 chars idle period */
uart_pram->max_idl = 4;
/* no last brk char received */
uart_pram->brkln = 0;
/* no break condition occurred */
uart_pram->brkec = 0;
/* 1 break char sent on top XMIT */
uart_pram->brkcr = 1;
/* setup RX buffer descriptors */
for (i = 0; i < RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = _BD_CTL_Ready | _BD_CTL_Int;
if (i == (RxNUM-1)) rxbd->ctrl |= _BD_CTL_Wrap; // Last buffer
RxBUF += RxSIZE;
rxbd++;
}
/* setup TX buffer descriptors */
for (i = 0; i < TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
if (i == (TxNUM-1)) txbd->ctrl |= _BD_CTL_Wrap; // Last buffer
TxBUF += TxSIZE;
txbd++;
}
/*
* Reset Rx & Tx params
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
IMM->cpm_cpcr = smc_chan->channel | CPCR_INIT_TX_RX_PARAMS | CPCR_FLG;
HAL_IO_BARRIER(); // Inforce I/O ordering
/*
* Clear any previous events. Enable interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
*/
ctl->smc_smce = 0xFF;
ctl->smc_smcm = SMCE_Bsy|SMCE_Tx|SMCE_Rx;
}
// Function to set up internal tables for device.
static void
quicc_scc_serial_init_info(quicc_sxx_serial_info *scc_chan,
volatile struct uart_pram *uart_pram,
volatile struct scc_regs *ctl,
int TxBD, int TxNUM, int TxSIZE,
cyg_uint8 *TxBUF,
int RxBD, int RxNUM, int RxSIZE,
cyg_uint8 *RxBUF,
int portAmask, int portBmask, int portCmask,
int port)
{
EPPC *eppc = eppc_base();
struct cp_bufdesc *txbd, *rxbd;
int i;
// Disable channel during setup
ctl->scc_gsmr_l = 0;
scc_chan->pram = (void *)uart_pram;
scc_chan->ctl = (void *)ctl;
// Set up baud rate generator
scc_chan->brg = _mpc8xx_allocate_brg(port);
/*
* Set up the PortA/B/C pins for UART operation.
*/
eppc->pio_papar |= portAmask;
eppc->pio_padir &= ~portAmask;
eppc->pio_paodr &= ~portAmask;
eppc->pio_pcdir &= portCmask;
eppc->pio_pcpar &= portCmask;
eppc->pio_pcso |= portCmask;
eppc->pip_pbpar |= portBmask;
eppc->pip_pbdir |= portBmask;
/*
* SDMA & LCD bus request level 5
* (Section 16.10.2.1)
*/
eppc->dma_sdcr = 1;
/*
* Set Rx and Tx function code
* (Section 16.15.4.2)
*/
uart_pram->rfcr = 0x18;
uart_pram->tfcr = 0x18;
/*
* Set pointers to buffer descriptors.
* (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
*/
uart_pram->rbase = RxBD;
uart_pram->tbase = TxBD;
/* tx and rx buffer descriptors */
txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
scc_chan->txbd = txbd;
scc_chan->tbase = txbd;
scc_chan->txsize = TxSIZE;
scc_chan->rxbd = rxbd;
scc_chan->rbase = rxbd;
scc_chan->rxsize = RxSIZE;
/* max receive buffer length */
uart_pram->mrblr = RxSIZE;
/* set max_idle feature - generate interrupt after 4 chars idle period */
uart_pram->max_idl = 4;
/* no last brk char received */
uart_pram->brkln = 0;
/* no break condition occurred */
uart_pram->brkec = 0;
/* 1 break char sent on top XMIT */
uart_pram->brkcr = 1;
/* character mask */
uart_pram->rccm = 0xC0FF;
/* control characters */
for (i = 0; i < 8; i++) {
uart_pram->cc[i] = 0x8000; // Mark unused
}
/* setup RX buffer descriptors */
for (i = 0; i < RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
if (i == (RxNUM-1)) rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
RxBUF += RxSIZE;
rxbd++;
}
/* setup TX buffer descriptors */
for (i = 0; i < TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
if (i == (TxNUM-1)) txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
TxBUF += TxSIZE;
txbd++;
}
/*
* Reset Rx & Tx params
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
while (eppc->cp_cr & QUICC_SMC_CMD_Go )
continue;
/*
* Clear any previous events. Enable interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
ctl->scc_scce = 0xFFFF;
ctl->scc_sccm = (QUICC_SCCE_BSY | QUICC_SCCE_TX | QUICC_SCCE_RX);
}
