externC void
_mb93091_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
cyg_pci_init();
// Enable controller - most of the basic configuration
// was set up at boot time in "platform.inc"
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
}
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0x10,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_ACTIVE)) {
/* It was already active. Turn it off so it gets
configured with a base address which is actually
in the range Redboot can see */
cmd_state &= ~CYG_PCI_CFG_COMMAND_ACTIVE;
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0x10,0),
CYG_PCI_CFG_COMMAND, cmd_state);
}
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
externC void
_csb281_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
// Initialize PCI support
cyg_pci_init();
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
// Force PCI-side window to 0
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0x01);
// Enable bus mastering from host
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
// Configure interrupts (high level)?
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}
externC void
hal_ppc405_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state, bridge_state;
if (_init) return;
_init = 1;
// Configure PCI bridge
HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0);
HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE);
HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001);
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0);
HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001);
// Indicate that the bridge has been configured
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
bridge_state |= 0x0001;
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state);
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
cyg_pci_init();
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
#if defined(CYGPKG_IO_PCI_DEBUG)
diag_printf("Configure PCI bus\n");
#endif
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
#if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS)
if (1) {
cyg_uint8 req;
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req);
diag_printf("\n");
diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid));
diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf(" Vendor Id: 0x%04X", dev_info.vendor);
diag_printf(", Device Id: 0x%04X", dev_info.device);
diag_printf(", Command: 0x%04X", dev_info.command);
diag_printf(", IRQ: %d\n", req);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
#endif
}
externC void
_csb281_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
if (_init) return;
_init = 1;
// Initialize PCI support
cyg_pci_init();
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
// Force PCI-side window to 0
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0x01);
// Enable bus mastering from host
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
if (0){
cyg_uint8 devfn;
cyg_pci_device_id devid;
cyg_pci_device dev_info;
int i;
devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN;
while (cyg_pci_find_next(devid, &devid)) {
devfn = CYG_PCI_DEV_GET_DEVFN(devid);
cyg_pci_get_device_info(devid, &dev_info);
diag_printf("\n");
diag_printf("Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid));
diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn));
diag_printf("PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn));
diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor);
diag_printf("Device Id : 0x%08X\n", dev_info.device);
for (i = 0; i < dev_info.num_bars; i++) {
diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
dev_info.base_size[i], dev_info.base_map[i]);
}
}
}
// Configure interrupts (high level)?
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1);
}
// Write functions
void
cyg_pcihw_write_config_uint8( cyg_uint8 bus, cyg_uint8 devfn,
cyg_uint8 offset, cyg_uint8 val)
{
HAL_PCI_CFG_WRITE_UINT8(bus, devfn, offset, val);
}
