Example #1
0
void EP956Controller_Reset(void)
{
	// Initial Variables
	//EP956_Reg_Set_Bit(EP956_Pixel_Repetition_Control, EP956_Pixel_Repetition_Control__OSCSEL);

	//Temp_Byte[0] = EP956_General_Control_2__RIEF | EP956_General_Control_2__VIEF; // we use polling
	//EP956_Reg_Write(EP956_General_Control_2, Temp_Byte, 1);

//#ifndef OUT_HDCP_DIS
#if 0
	// Copy the Test HDCP Key
	//memcpy(HDCP_Key, HDCP_Key_Default, sizeof(HDCP_Key_Default));
	EP956_AssignKeyAddress(HDCP_Key_Default);
	status = 0;
#else
	// Read HDCP Key for EEPROM
	//status = HDMI_Tx_Get_Key(HDCP_Key);
	status = 0;
#endif


	HDCP_Fake(0);
	pEP956C_Registers->System_Status &= ~EP956E_System_Status__KEY_FAIL;
	if(status) {
		// Do not upload the default Key!
		pEP956C_Registers->System_Configuration |= EP956E_System_Configuration__HDCP_DIS;
		EP_DEV_DBG("No HDCP Key\n");
	}
	else {
		// Check HDCP key and up load the key
//		Temp_Byte[0] = 0;
//		for(i=0; i<328; ++i) {
//			Temp_Byte[0] += *((unsigned char *)HDCP_Key+i);

//			if(!(i % 16))
//				EP_DEV_DBG("\n",HDCP_Key[i]);
//			if(!(i % 8))
//				EP_DEV_DBG("\t",HDCP_Key[i]);
//			EP_DEV_DBG("%02X ",HDCP_Key[i]);
//		}	

		EP_DEV_DBG("HDCP Key Check Sum 0x%02X\n", Temp_Byte[0] );
		if(0)//(/*HDCP_Key[3*8+7] != 0x50 || HDCP_Key[12*8+7] != 0x01 ||*/ Temp_Byte[0] != 0x00) 
		{// || HDCP_Key[40*8+0] != 0xA5) {
			HDCP_Fake(1);
			pEP956C_Registers->System_Status |= EP956E_System_Status__KEY_FAIL;
			EP_DEV_DBG("Check Key failed!\n");
		}
		else {
		
			// Upload the HDCP key
			if(EP956_Load_HDCP_Key()) {
			
				// Check AKSV
		    	if(!HDMI_Tx_read_AKSV(pEP956C_Registers->HDCP_AKSV)) {
					// Test failed
					pEP956C_Registers->System_Status |= EP956E_System_Status__KEY_FAIL;
					EP_DEV_DBG("Upload KSV failed!\n");
				}
			}
			else {
				pEP956C_Registers->System_Status |= EP956E_System_Status__KEY_FAIL;
				EP_DEV_DBG("Upload Key failed!\n");
			}
		}
	}
//#endif

	// EP956 Interface Reset
	EP956_If_Reset();

	// VBus Interface Reset
	VBUS_If_Reset();


	// Reset Variables

	// bit
	//Event_HDMI_Int = 0;
	is_Cap_HDMI = 0;
	is_Cap_YCC444 = is_Cap_YCC422 = 0;

	is_Connected = 0;
	is_Source_Ready = 0;
	is_ReceiverSense = 0;
	is_Hot_Plug = 0;
	is_VBus_Power = 0;
	is_PATH_EN = 0;
	is_PackedPixelMode = 0;

	is_VideoChanging = 0;
	is_AudioChanging = 0;
	is_HDMI_Mode_Set = 0;

	// data
	ConnectionState = 0;
	HP_ChangeCount = 0;
	RSEN_ChangeCount = 0;
	TX_State = TXS_Search_EDID;
	//VideoChg_TimeCount = 0;
	//AudioChg_TimeCount = 0;
	//ReadEDID_TimeCount = 0;
	//HDMI_Mode_Set_TimeCount = 0;

	// data
	if(TX_State > TXS_Search_EDID) {
		EP_DEV_DBG("State Transist: Reset -> [TXS_Wait_Upstream]\n");
		TX_State = TXS_Wait_Upstream;
	}

	MHL_Tx_CBUS_Disconnect();
}
Example #2
0
void EP932Controller_Reset(void)
{
#if defined(Enable_HDCP)
	SMBUS_STATUS status = SMBUS_STATUS_Success;
#endif
	// Reset Hardware
	DBG_printf(("Reset EP932\r\n"));

	EP_EP932M_Reset();
    pEP932C_Registers->System_Configuration = 0;
    pEP932C_Registers->System_Status = 0;
    
	EP932_EnableHPInit();
	
	// Initial Variables
	EP932_Reg_Set_Bit(EP932_Pixel_Repetition_Control, EP932_Pixel_Repetition_Control__OSCSEL);

#if defined(Enable_HDCP)

	// Read HDCP Key for EEPROM
	status = HDMI_Tx_Get_Key((unsigned char *)HDCP_Key);
	//DBG_printf(("Read HDCP Key = 0x%02X\r\n",(int)status));
	HDCP_Fake(0);
	pEP932C_Registers->System_Status &= ~EP932E_System_Status__KEY_FAIL;

	// Check HDCP key and up load the key
	if(status) {
		// Do not upload the default Key!
		pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
		pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
		DBG_printf(("No HDCP Key\r\n"));
	}
	else {
		// Check HDCP key and up load the key
		ChkSum = 0;
		for(i=0; i<328; ++i) {
			ChkSum += *((unsigned char *)HDCP_Key+i);
		}	
		DBG_printf(("HDCP Key Check Sum 0x%02X\r\n", (int)ChkSum ));
		if(HDCP_Key[3][7] != 0x50 || HDCP_Key[12][7] != 0x01 || ChkSum != 0x00) {// || HDCP_Key[40][0] != 0xA5) {
			HDCP_Fake(1);
			pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
			DBG_printf(("Check Key failed!\r\n"));
			pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
			//DBG_printf(("Disable HDCP \r\n"));
		}
		else {
			// Upload the key 0-39
			for(i=0; i<40; ++i) {
				DDC_Data[0] = (unsigned char)i;
				status |= EP932_Reg_Write(EP932_Key_Add, DDC_Data, 1);
				memcpy(DDC_Data,&HDCP_Key[i][0],7);
				status |= EP932_Reg_Write(EP932_Key_Data, DDC_Data, 7);
			}
			// Read and check	
			for(i=0; i<40; ++i) {
				DDC_Data[0] = (unsigned char)i;
				status |= EP932_Reg_Write(EP932_Key_Add, DDC_Data, 1);
				status |= EP932_Reg_Read(EP932_Key_Data, DDC_Data, 7);
				if((memcmp(DDC_Data,&HDCP_Key[i][0],7) != 0) || status) {
					// Test failed
					HDCP_Fake(1);
					pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
					DBG_printf(("Check Key failed!\r\n"));
					pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
					//DBG_printf(("Disable HDCP \r\n"));
					break;
				}
			}
			// Upload final KSV 40
			DDC_Data[0] = 40;
			status |= EP932_Reg_Write(EP932_Key_Add, DDC_Data, 1);
			memcpy(DDC_Data,&HDCP_Key[40][0],7);
			status |= EP932_Reg_Write(EP932_Key_Data, DDC_Data, 7);
			// Read back and check
	    	if(!HDMI_Tx_read_AKSV(pEP932C_Registers->HDCP_AKSV)) {
				// Test failed
				HDCP_Fake(1);
				pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
				DBG_printf(("Check KSV failed!\r\n"));
				pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS;
				//DBG_printf(("Disable HDCP \r\n"));
			}
		}	
	}

#else

	pEP932C_Registers->System_Status |= EP932E_System_Status__KEY_FAIL;
	pEP932C_Registers->System_Configuration |= EP932E_System_Configuration__HDCP_DIS|EP932E_System_Configuration__FORCE_HDMI_CAP;

#endif 

	// EP932 Interface Reset
	EP932_If_Reset();

	// Internal Variable Reset
	// bit
	//Event_HDMI_Int = 0;
	is_ReceiverSense = 0;

	// data
	Backup_Analog_Test_Control = 0;
	if(TX_State > TXS_Search_EDID) {
		DBG_printf(("\r\nState Transist: Reset -> [TXS_Wait_Upstream]\r\n"));
		TX_State = TXS_Wait_Upstream;
	}

	DBG_printf(("EP932Controller_Reset finish\r\n"));
}