static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
{
struct mmc_request *mrq = host->mrq;
struct mmc_data *data;
u32 crc;
WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
if (host->mrq == NULL)
return;
data = mrq->cmd->data;
if (status == 0)
status = au_readl(HOST_STATUS(host));
/* The transaction is really over when the SD_STATUS_DB bit is clear */
while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
status = au_readl(HOST_STATUS(host));
data->error = MMC_ERR_NONE;
dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
/* Process any errors */
crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
if (host->flags & HOST_F_XMIT)
crc |= ((status & 0x07) == 0x02) ? 0 : 1;
if (crc)
data->error = MMC_ERR_BADCRC;
/* Clear the CRC bits */
au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
data->bytes_xfered = 0;
if (data->error == MMC_ERR_NONE) {
if (host->flags & HOST_F_DMA) {
u32 chan = DMA_CHANNEL(host);
chan_tab_t *c = *((chan_tab_t **) chan);
au1x_dma_chan_t *cp = c->chan_ptr;
data->bytes_xfered = cp->ddma_bytecnt;
}
else
data->bytes_xfered =
(data->blocks * (1 << data->blksz_bits)) -
host->pio.len;
}
au1xmmc_finish_request(host);
}
static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
{
struct mmc_request *mrq = host->mrq;
struct mmc_data *data;
u32 crc;
WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
if (host->mrq == NULL)
return;
data = mrq->cmd->data;
if (status == 0)
status = au_readl(HOST_STATUS(host));
while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
status = au_readl(HOST_STATUS(host));
data->error = 0;
dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
if (host->flags & HOST_F_XMIT)
crc |= ((status & 0x07) == 0x02) ? 0 : 1;
if (crc)
data->error = -EILSEQ;
au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
data->bytes_xfered = 0;
if (!data->error) {
if (host->flags & HOST_F_DMA) {
#ifdef CONFIG_SOC_AU1200
u32 chan = DMA_CHANNEL(host);
chan_tab_t *c = *((chan_tab_t **)chan);
au1x_dma_chan_t *cp = c->chan_ptr;
data->bytes_xfered = cp->ddma_bytecnt;
#endif
} else
data->bytes_xfered =
(data->blocks * data->blksz) - host->pio.len;
}
au1xmmc_finish_request(host);
}
static void au1xmmc_tasklet_data(unsigned long param)
{
struct au1xmmc_host *host = (struct au1xmmc_host *)param;
u32 status = au_readl(HOST_STATUS(host));
au1xmmc_data_complete(host, status);
}
static void au1xmmc_send_pio(struct au1xmmc_host *host)
{
struct mmc_data *data = 0;
int sg_len, max, count = 0;
unsigned char *sg_ptr;
u32 status = 0;
struct scatterlist *sg;
data = host->mrq->data;
if (!(host->flags & HOST_F_XMIT))
return;
/* This is the pointer to the data buffer */
sg = &data->sg[host->pio.index];
sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset;
/* This is the space left inside the buffer */
sg_len = data->sg[host->pio.index].length - host->pio.offset;
/* Check to if we need less then the size of the sg_buffer */
max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
for(count = 0; count < max; count++ ) {
unsigned char val;
status = au_readl(HOST_STATUS(host));
if (!(status & SD_STATUS_TH))
break;
val = *sg_ptr++;
au_writel((unsigned long) val, HOST_TXPORT(host));
au_sync();
}
host->pio.len -= count;
host->pio.offset += count;
if (count == sg_len) {
host->pio.index++;
host->pio.offset = 0;
}
if (host->pio.len == 0) {
IRQ_OFF(host, SD_CONFIG_TH);
if (host->flags & HOST_F_STOP)
SEND_STOP(host);
tasklet_schedule(&host->data_task);
}
}
static void au1xmmc_send_pio(struct au1xmmc_host *host)
{
struct mmc_data *data;
int sg_len, max, count;
unsigned char *sg_ptr, val;
u32 status;
struct scatterlist *sg;
data = host->mrq->data;
if (!(host->flags & HOST_F_XMIT))
return;
sg = &data->sg[host->pio.index];
sg_ptr = sg_virt(sg) + host->pio.offset;
sg_len = data->sg[host->pio.index].length - host->pio.offset;
max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
if (max > AU1XMMC_MAX_TRANSFER)
max = AU1XMMC_MAX_TRANSFER;
for (count = 0; count < max; count++) {
status = au_readl(HOST_STATUS(host));
if (!(status & SD_STATUS_TH))
break;
val = *sg_ptr++;
au_writel((unsigned long)val, HOST_TXPORT(host));
au_sync();
}
host->pio.len -= count;
host->pio.offset += count;
if (count == sg_len) {
host->pio.index++;
host->pio.offset = 0;
}
if (host->pio.len == 0) {
IRQ_OFF(host, SD_CONFIG_TH);
if (host->flags & HOST_F_STOP)
SEND_STOP(host);
tasklet_schedule(&host->data_task);
}
}
static void au1xmmc_receive_pio(struct au1xmmc_host *host)
{
struct mmc_data *data;
int max, count, sg_len = 0;
unsigned char *sg_ptr = NULL;
u32 status, val;
struct scatterlist *sg;
data = host->mrq->data;
if (!(host->flags & HOST_F_RECV))
return;
max = host->pio.len;
if (host->pio.index < host->dma.len) {
sg = &data->sg[host->pio.index];
sg_ptr = sg_virt(sg) + host->pio.offset;
/* This is the space left inside the buffer */
sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
/* Check if we need less than the size of the sg_buffer */
if (sg_len < max)
max = sg_len;
}
if (max > AU1XMMC_MAX_TRANSFER)
max = AU1XMMC_MAX_TRANSFER;
for (count = 0; count < max; count++) {
status = au_readl(HOST_STATUS(host));
if (!(status & SD_STATUS_NE))
break;
if (status & SD_STATUS_RC) {
DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
host->pio.len, count);
break;
}
if (status & SD_STATUS_RO) {
DBG("RX Overrun [%d + %d]\n", host->pdev->id,
host->pio.len, count);
break;
}
else if (status & SD_STATUS_RU) {
DBG("RX Underrun [%d + %d]\n", host->pdev->id,
host->pio.len, count);
break;
}
val = au_readl(HOST_RXPORT(host));
if (sg_ptr)
*sg_ptr++ = (unsigned char)(val & 0xFF);
}
host->pio.len -= count;
host->pio.offset += count;
if (sg_len && count == sg_len) {
host->pio.index++;
host->pio.offset = 0;
}
if (host->pio.len == 0) {
/* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
IRQ_OFF(host, SD_CONFIG_NE);
if (host->flags & HOST_F_STOP)
SEND_STOP(host);
tasklet_schedule(&host->data_task);
}
}
static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
struct mmc_command *cmd, struct mmc_data *data)
{
u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
switch (mmc_resp_type(cmd)) {
case MMC_RSP_NONE:
break;
case MMC_RSP_R1:
mmccmd |= SD_CMD_RT_1;
break;
case MMC_RSP_R1B:
mmccmd |= SD_CMD_RT_1B;
break;
case MMC_RSP_R2:
mmccmd |= SD_CMD_RT_2;
break;
case MMC_RSP_R3:
mmccmd |= SD_CMD_RT_3;
break;
default:
printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
mmc_resp_type(cmd));
return -EINVAL;
}
if (data) {
if (data->flags & MMC_DATA_READ) {
if (data->blocks > 1)
mmccmd |= SD_CMD_CT_4;
else
mmccmd |= SD_CMD_CT_2;
} else if (data->flags & MMC_DATA_WRITE) {
if (data->blocks > 1)
mmccmd |= SD_CMD_CT_3;
else
mmccmd |= SD_CMD_CT_1;
}
}
au_writel(cmd->arg, HOST_CMDARG(host));
au_sync();
if (wait)
IRQ_OFF(host, SD_CONFIG_CR);
au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
au_sync();
/* Wait for the command to go on the line */
while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
/* nop */;
/* Wait for the command to come back */
if (wait) {
u32 status = au_readl(HOST_STATUS(host));
while (!(status & SD_STATUS_CR))
status = au_readl(HOST_STATUS(host));
/* Clear the CR status */
au_writel(SD_STATUS_CR, HOST_STATUS(host));
IRQ_ON(host, SD_CONFIG_CR);
}
return 0;
}
static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
struct mmc_command *cmd)
{
u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
switch(cmd->flags) {
case MMC_RSP_R1:
mmccmd |= SD_CMD_RT_1;
break;
case MMC_RSP_R1B:
mmccmd |= SD_CMD_RT_1B;
break;
case MMC_RSP_R2:
mmccmd |= SD_CMD_RT_2;
break;
case MMC_RSP_R3:
mmccmd |= SD_CMD_RT_3;
break;
}
switch(cmd->opcode) {
case MMC_READ_SINGLE_BLOCK:
case 51:
mmccmd |= SD_CMD_CT_2;
break;
case MMC_READ_MULTIPLE_BLOCK:
mmccmd |= SD_CMD_CT_4;
break;
case MMC_WRITE_BLOCK:
mmccmd |= SD_CMD_CT_1;
break;
case MMC_WRITE_MULTIPLE_BLOCK:
mmccmd |= SD_CMD_CT_3;
break;
case MMC_STOP_TRANSMISSION:
mmccmd |= SD_CMD_CT_7;
break;
}
au_writel(cmd->arg, HOST_CMDARG(host));
au_sync();
if (wait)
IRQ_OFF(host, SD_CONFIG_CR);
au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
au_sync();
/* Wait for the command to go on the line */
while(1) {
if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
break;
}
/* Wait for the command to come back */
if (wait) {
u32 status = au_readl(HOST_STATUS(host));
while(!(status & SD_STATUS_CR))
status = au_readl(HOST_STATUS(host));
/* Clear the CR status */
au_writel(SD_STATUS_CR, HOST_STATUS(host));
IRQ_ON(host, SD_CONFIG_CR);
}
return MMC_ERR_NONE;
}
