static sw_error_t
_shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
{
sw_error_t rv;
a_uint32_t entry, data;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry);
if (data)
{
*enable = A_TRUE;
SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry);
*queue = data;
}
else
{
*enable = A_FALSE;
*queue = 0;
}
return SW_OK;
}
static sw_error_t
_horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t * action)
{
sw_error_t rv;
a_uint32_t data;
a_uint32_t port_lock_en, port_drop_en;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data);
SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data);
if (1 == port_lock_en) {
if (1 == port_drop_en) {
*action = FAL_MAC_DROP;
} else {
*action = FAL_MAC_RDT_TO_CPU;
}
} else {
*action = FAL_MAC_FRWRD;
}
return SW_OK;
}
static sw_error_t
_horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t force, reg;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
if (0 == force)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
static sw_error_t
_horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t cmd)
{
sw_error_t rv;
a_uint32_t data;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU)) {
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (FAL_MAC_FRWRD == cmd) {
SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
} else if (FAL_MAC_DROP == cmd) {
SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
} else if (FAL_MAC_RDT_TO_CPU == cmd) {
SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
} else {
return SW_NOT_SUPPORTED;
}
HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
sizeof (a_uint32_t));
return rv;
}
static sw_error_t
horus_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
hsl_dev_t *pdev = NULL;
a_uint32_t port_id;
a_uint32_t data;
sw_error_t rv;
pdev = hsl_dev_ptr_get(dev_id);
if (NULL == pdev)
{
return SW_NOT_INITIALIZED;
}
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
if (port_id == pdev->cpu_port_nr)
{
continue;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
_isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
fal_acl_udf_type_t udf_type, a_uint32_t * offset,
a_uint32_t * length)
{
sw_error_t rv;
a_uint32_t reg;
HSL_DEV_ID_CHECK(dev_id);
if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
|| (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type)) {
HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
} else {
HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
}
SW_RTN_ON_ERROR(rv);
switch (udf_type) {
case FAL_ACL_UDF_TYPE_L2:
SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg);
SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg);
break;
case FAL_ACL_UDF_TYPE_L3:
SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg);
SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg);
break;
case FAL_ACL_UDF_TYPE_L4:
SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg);
SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg);
break;
case FAL_ACL_UDF_TYPE_L2_SNAP:
SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg);
SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg);
break;
case FAL_ACL_UDF_TYPE_L3_PLUS:
SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg);
SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg);
break;
default:
return SW_BAD_PARAM;
}
return SW_OK;
}
static sw_error_t
_athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_duplex_t duplex)
{
sw_error_t rv;
a_uint32_t phy_id = 0;
a_uint32_t reg_save = 0;
a_uint32_t reg_val = 0;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
{
return SW_BAD_PARAM;
}
SW_RTN_ON_NULL (phy_drv = hsl_phy_api_ops_get (dev_id));
if (NULL == phy_drv->phy_duplex_set)
return SW_NOT_SUPPORTED;
if (FAL_DUPLEX_BUTT <= duplex)
{
return SW_BAD_PARAM;
}
rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
SW_RTN_ON_ERROR(rv);
//save reg value
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
reg_save = reg_val;
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
//set mac be config by sw and turn off RX TX MAC_EN
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
rv = phy_drv->phy_duplex_set(dev_id, phy_id, duplex);
//retore reg value
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_save), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
athena_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
{
a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
sw_error_t rv;
while (vt_busy && --i) {
HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
(a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (i == 0)
return SW_BUSY;
HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
(a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (vt_full) {
val = 0x10;
HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (VLAN_LOAD_ENTRY == op) {
return SW_FULL;
} else if (VLAN_PURGE_ENTRY == op) {
return SW_NOT_FOUND;
}
}
return SW_OK;
}
static sw_error_t
_horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val, force, reg;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
if (force)
{
/* flow control isn't in force mode so can't set */
return SW_DISABLE;
}
SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_dess_mib_op_commit(a_uint32_t dev_id, a_uint32_t op)
{
a_uint32_t mib_busy = 1, i = 0x1000, val;
sw_error_t rv;
while (mib_busy && --i)
{
HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
(a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (i == 0)
return SW_BUSY;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val);
SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val);
HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_busy = 1;
i = 0x1000;
while (mib_busy && --i)
{
HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
(a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (i == 0)
return SW_FAIL;
return SW_OK;
}
static sw_error_t
_horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable)
{
sw_error_t rv;
a_uint32_t force, reg;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
if (force != (a_uint32_t) enable)
{
return SW_OK;
}
if (A_TRUE == enable)
{
SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg);
}
else if (A_FALSE == enable)
{
SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
}
else
{
return SW_BAD_PARAM;
}
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
_shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
{
sw_error_t rv;
a_uint32_t entry;
hsl_dev_t *p_dev;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (A_TRUE == enable)
{
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry);
SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
if (queue >= p_dev->nr_queue)
{
return SW_BAD_PARAM;
}
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry);
}
else if (A_FALSE == enable)
{
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry);
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry);
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
isis_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
hsl_dev_t *pdev = NULL;
a_uint32_t port_id;
a_uint32_t data;
sw_error_t rv;
pdev = hsl_dev_ptr_get(dev_id);
if (NULL == pdev) {
return SW_NOT_INITIALIZED;
}
/* Set default FDB hash mode as CRC10 */
data = 1;
HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, HASH_MODE,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
for (port_id = 0; port_id < pdev->nr_ports; port_id++) {
if (port_id == pdev->cpu_port_nr) {
continue;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
_horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
led_pattern_id_t id, led_ctrl_pattern_t * pattern)
{
a_uint32_t data = 0, reg, mode;
a_uint32_t addr;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (group >= LED_GROUP_BUTT)
{
return SW_BAD_PARAM;
}
if (id > MAX_LED_PATTERN_ID)
{
return SW_BAD_PARAM;
}
if ((LED_MAC_PORT_GROUP == group) && (0 != id))
{
return SW_BAD_PARAM;
}
if (LED_MAC_PORT_GROUP == group)
{
addr = LED_PATTERN_ADDR + 8;
}
else
{
addr = LED_PATTERN_ADDR + (id << 2);
}
if (LED_ALWAYS_OFF == pattern->mode)
{
mode = 0;
}
else if (LED_ALWAYS_BLINK == pattern->mode)
{
mode = 1;
}
else if (LED_ALWAYS_ON == pattern->mode)
{
mode = 2;
}
else if (LED_PATTERN_MAP_EN == pattern->mode)
{
mode = 3;
}
else
{
return SW_BAD_PARAM;
}
SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << POWER_ON_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << LINK_100M_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << LINK_10M_LIGHT_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
}
if (pattern->map & (1 << COLLISION_BLINK_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
}
if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
}
if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
}
if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
{
SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
}
if (LED_BLINK_2HZ == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
}
else if (LED_BLINK_4HZ == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
}
else if (LED_BLINK_8HZ == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
}
else if (LED_BLINK_TXRX == pattern->freq)
{
SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (LED_WAN_PORT_GROUP == group)
{
reg &= 0xffff;
reg |= (data << 16);
}
else
{
reg &= 0xffff0000;
reg |= data;
}
HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
(a_uint8_t *) (®),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (LED_WAN_PORT_GROUP == group)
{
return SW_OK;
}
HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (LED_LAN_PORT_GROUP == group)
{
if (id)
{
SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
}
else
{
SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
}
}
else
{
SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data);
}
HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
return SW_OK;
}
static sw_error_t
shiva_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
{
sw_error_t rv;
a_uint32_t reg[3] = { 0 };
a_uint32_t status = 0;
a_uint32_t hwop = op;
if ((ARL_NEXT_ENTRY == op)
|| (ARL_FIND_ENTRY == op))
{
shiva_fdb_fill_addr(entry->addr, ®[0], ®[1]);
}
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
(a_uint8_t *) (®[0]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
(a_uint8_t *) (®[1]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
/* set status not zero */
if (ARL_NEXT_ENTRY == op)
{
reg[2] = 0xf0000;
}
if (ARL_FIRST_ENTRY == op)
{
hwop = ARL_NEXT_ENTRY;
}
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
(a_uint8_t *) (®[2]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
rv = shiva_fdb_commit(dev_id, hwop);
SW_RTN_ON_ERROR(rv);
/* get hardware enrety */
HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
(a_uint8_t *) (®[0]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
(a_uint8_t *) (®[1]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
(a_uint8_t *) (®[2]), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
shiva_atu_hw_to_sw(reg, entry);
/* If hardware return back with address and status all zero,
that means no other next valid entry in fdb table */
if ((A_TRUE == shiva_fdb_is_zeroaddr(entry->addr))
&& (0 == status))
{
if (ARL_NEXT_ENTRY == op)
{
return SW_NO_MORE;
}
else if ((ARL_FIND_ENTRY == op)
|| (ARL_FIRST_ENTRY == op))
{
return SW_NOT_FOUND;
}
else
{
return SW_FAIL;
}
}
else
{
return SW_OK;
}
}
static sw_error_t
shiva_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
{
sw_error_t rv;
a_uint32_t busy = 1;
a_uint32_t full_vio;
a_uint32_t i = 1000;
a_uint32_t entry;
a_uint32_t hwop = op;
while (busy && --i)
{
HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
(a_uint8_t *) (&busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (0 == i)
{
return SW_BUSY;
}
HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
if (ARL_FLUSH_PORT_AND_STATIC == hwop)
{
hwop = ARL_FLUSH_PORT_UNICAST;
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry);
}
if (ARL_FLUSH_PORT_NO_STATIC == hwop)
{
hwop = ARL_FLUSH_PORT_UNICAST;
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry);
}
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry);
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
busy = 1;
i = 1000;
while (busy && --i)
{
HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
(a_uint8_t *) (&busy), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_udelay(5);
}
if (0 == i)
{
return SW_FAIL;
}
HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
(a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (full_vio)
{
/* must clear AT_FULL_VOI bit */
entry = 0x1000;
HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (ARL_LOAD_ENTRY == hwop)
{
return SW_FULL;
}
else if ((ARL_PURGE_ENTRY == hwop)
|| (ARL_FLUSH_PORT_UNICAST == hwop))
{
return SW_NOT_FOUND;
}
else
{
return SW_FAIL;
}
}
return SW_OK;
}
static sw_error_t
garuda_bist_test(a_uint32_t dev_id)
{
a_uint32_t entry, data, i;
sw_error_t rv;
data = 1;
i = 0x1000;
while (data && --i)
{
HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
aos_udelay(5);
}
if (0 == i)
{
return SW_INIT_ERROR;
}
entry = 0;
SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
data = 1;
i = 0x1000;
while (data && --i)
{
HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
aos_udelay(5);
}
if (0 == i)
{
return SW_INIT_ERROR;
}
SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
if (data)
{
SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry);
if (!data)
{
return SW_INIT_ERROR;
}
SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry);
entry = 0;
SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry);
SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry);
HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
else
{
return SW_OK;
}
entry = 0;
SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
data = 1;
i = 0x1000;
while (data && --i)
{
HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
aos_udelay(5);
}
if (0 == i)
{
return SW_INIT_ERROR;
}
SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
if (data)
{
return SW_INIT_ERROR;
}
return SW_OK;
}
static sw_error_t
garuda_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
garuda_init_spec_cfg *garuda_init_cfg = NULL;
hsl_dev_t *pdev = NULL;
hsl_init_mode cpu_mode;
a_uint32_t port_id;
a_uint32_t data;
sw_error_t rv;
pdev = hsl_dev_ptr_get(dev_id);
if (NULL == pdev)
{
return SW_NOT_INITIALIZED;
}
cpu_mode = cfg->cpu_mode;
HSL_REG_ENTRY_GET(rv, dev_id, POSTRIP, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
/* phy pll on */
SW_SET_REG_BY_FIELD(POSTRIP, PHY_PLL_ON, 1, data);
garuda_init_cfg = (garuda_init_spec_cfg* )(cfg->chip_spec_cfg);
if (!garuda_init_cfg)
{
return SW_BAD_PARAM;
}
/* delay */
if (A_TRUE == garuda_init_cfg->rx_delay_s1)
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 0, data);
}
if (A_TRUE == garuda_init_cfg->rx_delay_s0)
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 0, data);
}
if (A_TRUE == garuda_init_cfg->tx_delay_s1)
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 0, data);
}
if (A_TRUE == garuda_init_cfg->tx_delay_s0)
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
}
/* tx/rx delay enable */
if (A_TRUE == garuda_init_cfg->rgmii_txclk_delay)
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 0, data);
}
/* tx/rx delay enable */
if (A_TRUE == garuda_init_cfg->rgmii_rxclk_delay)
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 0, data);
}
/* mac5 default mode */
/*SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);*/
/* mac0 default phy mode */
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_MAC_MODE, 0, data);
/* mac0 default rgmii mode */
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 1, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 0, data);
/* mac5 default disable mode */
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);
/* phy default mode */
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
/* modify default mode */
if (A_FALSE == garuda_init_cfg->mac0_rgmii)
{
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 1, data);
/*invert clock output for port0 gmii pad.*/
a_uint32_t temp;
HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
(a_uint8_t *) (&temp), sizeof (a_uint32_t));
temp |= 1<<MASK_CTL_MII_CLK0_SEL_BOFFSET;
HSL_REG_ENTRY_SET(rv, dev_id, MASK_CTL, 0,
(a_uint8_t *) (&temp), sizeof (a_uint32_t));
}
if(HSL_CPU_2 == cpu_mode)
{
if (A_TRUE == garuda_init_cfg->mac5_rgmii)
{
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 1, data);
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
a_uint32_t phy_id = 4;
/* phy4 rgmii mode enable */
phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RGMII_MODE, F1_DEBUG_PORT_RGMII_MODE_EN);
/* Rx delay enable */
if (A_TRUE == garuda_init_cfg->phy4_rx_delay)
{
phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
}
else
{
phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
}
/* Tx delay enable */
if (A_TRUE == garuda_init_cfg->phy4_tx_delay)
{
phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
}
else
{
phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
}
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 1, data);
}
}
else if (HSL_CPU_1 == cpu_mode)
{
//SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
}
else if (HSL_CPU_1_PLUS == cpu_mode)
{
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 1, data);
}
else if (HSL_NO_CPU == cpu_mode)
{
}
HSL_REG_ENTRY_SET(rv, dev_id, POSTRIP, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
if (port_id == pdev->cpu_port_nr)
{
continue;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
_athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info)
{
a_uint32_t val0 = 0, val1 = 0;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_OUT_OF_RANGE;
}
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxBroad = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxPause = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxMulti = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxFcsErr = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxAllignErr = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val0),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxRunt = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxFragment = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx64Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx128Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx256Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx512Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx1024Byte = val0 + val1;
mib_info->Rx1518Byte = 0; //reserved for s16
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxMaxByte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxTooLong = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxGoodByte_lo = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxGoodByte_hi = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxBadByte_lo = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxBadByte_hi = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxOverFlow = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Filtered = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val0),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxBroad = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val0),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxPause = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val0),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxMulti = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxUnderRun = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx64Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx128Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx256Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx512Byte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx1024Byte = val0 + val1;
mib_info->Tx1518Byte = 0; //reserved for s16
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxMaxByte = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxOverSize = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxByte_lo = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxByte_hi = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxCollision = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxAbortCol = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxMultiCol = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxSingalCol = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxExcDefer = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val0),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxDefer = val0 + val1;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
(a_uint8_t *) (&val0), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL_2, port_id,
(a_uint8_t *) (&val1), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxLateCol = val0 + val1;
return SW_OK;
}
static sw_error_t
_dess_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info)
{
a_uint32_t val;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_OUT_OF_RANGE;
}
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxBroad = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxPause = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxMulti = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxUnderRun = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx64Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx128Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx256Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx512Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx1024Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Tx1518Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxMaxByte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxOverSize = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxByte_lo = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxByte_hi = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxCollision = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxAbortCol = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxMultiCol = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxSingalCol = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxExcDefer = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxDefer = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxLateCol = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id,
(a_uint8_t *) (&val), sizeof
(a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->TxUniCast = val;
return SW_OK;
}
static sw_error_t
_dess_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info)
{
a_uint32_t val;
sw_error_t rv;
HSL_DEV_ID_CHECK(dev_id);
if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
return SW_OUT_OF_RANGE;
}
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxBroad = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxPause = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxMulti = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxFcsErr = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxAllignErr = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxRunt = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxFragment = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx64Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx128Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx256Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx512Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx1024Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Rx1518Byte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxMaxByte = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxTooLong = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxGoodByte_lo = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxGoodByte_hi = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxBadByte_lo = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxBadByte_hi = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxOverFlow = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->Filtered = val;
HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id,
(a_uint8_t *) (&val), sizeof
(a_uint32_t));
SW_RTN_ON_ERROR(rv);
mib_info->RxUniCast = val;
return SW_OK;
}
