bool
SignalClassifier::match(Activity *act, SignalDescription& sig,
FrequencyBand& band)
{
float64_t sigLo = sig.path.rfFreq - (HZ_TO_MHZ(sig.path.width / 2));
float64_t sigHi = sig.path.rfFreq + (HZ_TO_MHZ(sig.path.width / 2));
float64_t bandLo = band.centerFreq - band.bandwidth / 2;
float64_t bandHi = band.centerFreq + band.bandwidth / 2;
float64_t obsLen = act->getDataCollectionTime();
if (sig.path.drift >= 0)
sigHi += HZ_TO_MHZ(sig.path.drift * obsLen);
else
sigLo -= HZ_TO_MHZ(sig.path.drift * obsLen);
return (sigLo < bandHi && sigHi > bandLo);
}
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
long lNewRate;
long lRate;
IMG_INT res;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
{
return PVRSRV_OK;
}
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
res = clk_enable(psSysSpecData->psSGX_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
#if 0
lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ);
if (lNewRate <= 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate"));
return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE;
}
lRate = clk_get_rate(psSysSpecData->psSGX_FCK);
if (lRate != lNewRate)
{
res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate);
if (res < 0)
{
PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res));
}
}
#endif
// IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
// PVR_TRACE((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
#if defined(DEBUG)
{
IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
}
#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
return PVRSRV_OK;
}
void nvhost_scale_emc_calibrate_emc(struct nvhost_emc_params *emc_params,
struct clk *clk_3d, struct clk *clk_3d_emc,
bool linear_emc)
{
long correction;
unsigned long max_emc;
unsigned long min_emc;
unsigned long min_rate_3d;
unsigned long max_rate_3d;
max_emc = clk_round_rate(clk_3d_emc, UINT_MAX);
max_emc = INT_TO_FX(HZ_TO_MHZ(max_emc));
min_emc = clk_round_rate(clk_3d_emc, 0);
min_emc = INT_TO_FX(HZ_TO_MHZ(min_emc));
max_rate_3d = clk_round_rate(clk_3d, UINT_MAX);
max_rate_3d = INT_TO_FX(HZ_TO_MHZ(max_rate_3d));
min_rate_3d = clk_round_rate(clk_3d, 0);
min_rate_3d = INT_TO_FX(HZ_TO_MHZ(min_rate_3d));
emc_params->emc_slope =
FXDIV((max_emc - min_emc), (max_rate_3d - min_rate_3d));
emc_params->emc_offset = max_emc -
FXMUL(emc_params->emc_slope, max_rate_3d);
/* Guarantee max 3d rate maps to max emc rate */
emc_params->emc_offset += max_emc -
(FXMUL(emc_params->emc_slope, max_rate_3d) +
emc_params->emc_offset);
emc_params->linear = linear_emc;
if (linear_emc)
return;
emc_params->emc_dip_offset = (max_emc - min_emc) / 4;
emc_params->emc_dip_slope =
-FXDIV(emc_params->emc_slope, max_rate_3d - min_rate_3d);
emc_params->emc_xmid = (max_rate_3d + min_rate_3d) / 2;
correction =
emc_params->emc_dip_offset +
FXMUL(emc_params->emc_dip_slope,
FXMUL(max_rate_3d - emc_params->emc_xmid,
max_rate_3d - emc_params->emc_xmid));
emc_params->emc_dip_offset -= correction;
}
static void nvhost_scale3d_calibrate_emc(void)
{
long correction;
unsigned long max_emc;
unsigned long min_emc;
unsigned long min_rate_3d;
unsigned long max_rate_3d;
max_emc = clk_round_rate(power_profile.clk_3d_emc, UINT_MAX);
max_emc = INT_TO_FX(HZ_TO_MHZ(max_emc));
min_emc = clk_round_rate(power_profile.clk_3d_emc, 0);
min_emc = INT_TO_FX(HZ_TO_MHZ(min_emc));
max_rate_3d = INT_TO_FX(HZ_TO_MHZ(power_profile.max_rate_3d));
min_rate_3d = INT_TO_FX(HZ_TO_MHZ(power_profile.min_rate_3d));
power_profile.emc_slope =
FXDIV((max_emc - min_emc), (max_rate_3d - min_rate_3d));
power_profile.emc_offset = max_emc -
FXMUL(power_profile.emc_slope, max_rate_3d);
/* Guarantee max 3d rate maps to max emc rate */
power_profile.emc_offset += max_emc -
(FXMUL(power_profile.emc_slope, max_rate_3d) +
power_profile.emc_offset);
power_profile.emc_dip_offset = (max_emc - min_emc) / 4;
power_profile.emc_dip_slope =
-4 * FXDIV(power_profile.emc_dip_offset,
(FXMUL(max_rate_3d - min_rate_3d,
max_rate_3d - min_rate_3d)));
power_profile.emc_xmid = (max_rate_3d + min_rate_3d) / 2;
correction =
power_profile.emc_dip_offset +
FXMUL(power_profile.emc_dip_slope,
FXMUL(max_rate_3d - power_profile.emc_xmid,
max_rate_3d - power_profile.emc_xmid));
power_profile.emc_dip_offset -= correction;
}
static int nvhost_scale3d_target(struct device *d, unsigned long *freq,
u32 flags)
{
long hz;
long after;
/* Inform that the clock is disabled */
if (!tegra_is_clk_enabled(power_profile.clk_3d)) {
*freq = 0;
return 0;
}
/* Limit the frequency */
if (*freq < power_profile.min_rate_3d)
*freq = power_profile.min_rate_3d;
else if (*freq > power_profile.max_rate_3d)
*freq = power_profile.max_rate_3d;
/* Check if we're already running at the desired speed */
if (*freq == clk_get_rate(power_profile.clk_3d))
return 0;
/* Set GPU clockrate */
if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3)
nvhost_module_set_devfreq_rate(power_profile.dev,
clk_to_idx(power_profile.clk_3d2), 0);
nvhost_module_set_devfreq_rate(power_profile.dev,
clk_to_idx(power_profile.clk_3d), *freq);
/* Set EMC clockrate */
after = (long) clk_get_rate(power_profile.clk_3d);
after = INT_TO_FX(HZ_TO_MHZ(after));
hz = FXMUL(after, power_profile.emc_slope) +
power_profile.emc_offset;
hz -= FXMUL(power_profile.emc_dip_slope,
FXMUL(after - power_profile.emc_xmid,
after - power_profile.emc_xmid)) +
power_profile.emc_dip_offset;
hz = MHZ_TO_HZ(FX_TO_INT(hz + FX_HALF)); /* round to nearest */
hz = (hz < 0) ? 0 : hz;
nvhost_module_set_devfreq_rate(power_profile.dev,
clk_to_idx(power_profile.clk_3d_emc), hz);
/* Get the new clockrate */
*freq = clk_get_rate(power_profile.clk_3d);
return 0;
}
static int VDD2PostFunc(struct notifier_block *n, unsigned long event, IMG_VOID *ptr)
{
PVR_UNREFERENCED_PARAMETER(n);
PVR_UNREFERENCED_PARAMETER(event);
PVR_UNREFERENCED_PARAMETER(ptr);
if (in_interrupt())
{
PVR_DPF((PVR_DBG_ERROR, "%s Called in interrupt context. Ignoring.", __FUNCTION__));
return 0;
}
if (!NotifyLockedOnCPU(gpsSysSpecificData))
{
return 0;
}
#if defined(DEBUG)
if (ConstraintNotificationsEnabled(gpsSysSpecificData))
{
IMG_UINT32 rate;
rate = clk_get_rate(gpsSysSpecificData->psSGX_FCK);
PVR_ASSERT(rate != 0);
PVR_DPF((PVR_DBG_MESSAGE, "%s: SGX clock rate: %dMHz", __FUNCTION__, HZ_TO_MHZ(rate)));
}
#endif
if (gpsSysSpecificData->bCallVDD2PostFunc)
{
PVRSRVDevicePostClockSpeedChange(gpsSysSpecificData->psSGXDevNode->sDevId.ui32DeviceIndex, IMG_TRUE, IMG_NULL);
gpsSysSpecificData->bCallVDD2PostFunc = IMG_FALSE;
}
else
{
if (ConstraintNotificationsEnabled(gpsSysSpecificData))
{
PVR_TRACE(("%s: Not calling PVR clock speed notification functions", __FUNCTION__));
}
}
NotifyUnlock(gpsSysSpecificData);
return 0;
}
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
IMG_INT res;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
{
return PVRSRV_OK;
}
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
#if defined(DEBUG)
{
IMG_UINT32 rate = clk_get_rate(psSysSpecData->psMPU_CK);
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: CPU Clock is %dMhz", HZ_TO_MHZ(rate)));
}
#endif
res = clk_enable(psSysSpecData->psSGX_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res));
return PVRSRV_ERROR_GENERIC;
}
res = clk_enable(psSysSpecData->psSGX_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX interface clock (%d)", res));
clk_disable(psSysSpecData->psSGX_FCK);
return PVRSRV_ERROR_GENERIC;
}
ForceMaxSGXClocks(psSysSpecData);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
return PVRSRV_OK;
}
long nvhost_scale_emc_get_emc_rate(struct nvhost_emc_params *emc_params,
long freq)
{
long hz;
freq = INT_TO_FX(HZ_TO_MHZ(freq));
hz = FXMUL(freq, emc_params->emc_slope) + emc_params->emc_offset;
if (!emc_params->linear)
hz -= FXMUL(emc_params->emc_dip_slope,
FXMUL(freq - emc_params->emc_xmid,
freq - emc_params->emc_xmid)) +
emc_params->emc_dip_offset;
hz = MHZ_TO_HZ(FX_TO_INT(hz + FX_HALF)); /* round to nearest */
hz = (hz < 0) ? 0 : hz;
return hz;
}
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
long lNewRate;
long lRate;
IMG_INT res;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
{
return PVRSRV_OK;
}
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
#if defined(DEBUG)
{
IMG_UINT32 rate = clk_get_rate(psSysSpecData->psMPU_CK);
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: CPU Clock is %dMhz", HZ_TO_MHZ(rate)));
}
#endif
res = clk_enable(psSysSpecData->psSGX_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
res = clk_enable(psSysSpecData->psSGX_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX interface clock (%d)", res));
clk_disable(psSysSpecData->psSGX_FCK);
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ);
if (lNewRate <= 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate"));
return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE;
}
lRate = clk_get_rate(psSysSpecData->psSGX_FCK);
if (lRate != lNewRate)
{
res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate);
if (res < 0)
{
PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res));
}
}
IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK); //Get the functional clock
printk(KERN_DEBUG "EnableSGXClocks: SGX Functional Clock is %dMhz\n", HZ_TO_MHZ(rate));
#if defined(SYS_OMAP3430_PIN_MEMORY_BUS_CLOCK)
omap_pm_set_min_bus_tput(&gpsPVRLDMDev->dev, OCP_INITIATOR_AGENT, OMAP_MEMORY_BUS_CLOCK_MAX);
#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
#else /* !defined(NO_HARDWARE) */
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif /* !defined(NO_HARDWARE) */
return PVRSRV_OK;
}
void
SignalClassifier::classifySignal(Activity *act, SignalDescription& sig,
SuperClusterer *superClusterer, int32_t sigNum, int32_t maxCandidates)
{
sig.pol = superClusterer->getNthPolarization(sigNum);
sig.subchannelNumber = act->getChannel()->getSubchannel(sig.path.rfFreq);
sig.signalId = superClusterer->getNthSignalId(sigNum);
sig.origSignalId = SignalId();
// initial classification of the signal depends on the
// operating mode
sig.sigClass = CLASS_CAND;
sig.reason = PASSED_POWER_THRESH;
// test for zero-drift signal
if (operations.test(REJECT_ZERO_DRIFT_SIGNALS)) {
float64_t absDrift = fabs(sig.path.drift);
if (absDrift <= params.zeroDriftTolerance) {
sig.sigClass = CLASS_RFI;
sig.reason = ZERO_DRIFT;
}
}
// test for too-big-drift signal
if (operations.test(REJECT_ZERO_DRIFT_SIGNALS)) {
float32_t absDrift = fabs(sig.path.drift);
float32_t maxDrift = params.maxDriftRateTolerance
* MHZ_TO_GHZ(params.dxSkyFreq);
if (absDrift > maxDrift) {
sig.sigClass = CLASS_RFI;
sig.reason = DRIFT_TOO_HIGH;
}
}
// test for recent RFI mask match
Debug(DEBUG_SIGNAL_CLASS,
(int32_t) operations.test(APPLY_RECENT_RFI_MASK),
"apply recent RFI mask");
Debug(DEBUG_SIGNAL_CLASS, (void *) recentRfi, "recent RFI mask");
if (act->getMode() == PRIMARY) {
if (operations.test(APPLY_RECENT_RFI_MASK) && recentRfi) {
Debug(DEBUG_SIGNAL_CLASS, (void *) recentRfi, "apply mask?");
if (recentRfi->isMasked(sig.path.rfFreq,
HZ_TO_MHZ(sig.path.width))) {
sig.sigClass = CLASS_RFI;
sig.reason = RECENT_RFI_MATCH;
Debug(DEBUG_SIGNAL_CLASS, (void *) recentRfi, "yep");
} else
Debug(DEBUG_SIGNAL_CLASS, (void *) recentRfi, "nope");
}
}
// test for test signal mask match; this overrides rfi mask
if (operations.test(APPLY_TEST_SIGNAL_MASK) && testSignal) {
if (testSignal->isMasked(sig.path.rfFreq, HZ_TO_MHZ(sig.path.width))) {
sig.sigClass = CLASS_CAND;
sig.reason = TEST_SIGNAL_MATCH;
}
}
// test for followup candidates; the signal must already
// be a candidate;
if (operations.test(FOLLOW_UP_CANDIDATES)) {
Signal *signal = findFollowupSignal(act, sig);
if (signal) {
sig.origSignalId = signal->getOrigSignalId();
if (sig.sigClass == CLASS_CAND)
act->removeFollowupSignal(signal);
else {
// preserve the class/reason information for the
// candidate
signal->setClass(sig.sigClass);
signal->setReason(sig.reason);
}
}
else {
sig.sigClass = CLASS_UNKNOWN;
sig.reason = PASSED_POWER_THRESH;
}
}
// if we are not selecting candidates, or we have exceeded
// the maximum number of candidates, mark any candidate signal as
// class unknown
if (!operations.test(CANDIDATE_SELECTION))
sig.sigClass = CLASS_UNKNOWN;
else if (sig.path.rfFreq < act->getChannel()->getLowFreq()
|| sig.path.rfFreq >= act->getChannel()->getHighFreq()) {
sig.sigClass = CLASS_UNKNOWN;
sig.reason = SIGNAL_NOT_IN_CHANNEL;
}
else if (sig.sigClass == CLASS_CAND
&& act->getCandidateCount(ANY_TYPE) >= maxCandidates) {
++candidatesOverMax;
sig.sigClass = CLASS_UNKNOWN;
sig.reason = TOO_MANY_CANDIDATES;
}
Debug(DEBUG_SIGNAL_CLASS, sig.signalId.number, "sig.signalId.number");
Debug(DEBUG_SIGNAL_CLASS, sig.sigClass, "sig.sigClass");
Debug(DEBUG_SIGNAL_CLASS, sig.reason, "sig.reason");
}
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
#if !defined(PM_RUNTIME_SUPPORT)
IMG_INT res;
long lRate,lNewRate;
#endif
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
{
return PVRSRV_OK;
}
#if !defined(PM_RUNTIME_SUPPORT)
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
res=clk_enable(psSysSpecData->psSGX_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ);
if (lNewRate <= 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate"));
return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE;
}
lRate = clk_get_rate(psSysSpecData->psSGX_FCK);
if (lRate != lNewRate)
{
res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate);
if (res < 0)
{
PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res));
return PVRSRV_ERROR_UNABLE_TO_SET_CLOCK_RATE;
}
}
#if defined(DEBUG)
{
IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
}
#endif
#endif
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
#if defined(PM_RUNTIME_SUPPORT)
{
int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
}
#endif
#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
return PVRSRV_OK;
}
/*
* display_pci
* Display all the PCI IO cards on this board.
*/
void
display_pci(Board_node *board)
{
struct io_card *card_list = NULL;
struct io_card card;
void *value;
Prom_node *pci;
Prom_node *card_node;
Prom_node *pci_bridge_node = NULL;
char *slot_name_arr[MAX_SLOTS_PER_IO_BD] = {NULL};
char *slot_name = NULL;
int slot_name_bits;
int slot_name_offset = 0;
char *child_name;
char *name, *type;
char buf[MAXSTRLEN];
int *int_val;
int pci_bus;
int pci_bridge = 0;
int pci_bridge_dev_no;
int child_dev_no;
int i;
int portid;
int version, *pversion;
if (board == NULL)
return;
/* Initialize all the common information */
card.display = TRUE;
card.board = board->board_num;
card.node_id = board->node_id;
/*
* Search for each schizo, then find/display all nodes under
* each schizo node found. Since the model property "SUNW,schizo"
* is not supported on Starcat, we must match on the compatible
* property "pci108e,8001".
*/
for (pci = dev_find_node_by_compatible(board->nodes, SCHIZO_COMPATIBLE);
pci != NULL;
pci = dev_next_node_by_compatible(pci, SCHIZO_COMPATIBLE)) {
/* set max freq for this board */
board_bus_max_freq = DEFAULT_MAX_FREQ;
/*
* Find out if this is a PCI or cPCI IO Board.
* If "enum-impl" property exists in pci node => cPCI.
*/
value = get_prop_val(find_prop(pci, "enum-impl"));
if (value == NULL) {
(void) sprintf(card.bus_type, "PCI");
} else {
(void) sprintf(card.bus_type, "cPCI");
}
if (strstr((char *)get_prop_val(
find_prop(pci, "compatible")), XMITS_COMPATIBLE)) {
sprintf(card.notes, "%s", XMITS_COMPATIBLE);
/*
* With XMITS 3.X and PCI-X mode, the bus speed
* can be higher than 66MHZ.
*/
value = (int *)get_prop_val
(find_prop(pci, "module-revision#"));
if (value) {
pversion = (int *)value;
version = *pversion;
if (version >= 4)
board_bus_max_freq = PCIX_MAX_FREQ;
}
} else if (strstr((char *)get_prop_val(
find_prop(pci, "compatible")), SCHIZO_COMPATIBLE))
sprintf(card.notes, "%s", SCHIZO_COMPATIBLE);
else
sprintf(card.notes, " ");
/*
* Get slot-names property from parent node and
* store the individual slot names in an array.
* This is more general than Starcat requires, but
* it is correct, according to the slot-names property.
*/
value = (char *)get_prop_val(find_prop(pci, "slot-names"));
if (value == NULL) {
/*
* No slot_names property. This could be an Xmits
* card, so check the child node for slot-names property
*/
value = (char *)get_prop_val(
find_prop(pci->child, "slot-names"));
}
if (value != NULL) {
/* Get the 4 byte bitmask and pointer to first name */
slot_name_bits = *(int *)value;
if (slot_name_bits > 0)
slot_name_offset = slot_name_bits - 1;
slot_name = (char *)value + sizeof (int);
for (i = 0; i < MAX_SLOTS_PER_IO_BD; i++) {
if (! (slot_name_bits & (1 << i))) {
slot_name_arr[i] = (char *)NULL;
continue;
}
/*
* Save the name pointer into the array
* and advance it past the end of this
* slot name
*/
slot_name_arr[i] = slot_name;
slot_name += strlen(slot_name) + 1;
}
slot_name = (char *)NULL;
}
/*
* Search for Children of this node ie. Cards.
* Note: any of these cards can be a pci-bridge
* that itself has children. If we find a
* pci-bridge we need to handle it specially.
*/
card_node = pci->child;
while (card_node != NULL) {
pci_bridge = 0;
/* If it doesn't have a name, skip it */
name = (char *)get_prop_val(
find_prop(card_node, "name"));
if (name == NULL) {
card_node = card_node->sibling;
continue;
}
/*
* get dev# and func# for this card from the
* 'reg' property.
*/
int_val = (int *)get_prop_val(
find_prop(card_node, "reg"));
if (int_val != NULL) {
card.dev_no = (((*int_val) & 0xF800) >> 11);
card.func_no = (((*int_val) & 0x700) >> 8);
} else {
card.dev_no = -1;
card.func_no = -1;
}
/*
* If this is a pci-bridge, then store it's dev#
* as its children nodes need this to get their slot#.
* We set the pci_bridge flag so that we know we are
* looking at a pci-bridge node. This flag gets reset
* every time we enter this while loop.
*/
/*
* Check for a PCI-PCI Bridge for PCI and cPCI
* IO Boards using the name and type properties.
*/
type = (char *)get_prop_val(
find_prop(card_node, "device_type"));
if ((type != NULL) &&
(strncmp(name, "pci", 3) == 0) &&
(strcmp(type, "pci") == 0)) {
pci_bridge_dev_no = card.dev_no;
pci_bridge_node = card_node;
pci_bridge = TRUE;
}
/*
* Get slot-names property from slot_names_arr.
* If we are the child of a pci_bridge we use the
* dev# of the pci_bridge as an index to get
* the slot number. We know that we are a child of
* a pci-bridge if our parent is the same as the last
* pci_bridge node found above.
*/
if (card.dev_no != -1) {
/*
* We compare this card's parent node with the
* pci_bridge_node to see if it's a child.
*/
if (card_node->parent == pci_bridge_node) {
/* use dev_no of pci_bridge */
child_dev_no = pci_bridge_dev_no - 1;
} else {
/* use card's own dev_no */
child_dev_no = card.dev_no - 1;
}
if (child_dev_no < MAX_SLOTS_PER_IO_BD &&
child_dev_no >= 0 &&
slot_name_arr
[child_dev_no + slot_name_offset] != NULL) {
slot_name = slot_name_arr[
child_dev_no + slot_name_offset];
} else
slot_name = (char *)NULL;
if (slot_name != NULL && slot_name[0] != '\0') {
(void) sprintf(card.slot_str, "%s",
slot_name);
} else {
(void) sprintf(card.slot_str, "-");
}
} else {
(void) sprintf(card.slot_str, "%c", '-');
}
/*
* Get the portid of the schizo that this card
* lives under.
*/
portid = -1;
value = get_prop_val(find_prop(pci, "portid"));
if (value != NULL) {
portid = *(int *)value;
}
card.schizo_portid = portid;
#ifdef DEBUG
(void) sprintf(card.notes, "%s portid [%d]"
" dev_no [%d] slot_name[%s] name_bits[%#x]",
card.notes, portid, card.dev_no,
((slot_name != NULL) ? slot_name : "NULL"),
slot_name_bits);
#endif /* DEBUG */
/*
* Find out whether this is PCI bus A or B
* using the 'reg' property.
*/
int_val = (int *)get_prop_val
(find_prop(pci, "reg"));
if (int_val != NULL) {
int_val ++; /* skip over first integer */
pci_bus = ((*int_val) & 0x7f0000);
if (pci_bus == 0x600000)
card.pci_bus = 'A';
else if (pci_bus == 0x700000)
card.pci_bus = 'B';
else
card.pci_bus = '-';
} else {
card.pci_bus = '-';
}
/*
* Check for failed status.
*/
if (node_failed(card_node))
strcpy(card.status, "fail");
else
strcpy(card.status, "ok");
/* Get the model of this card */
value = get_prop_val(find_prop(card_node, "model"));
if (value == NULL)
card.model[0] = '\0';
else {
(void) sprintf(card.model, "%s", (char *)value);
/*
* If we wish to exclude onboard devices
* (such as SBBC) then this is the place
* and here is how to do it:
*
* if (strcmp(card.model, "SUNW,sbbc") == 0) {
* card_node = card_node->sibling;
* continue;
* }
*/
}
/*
* The card may have a "clock-frequency" but we
* are not interested in that. Instead we get the
* "clock-frequency" of the PCI Bus that the card
* resides on. PCI-A can operate at 33Mhz or 66Mhz
* depending on what card is plugged into the Bus.
* PCI-B always operates at 33Mhz.
*
*/
int_val = get_prop_val(find_prop(pci,
"clock-frequency"));
if (int_val != NULL) {
card.freq = HZ_TO_MHZ(*int_val);
} else {
card.freq = -1;
}
/*
* Figure out how we want to display the name
*/
value = get_prop_val(find_prop(card_node,
"compatible"));
if (value != NULL) {
/* use 'name'-'compatible' */
(void) sprintf(buf, "%s-%s", name,
(char *)value);
} else {
/* just use 'name' */
(void) sprintf(buf, "%s", name);
}
name = buf;
/*
* If this node has children, add the device_type
* of the child to the name value of this card.
*/
child_name = (char *)get_node_name(card_node->child);
if ((card_node->child != NULL) &&
(child_name != NULL)) {
value = get_prop_val(find_prop(card_node->child,
"device_type"));
if (value != NULL) {
/* add device_type of child to name */
(void) sprintf(card.name, "%s/%s (%s)",
name, child_name,
(char *)value);
} else {
/* just add child's name */
(void) sprintf(card.name, "%s/%s",
name, child_name);
}
} else {
/* childless, just the card's name */
(void) sprintf(card.name, "%s", (char *)name);
}
/*
* If this is a pci-bridge, then add the word
* 'pci-bridge' to its model.
*/
if (pci_bridge) {
if (card.model[0] == '\0')
(void) sprintf(card.model,
"%s", "pci-bridge");
else
(void) strcat(card.model,
"/pci-bridge");
}
/* insert this card in the list to be displayed later */
card_list = insert_io_card(card_list, &card);
/*
* If we are dealing with a pci-bridge, we need to move
* down to the children of this bridge, if there are
* any, otherwise its siblings.
*
* If not a bridge, we are either dealing with a regular
* card (in which case we move onto the sibling of this
* card) or we are dealing with a child of a pci-bridge
* (in which case we move onto the child's siblings or
* if there are no more siblings for this child, we
* move onto the parent's siblings). I hope you're
* getting all this, there will be an exam later.
*/
if (pci_bridge) {
if (card_node->child != NULL)
card_node = card_node->child;
else
card_node = card_node->sibling;
} else {
/*
* If our parent is a pci-bridge but there
* are no more of its children to process we
* move back up to our parent's sibling,
* otherwise we move onto our own sibling.
*/
if ((card_node->parent == pci_bridge_node) &&
(card_node->sibling == NULL))
card_node =
pci_bridge_node->sibling;
else
card_node = card_node->sibling;
}
} /* end while (card_node ...) loop */
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
struct clk *psCLK;
IMG_INT res;
PVRSRV_ERROR eError;
IMG_BOOL bPowerLock;
#if defined(DEBUG) || defined(TIMING)
IMG_INT rate;
struct clk *sys_ck;
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#endif
PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
if (!psSysSpecData->bSysClocksOneTimeInit)
{
bPowerLock = IMG_FALSE;
spin_lock_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sPowerLockCPU, -1);
spin_lock_init(&psSysSpecData->sNotifyLock);
atomic_set(&psSysSpecData->sNotifyLockCPU, -1);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
psCLK = clk_get(NULL, "sgx_ck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock"));
goto ExitError;
}
psSysSpecData->psSGX_FCK = psCLK;
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
}
else
{
bPowerLock = PowerLockWrappedOnCPU(psSysSpecData);
if (bPowerLock)
{
PowerLockUnwrap(psSysSpecData);
}
}
#if defined(CONSTRAINT_NOTIFICATIONS)
psSysSpecData->pVdd2Handle = constraint_get(PVRSRV_MODNAME, &cnstr_id_vdd2);
if (IS_ERR(psSysSpecData->pVdd2Handle))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get VDD2 constraint handle"));
goto ExitError;
}
RegisterConstraintNotifications();
#endif
#if defined(DEBUG) || defined(TIMING)
if(cpu_is_ti816x()) {
psCLK = clk_get(NULL, "gpt6_fck");
} else {
psCLK = clk_get(NULL, "gpt7_fck");
}
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_FCK = psCLK;
if(cpu_is_ti816x()) {
psCLK = clk_get(NULL, "gpt6_ick");
} else {
psCLK = clk_get(NULL, "gpt7_ick");
}
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_ICK = psCLK;
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
rate = *pui32TimerEnable;
if(!(rate & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable = rate | 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#endif
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
PVR_TRACE(("EnableSystemClocks: Setting SGX OPP constraint"));
res = constraint_set(psSysSpecData->pVdd2Handle, max_vdd2_opp);
if (res != 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: constraint_set failed (%d)", res));
goto ExitConstraintSetFailed;
}
#endif
eError = PVRSRV_OK;
goto Exit;
#if defined(PDUMP) && !defined(NO_HARDWARE) && defined(CONSTRAINT_NOTIFICATIONS)
ExitConstraintSetFailed:
#endif
#if defined(DEBUG) || defined(TIMING)
ExitDisableGPT11ICK:
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitUnRegisterConstraintNotifications:
#endif
#if defined(CONSTRAINT_NOTIFICATIONS)
UnRegisterConstraintNotifications();
constraint_put(psSysSpecData->pVdd2Handle);
#endif
Exit:
if (bPowerLock)
{
PowerLockWrap(psSysSpecData);
}
ExitError:
eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE;
return eError;
}
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
#if defined(PVR_OMAP3_TIMING_PRCM)
struct clk *psCLK;
IMG_INT res;
struct clk *sys_ck;
IMG_INT rate;
#endif
PVRSRV_ERROR eError;
IMG_CPU_PHYADDR sTimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0);
#endif
#if defined(PVR_OMAP3_TIMING_PRCM)
psCLK = clk_get(NULL, "gpt7_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitError;
}
psSysSpecData->psGPT11_FCK = psCLK;
psCLK = clk_get(NULL, "gpt7_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitError;
}
psSysSpecData->psGPT11_ICK = psCLK;
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitError;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
#endif
sTimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
if(!(*pui32TimerEnable & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable |= 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
sTimerRegPhysBase.uiAddr = SYS_TI335x_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA)
psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase;
#endif
eError = PVRSRV_OK;
goto Exit;
ExitDisableGPT11ICK:
#if defined(PVR_OMAP3_TIMING_PRCM)
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitError:
#endif
eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
Exit:
return eError;
}
/*!
******************************************************************************
@Function EnableSGXClocks
@Description Enable SGX clocks
@Return PVRSRV_ERROR
******************************************************************************/
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
#if !defined(PM_RUNTIME_SUPPORT)
IMG_INT res;
long lRate,lNewRate;
#endif
/* SGX clocks already enabled? */
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
{
return PVRSRV_OK;
}
#if !defined(PM_RUNTIME_SUPPORT)
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
res=clk_enable(psSysSpecData->psSGX_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ);
if (lNewRate <= 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate"));
return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE;
}
lRate = clk_get_rate(psSysSpecData->psSGX_FCK);
if (lRate != lNewRate)
{
res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate);
if (res < 0)
{
PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res));
return PVRSRV_ERROR_UNABLE_TO_SET_CLOCK_RATE;
}
}
#if defined(DEBUG)
{
IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
}
#endif
#endif
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
#if defined(SYS_OMAP_HAS_DVFS_FRAMEWORK)
{
struct gpu_platform_data *pdata;
IMG_UINT32 max_freq_index;
int res;
pdata = (struct gpu_platform_data *)gpsPVRLDMDev->dev.platform_data;
max_freq_index = psSysSpecData->ui32SGXFreqListSize - 2;
/*
* Request maximum frequency from DVFS layer if not already set. DVFS may
* report busy if early in initialization, but all other errors are
* considered serious. Upon any error we proceed assuming our safe frequency
* value to be in use as indicated by the "unknown" index.
*/
if (psSysSpecData->ui32SGXFreqListIndex != max_freq_index)
{
PVR_ASSERT(pdata->device_scale != IMG_NULL);
res = pdata->device_scale(&gpsPVRLDMDev->dev,
#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,4,0))
&gpsPVRLDMDev->dev,
#endif
psSysSpecData->pui32SGXFreqList[max_freq_index]);
if (res == 0)
{
psSysSpecData->ui32SGXFreqListIndex = max_freq_index;
}
else if (res == -EBUSY)
{
PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Unable to scale SGX frequency (EBUSY)"));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
else if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Unable to scale SGX frequency (%d)", res));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
}
}
#endif /* defined(SYS_OMAP_HAS_DVFS_FRAMEWORK) */
{
/*
* pm_runtime_get_sync returns 1 after the module has
* been reloaded.
*/
#if defined(PM_RUNTIME_SUPPORT)
int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
#endif
}
#endif /* defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) */
SysEnableSGXInterrupts(psSysData);
/* Indicate that the SGX clocks are enabled */
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
#else /* !defined(NO_HARDWARE) */
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif /* !defined(NO_HARDWARE) */
return PVRSRV_OK;
}
/*!
******************************************************************************
@Function AcquireGPTimer
@Description Acquire a GP timer
@Return PVRSRV_ERROR
******************************************************************************/
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData)
{
#if defined(PVR_OMAP4_TIMING_PRCM)
struct clk *psCLK;
IMG_INT res;
struct clk *sys_ck;
IMG_INT rate;
#endif
PVRSRV_ERROR eError;
IMG_CPU_PHYADDR sTimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0);
psCLK = clk_get(NULL, "sgx_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
return;
}
clk_enable(psCLK);
psCLK = clk_get(NULL, "sgx_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
return;
}
clk_enable(psCLK);
#if defined(PVR_OMAP4_TIMING_PRCM)
psCLK = clk_get(NULL, "gpt6_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitError;
}
psSysSpecData->psGPT11_FCK = psCLK;
psCLK = clk_get(NULL, "gpt6_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitError;
}
psSysSpecData->psGPT11_ICK = psCLK;
sys_ck = clk_get(NULL, "sys_ck");
if (IS_ERR(sys_ck))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock"));
goto ExitError;
}
if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck)
{
PVR_TRACE(("Setting GPTIMER11 parent to System Clock"));
res = clk_set_parent(psSysSpecData->psGPT11_FCK, sys_ck);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res));
goto ExitError;
}
}
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitError;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
#endif /* defined(PVR_OMAP4_TIMING_PRCM) */
/* Set the timer to non-posted mode */
sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
if(!(*pui32TimerEnable & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
/* Set posted mode */
*pui32TimerEnable |= 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
/* Enable the timer */
sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
/* Enable and set autoreload on overflow */
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase;
eError = PVRSRV_OK;
goto Exit;
ExitDisableGPT11ICK:
#if defined(PVR_OMAP4_TIMING_PRCM)
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitError:
#endif /* defined(PVR_OMAP4_TIMING_PRCM) */
eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED;
Exit:
return eError;
}
void
display_cpus(Board_node *board)
{
Prom_node *cpu;
uint_t freq;
int ecache_size;
int *l3_shares;
int *mid;
int *impl;
int *mask;
int *coreid;
char fru_prev = 'X'; /* Valid frus are 'A','B' */
int mid_prev;
int ecache_size_prev = 0;
char fru_name;
/*
* display the CPUs' operating frequency, cache size, impl. field
* and mask revision.
*/
for (cpu = dev_find_type(board->nodes, "cpu"); cpu != NULL;
cpu = dev_next_type(cpu, "cpu")) {
mid = (int *)get_prop_val(find_prop(cpu, "portid"));
if (mid == NULL)
mid = (int *)get_prop_val(find_prop(cpu, "cpuid"));
freq = HZ_TO_MHZ(get_cpu_freq(cpu));
ecache_size = get_ecache_size(cpu);
impl = (int *)get_prop_val(find_prop(cpu, "implementation#"));
mask = (int *)get_prop_val(find_prop(cpu, "mask#"));
l3_shares =
(int *)get_prop_val(find_prop(cpu, "l3-cache-sharing"));
/* Do not display a failed CPU node */
if ((impl == NULL) || (freq == 0) || (node_failed(cpu)))
continue;
fru_name = CHERRYSTONE_GETSLOT_LABEL(*mid);
if (CPU_IMPL_IS_CMP(*impl)) {
coreid = (int *)get_prop_val(find_prop(cpu, "reg"));
if (coreid == NULL) {
continue;
}
if ((fru_prev == 'X') ||
((fru_prev != 'X') &&
(fru_name != fru_prev))) {
fru_prev = fru_name;
mid_prev = *mid;
ecache_size_prev = ecache_size;
continue;
} else {
/*
* Some CMP chips have a split E$,
* so the size for both cores is added
* together to get the total size for
* the chip.
*
* Still, other CMP chips have E$ (L3)
* which is logically shared, so the
* total size is equal to the core size.
*/
if ((l3_shares == NULL) ||
((l3_shares != NULL) &&
MULTIPLE_BITS_SET(*l3_shares))) {
ecache_size += ecache_size_prev;
}
ecache_size_prev = 0;
fru_prev = 'X';
}
}
log_printf(" %c", fru_name);
/* CPU Module ID */
if (CPU_IMPL_IS_CMP(*impl)) {
log_printf("%3d,%3d ", mid_prev, *mid, 0);
} else
log_printf(" %2d ", *mid);
/* Running frequency */
log_printf("%4u", freq);
if (ecache_size == 0)
log_printf(" N/A ");
else
log_printf(" %4.1f ",
(float)ecache_size / (float)(1<<20));
/* Implementation */
if (impl == NULL) {
log_printf(dgettext(TEXT_DOMAIN, " N/A "));
} else {
if (IS_CHEETAH(*impl))
log_printf(dgettext(TEXT_DOMAIN,
"US-III "));
else if (IS_CHEETAH_PLUS(*impl))
log_printf(dgettext(TEXT_DOMAIN,
"US-III+ "));
else if (IS_JAGUAR(*impl))
log_printf(dgettext(TEXT_DOMAIN,
"US-IV "));
else if (IS_PANTHER(*impl))
log_printf(dgettext(TEXT_DOMAIN,
"US-IV+ "));
else
log_printf("%-6x ", *impl);
}
/* CPU Mask */
if (mask == NULL) {
log_printf(dgettext(TEXT_DOMAIN, " N/A\n"));
} else {
log_printf(dgettext(TEXT_DOMAIN, " %d.%d\n"),
(*mask >> 4) & 0xf, *mask & 0xf);
}
}
}
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
struct clk *psCLK;
IMG_INT res;
PVRSRV_ERROR eError;
#if defined(DEBUG) || defined(TIMING)
IMG_INT rate;
struct clk *sys_ck;
IMG_CPU_PHYADDR TimerRegPhysBase;
IMG_HANDLE hTimerEnable;
IMG_UINT32 *pui32TimerEnable;
#endif
PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
if (!psSysSpecData->bSysClocksOneTimeInit)
{
mutex_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
psCLK = clk_get(NULL, SGX_PARENT_CLOCK);
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get Core Clock"));
goto ExitError;
}
psSysSpecData->psCORE_CK = psCLK;
psCLK = clk_get(NULL, "sgx_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock"));
goto ExitError;
}
psSysSpecData->psSGX_FCK = psCLK;
psCLK = clk_get(NULL, "sgx_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
goto ExitError;
}
psSysSpecData->psSGX_ICK = psCLK;
#if defined(DEBUG)
psCLK = clk_get(NULL, "mpu_ck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get MPU Clock"));
goto ExitError;
}
psSysSpecData->psMPU_CK = psCLK;
#endif
res = clk_set_parent(psSysSpecData->psSGX_FCK, psSysSpecData->psCORE_CK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set SGX parent clock (%d)", res));
goto ExitError;
}
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
}
#if defined(DEBUG) || defined(TIMING)
psCLK = clk_get(NULL, "gpt11_fck");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_FCK = psCLK;
psCLK = clk_get(NULL, "gpt11_ick");
if (IS_ERR(psCLK))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
goto ExitUnRegisterConstraintNotifications;
}
psSysSpecData->psGPT11_ICK = psCLK;
sys_ck = clk_get(NULL, "sys_ck");
if (IS_ERR(sys_ck))
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock"));
goto ExitUnRegisterConstraintNotifications;
}
if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck)
{
PVR_TRACE(("Setting GPTIMER11 parent to System Clock"));
res = clk_set_parent(psSysSpecData->psGPT11_FCK, sys_ck);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
}
rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
res = clk_enable(psSysSpecData->psGPT11_FCK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
goto ExitUnRegisterConstraintNotifications;
}
res = clk_enable(psSysSpecData->psGPT11_ICK);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
goto ExitDisableGPT11FCK;
}
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_TSICR_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
rate = *pui32TimerEnable;
if(!(rate & 4))
{
PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
*pui32TimerEnable = rate | 4;
}
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
TimerRegPhysBase.uiAddr = SYS_TI81xx_GP7TIMER_ENABLE_SYS_PHYS_BASE;
pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
&hTimerEnable);
if (pui32TimerEnable == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
goto ExitDisableGPT11ICK;
}
*pui32TimerEnable = 3;
OSUnMapPhysToLin(pui32TimerEnable,
4,
PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
hTimerEnable);
#endif
eError = PVRSRV_OK;
goto Exit;
#if defined(DEBUG) || defined(TIMING)
ExitDisableGPT11ICK:
clk_disable(psSysSpecData->psGPT11_ICK);
ExitDisableGPT11FCK:
clk_disable(psSysSpecData->psGPT11_FCK);
ExitUnRegisterConstraintNotifications:
#endif
ExitError:
eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE;
Exit:
return eError;
}
//
// startActivity: start the next signal detection
//
// Synopsis:
// void startActivity(msg);
// Msg *msg; ptr to message
// Returns:
// Nothing.
// Description:
// Starts signal detection.
// Notes:
// All activity information has been stored in the
// Activity structure assigned to this activity.
//
void
DetectionTask::startActivity(Msg *msg)
{
Debug(DEBUG_DETECT, 0, "");
const SseInterfaceHeader& hdr = msg->getHeader();
// the activity must exist and be DX_ACT_PEND_SD
Activity *act;
if (!(act = state->findActivity(hdr.activityId))) {
LogError(ERR_NSA, msg->getActivityId(), "activity %d",
msg->getActivityId());
return;
}
else if (act->getState() != DX_ACT_PEND_SD) {
LogError(ERR_ANS, act->getActivityId(), "activity %d, state %d",
act->getActivityId(), act->getState());
return;
}
// record the activity and get the activity parameters
activity = act;
params = activity->getActivityParams();
// clear the hit list and set the activity parameters
SuperClusterer *superClusterer = activity->getSuperClusterer();
Assert(superClusterer);
Assert(!superClusterer->getCount());
// compute the bottom edge of the frequency range, which is 1/2
// subchannel below the middle of subchannel 0
float64_t chanWidth = activity->getChannelWidthMHz();
float64_t deltaFreq = -chanWidth / 2;
deltaFreq -= activity->getSubchannelWidthMHz() / 2;
// initialize the signal ID for this activity
NssDate startTime = activity->getActualStartTime();
SignalIdGenerator sigGen(state->getSerialNumber(), params.activityId,
startTime);
/////////////////////////////////////////////////////////////////////
// NOTE: this code will have to be modified when we run multiple
// pulse resolutions, because there is only one resolution specified
// to the SuperClusterer.
/////////////////////////////////////////////////////////////////////
int32_t spectra = activity->getSpectra(params.daddResolution);
float64_t binWidth = activity->getBinWidthHz(params.daddResolution);
superClusterer->setObsParams(params.activityId, spectra,
params.dxSkyFreq + deltaFreq, chanWidth, binWidth, sigGen);
superClusterer->setSuperClusterGap(HZ_TO_MHZ(params.clusteringFreqTolerance));
// send a message to the control task indicating that signal detection
// has started
Msg *cMsg = msgList->alloc(SIGNAL_DETECTION_STARTED, hdr.activityId);
controlQ->send(cMsg);
Debug(DEBUG_DETECT, hdr.activityId, "starting CWD");
// do CW detection first, if it's enabled, otherwise start
// pulse detection
startCwDetection();
}
