//----------------------------------------------------------------------------
int HostPCIe_MDIOWrite(int argc, char* argv[])
{
if(argc<2)
{
dprintf("mdiow <addr> <val> \n");
dprintf("ex: mdiow 00 ffff \n");
return;
}
unsigned int addr = strtoul((const char*)(argv[0]), (char **)NULL, 16);
unsigned int val = strtoul((const char*)(argv[1]), (char **)NULL, 16);
/*
REG32(PCIE0_MDIO)= (addr<<PCIE_MDIO_REG_OFFSET) | (val<<PCIE_MDIO_DATA_OFFSET) | (1<<PCIE_MDIO_RDWR_OFFSET) ; ;
*/
HostPCIe_SetPhyMdioWrite(addr, val);
};
void PCIE_reset_procedure(int PCIE_Port0and1_8196B_208pin, int Use_External_PCIE_CLK, int mdio_reset)
{
#define SYS_PCIE_PHY0 (0xb8000000 +0x50)
//PCIE Register
#define CLK_MANAGE 0xb8000010
#define PCIE_PHY0_REG 0xb8b01000
//#define PCIE_PHY1_REG 0xb8b21000
#define PCIE_PHY0 0xb8b01008
// #define PCIE_PHY1 0xb8b21008
//JSW:PCIE reset procedure
#if 0
//1. "Enable internal PCIE PLL
//#if Use_External_PCIE_CLK
if(Use_External_PCIE_CLK)
REG32(PIE_PLL) = 0x358; //Use External PCIE CLK (clock chip)
//#else
else
REG32(PCIE_PLL) = 0x9; //Use Internal PCIE CLK and PCIE fine-tune
//#endif
//prom_printf("\nPCIE_PLL(0x%x)=0x%x\n",PCIE_PLL,READ_MEM32(PCIE_PLL));
mdelay(100);//mdelay(10);
#endif
//2.Active LX & PCIE Clock
REG32(CLK_MANAGE) |= (1<<11); //enable active_pcie0
mdelay(100);
#if 1
if(mdio_reset)
{
printk("Do MDIO_RESET\n");
// 3.MDIO Reset
REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (0<<0); //mdio reset=0,
REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (1<<0); //mdio reset=1,
REG32(SYS_PCIE_PHY0) = (1<<3) |(1<<1) | (1<<0); //bit1 load_done=1
}
//4. PCIE PHY Reset
REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
mdelay(100);
#endif
mdelay(100);
#if 0
//#if Use_External_PCIE_CLK
if(Use_External_PCIE_CLK)
{
//5. PCIE P0 PHY external clock
mdelay(100);
REG32(PCIE_PHY0_REG) = 0xC3930301; //bit[3] must be "0" for external clock
//REG32(PCIE_PHY0_REG) = 0xC39B0301; //20090304:RDC for for PCIE port 0 Refine-tune
mdelay(100);
REG32(PCIE_PHY0_REG) = 0x3c011901; //close PHY 0 ,"0"=R,"1"=W
mdelay(100);
}
//#endif
#endif
//----------------------------------------
if(mdio_reset)
{
//fix 8196C test chip pcie tx problem.
/*
HostPCIe_SetPhyMdioWrite( 8, HostPCIe_SetPhyMdioRead(8) | (1<<3) );
HostPCIe_SetPhyMdioWrite(0x0d, HostPCIe_SetPhyMdioRead(0x0d) | (5<<5) );
HostPCIe_SetPhyMdioWrite(0x0d, HostPCIe_SetPhyMdioRead(0x0d) | (1<<4) );
HostPCIe_SetPhyMdioWrite(0x0f, HostPCIe_SetPhyMdioRead(0x0f) & ~(1<<4));
HostPCIe_SetPhyMdioWrite(0x06, HostPCIe_SetPhyMdioRead(0x06) | (1<<11) );
*/
HostPCIe_SetPhyMdioWrite(0, 0x5027);
HostPCIe_SetPhyMdioWrite(2, 0x6d18);
HostPCIe_SetPhyMdioWrite(6, 0x8828);
HostPCIe_SetPhyMdioWrite(7, 0x30ff);
HostPCIe_SetPhyMdioWrite(8, 0x18d7);
HostPCIe_SetPhyMdioWrite(0xa, 0xe9);
HostPCIe_SetPhyMdioWrite(0xb, 0x0511);
HostPCIe_SetPhyMdioWrite(0xd, 0x15b6);
HostPCIe_SetPhyMdioWrite(0xf, 0x0f0f);
#if 1 // PHY_EAT_40MHZ
HostPCIe_SetPhyMdioWrite(5, 0xbcb); //[9:3]=1111001 (binary) 121 (10)
HostPCIe_SetPhyMdioWrite(6, 0x8128); //[11]=0 [9:8]=01
#endif
/*
emdiow 0 5027
emdiow 2 6d18
emdiow 6 8828
emdiow 7 30ff
emdiow 8 18dd
emdiow a e9
emdiow b 0511
emdiow d 15b6
emdiow f 0f0f
*/
}
//---------------------------------------
// 6. PCIE Device Reset
REG32(CLK_MANAGE) &= ~(1<<12); //perst=0 off.
mdelay(100);
mdelay(100);
mdelay(100);
REG32(CLK_MANAGE) |= (1<<12); //PERST=1
//prom_printf("\nCLK_MANAGE(0x%x)=0x%x\n\n",CLK_MANAGE,READ_MEM32(CLK_MANAGE));
//4. PCIE PHY Reset
REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
mdelay(100);
mdelay(1000);
#if 1 //wait for LinkUP
int i=100;
while(--i)
{
if( (REG32(0xb8b00728)&0x1f)==0x11)
break;
mdelay(100);
}
if(i==0)
printk("i=%x Cannot LinkUP \n",i);
#endif
printk("devid=%x\n",REG32(0xb8b10000));
}
int PCIE_reset_procedure(int portnum, int Use_External_PCIE_CLK, int mdio_reset)
{
// dprintf("port=%x, mdio_rst=%x \n", portnum, mdio_reset);
int result=0;
//first, Turn On PCIE IP
#define CLK_MANAGE 0xb8000010
if(portnum==0) REG32(CLK_MANAGE) |= (1<<14); //enable active_pcie0
else if(portnum==1) REG32(CLK_MANAGE) |= (1<<16); //enable active_pcie1
else return result;
if (portnum==0)
{
REG32(CLK_MANAGE) |= (1<<26); //PERST=1
}
else if (portnum==1)
{
REG32(0xb8000040)|=0x300;
REG32(PEFGHCNR_REG) &= ~(0x1000); /*port F bit 4 */
REG32(PEFGHDIR_REG) |= (0x1000); /*port F bit 4 */
REG32(PEFGHDAT_REG) |= (0x1000); //PERST=1
}
#if defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E)
REG32(CLK_MANAGE) |= (1<<12)| (1<<13)|(1<<18);
#endif
mdelay(500);
#ifdef CONFIG_RTL8198_REVISION_B
if(portnum==1)
{
#define PAD_CONTROL 0xb8000048
REG32(PAD_CONTROL)|=(1<<27);
}
#endif
if(mdio_reset)
{
if(at2_mode==0) //no auto test, show message
printk("Do MDIO_RESET\n");
mdelay(1);
// 3.MDIO Reset
PCIE_MDIO_Reset(portnum);
}
/*
PCIE_PHY_Reset(portnum);
*/
mdelay(500);
mdelay(500);
//----------------------------------------
if(mdio_reset)
{
//fix 8198 test chip pcie tx problem.
#if defined(CONFIG_RTL8198_REVISION_B) || defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E)
if ((REG32(BSP_REVR) >= BSP_RTL8198_REVISION_B) || ((REG32(BSP_REVR)&0xfffff000) == BSP_RTL8197D) || ((REG32(BSP_REVR) & 0xFFFFF000) == BSP_RTL8196E))
{
#if 1//def RTL8198_FORMALCHIP_A
HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); //bokai tell, and fix
HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003);
HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18);
#ifdef CONFIG_PHY_EAT_40MHZ
HostPCIe_SetPhyMdioWrite(portnum, 5, 0x0BCB); //40M
#endif
#ifdef CONFIG_PHY_EAT_40MHZ
HostPCIe_SetPhyMdioWrite(portnum, 6, 0xF148); //40M
#else
HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf848); //25M
#endif
HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff);
HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d5); //peisi tune
#if 0 //old,
HostPCIe_SetPhyMdioWrite(portnum, 9, 0x531c);
HostPCIe_SetPhyMdioWrite(portnum, 0xd, 0x1766); //peisi tune
#else //saving more power, 8196c pe-si tune
HostPCIe_SetPhyMdioWrite(portnum, 0x09, 0x539c);
HostPCIe_SetPhyMdioWrite(portnum, 0x0a, 0x20eb);
HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1766);
#endif
#if defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E)
HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0711); //for sloving low performance
#else
HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0511); //for sloving low performance
#endif
HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00);
HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0);
HostPCIe_SetPhyMdioWrite(portnum, 0x1a, 0x7e4f); //formal chip, reg 0x1a.4=0
HostPCIe_SetPhyMdioWrite(portnum, 0x1b, 0xFC01); //formal chip reg 0x1b.0=1
HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280);
#endif
}
else
#endif
{
//#define PHY_USE_TEST_CHIP 1 // 1: test chip, 0: fib chip
//#define PHY_EAT_40MHZ 0 // 0: 25MHz, 1: 40MHz
//HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD187);//ori
HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087);
HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003);
//HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18);
HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf448); //new
HostPCIe_SetPhyMdioWrite(portnum, 6, 0x408); //avoid noise infuse //15-12=0, 7-5=0, 0448
HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff);
HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d5); //new
HostPCIe_SetPhyMdioWrite(portnum, 9, 0x531c);
//HostPCIe_SetPhyMdioWrite(portnum, 0xa, 0x00C9);
//HostPCIe_SetPhyMdioWrite(portnum, 0xb, 0xe511);
//HostPCIe_SetPhyMdioWrite(portnum, 0xc, 0x0820);
HostPCIe_SetPhyMdioWrite(portnum, 0xd, 0x1766);
HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0010);//ori
// HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00);
HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0);
HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280);
#if 0 //saving more power
HostPCIe_SetPhyMdioWrite(0xa, 0xeb);
HostPCIe_SetPhyMdioWrite(0x9, 0x538c);
// HostPCIe_SetPhyMdioWrite(0xc, 0xC828); //original
// HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix
HostPCIe_SetPhyMdioWrite(0xc, 0x8828); //new
HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix
#endif
}
}
//---------------------------------------
PCIE_Device_PERST(portnum);
PCIE_PHY_Reset(portnum);
mdelay(500);
mdelay(500);
result=PCIE_Check_Link(portnum);
#if 0
if(portnum==0)
{
if(result)
{
WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) & 0xFFFFFF7F);
mdelay(100);
WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) | 0x00000080);
}
}
else
{
#ifdef PIN_208
if(result)
{
WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) & 0xFFFFFF7F);
mdelay(100);
WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) | 0x00000080);
}
#endif
}
#endif
return result;
}
int OnlyOneReset()
{
int result=0;
int portnum=0;
printk("PCIE RESET Only Once\n");
#define CLK_MANAGE 0xb8000010
#if defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E)
REG32(CLK_MANAGE)|= (1<<12)|(1<<13)|(1<<19)|(1<<20)|(1<<18)|(1<<16);
#endif
REG32(CLK_MANAGE) &= (~(1<<14)); //disable active_pcie0
REG32(CLK_MANAGE) |= (1<<14); //enable active_pcie0
#define PAD_CONTROL 0xb8000048
REG32(PAD_CONTROL)|=(1<<27); //switch to rc
REG32(CLK_MANAGE) &= (~(1<<16)); //disable active_pcie1
REG32(CLK_MANAGE) |= (1<<16); //enable active_pcie1
//PERST=1
//REG32(CLK_MANAGE) |= (1<<26);
//PCIE_Device_PERST(0);
for(portnum=0; portnum<2; portnum++)
PCIE_MDIO_Reset(portnum);
mdelay(500);
for(portnum=0; portnum<2; portnum++)
{
#if 1//def RTL8198_FORMALCHIP_A
HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); //bokai tell, and fix
HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003);
HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18);
#ifdef CONFIG_PHY_EAT_40MHZ
HostPCIe_SetPhyMdioWrite(portnum, 5, 0x0BCB); //40M
#endif
#ifdef CONFIG_PHY_EAT_40MHZ
HostPCIe_SetPhyMdioWrite(portnum, 6, 0xF148); //40M
#else
HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf848); //25M
#endif
HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff);
#if defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E)
HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d6); //peisi tune
#else
HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d7); //peisi tune
#endif
HostPCIe_SetPhyMdioWrite(portnum, 0x09, 0x539c);
HostPCIe_SetPhyMdioWrite(portnum, 0x0a, 0x20eb);
HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1766);
//HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1464); //wei add
HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0511); //for sloving low performance
HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00);
HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0);
HostPCIe_SetPhyMdioWrite(portnum, 0x1a, 0x7e40); //formal chip, reg 0x1a.4=0
HostPCIe_SetPhyMdioWrite(portnum, 0x1b, 0xFC01); //formal chip reg 0x1b.0=1
HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280);
#endif
}
PCIE_Device_PERST(0);
mdelay(500);
for(portnum=0; portnum<2; portnum++)
PCIE_PHY_Reset(portnum);
mdelay(500);
mdelay(500);
mdelay(500);
for(portnum=0; portnum<2; portnum++)
{ result=PCIE_Check_Link(portnum);
if(result!=1)
continue;
#if 1 //wei add patch
//add compatible, slove sata pcie card.
if(portnum==0) REG32(0xb8b0100c)=(1<<3); //set target Device Num=1;
if(portnum==1) REG32(0xb8b2100c)=(2<<3); //set target Device Num=1;
unsigned int rc_cfg, cfgaddr;
unsigned int iomapaddr;
unsigned int memmapaddr;
#define PCIE0_RC_CFG_BASE (0xb8b00000)
#define PCIE0_RC_EXT_BASE (PCIE0_RC_CFG_BASE + 0x1000)
#define PCIE0_EP_CFG_BASE (0xb8b10000)
#define PCIE1_RC_CFG_BASE (0xb8b20000)
#define PCIE1_RC_EXT_BASE (PCIE1_RC_CFG_BASE + 0x1000)
#define PCIE1_EP_CFG_BASE (0xb8b30000)
#define PCIE0_MAP_IO_BASE (0xb8c00000)
#define PCIE0_MAP_MEM_BASE (0xb9000000)
#define PCIE1_MAP_IO_BASE (0xb8e00000)
#define PCIE1_MAP_MEM_BASE (0xba000000)
#define MAX_READ_REQSIZE_128B 0x00
#define MAX_READ_REQSIZE_256B 0x10
#define MAX_READ_REQSIZE_512B 0x20
#define MAX_READ_REQSIZE_1KB 0x30
#define MAX_READ_REQSIZE_2KB 0x40
#define MAX_READ_REQSIZE_4KB 0x50
#define MAX_PAYLOAD_SIZE_128B 0x00
#define MAX_PAYLOAD_SIZE_256B 0x20
#define MAX_PAYLOAD_SIZE_512B 0x40
#define MAX_PAYLOAD_SIZE_1KB 0x60
#define MAX_PAYLOAD_SIZE_2KB 0x80
#define MAX_PAYLOAD_SIZE_4KB 0xA0
if(portnum==0)
{ rc_cfg=PCIE0_RC_CFG_BASE;
cfgaddr=PCIE0_EP_CFG_BASE;
iomapaddr=PCIE0_MAP_IO_BASE;
memmapaddr=PCIE0_MAP_MEM_BASE;
}
else if(portnum==1)
{ rc_cfg=PCIE1_RC_CFG_BASE;
cfgaddr=PCIE1_EP_CFG_BASE;
iomapaddr=PCIE1_MAP_IO_BASE;
memmapaddr=PCIE1_MAP_MEM_BASE;
}
//STATUS
//bit 4: capabilties List
//CMD
//bit 2: Enable Bys master,
//bit 1: enable memmap,
//bit 0: enable iomap
REG32(rc_cfg + 0x04)= 0x00100007;
//Device Control Register
//bit [7-5] payload size
REG32(rc_cfg + 0x78)= (REG32(rc_cfg + 0x78 ) & (~0xE0)) | MAX_PAYLOAD_SIZE_128B; // Set MAX_PAYLOAD_SIZE to 128B,default
REG32(cfgaddr + 0x04)= 0x00100007; //0x00180007
//bit 0: 0:memory, 1 io indicate
//REG32(cfgaddr + 0x10)= (iomapaddr | 0x00000001) & 0x1FFFFFFF; // Set BAR0
//bit 3: prefetch
//bit [2:1] 00:32bit, 01:reserved, 10:64bit 11:reserved
//REG32(cfgaddr + 0x18)= (memmapaddr | 0x00000004) & 0x1FFFFFFF; // Set BAR1
//offset 0x78 [7:5]
REG32(cfgaddr + 0x78) = (REG32(cfgaddr + 0x78) & (~0xE0)) | (MAX_PAYLOAD_SIZE_128B); // Set MAX_PAYLOAD_SIZE to 128B
//offset 0x79: [6:4]
REG32(cfgaddr + 0x78) = (REG32(cfgaddr + 0x78) & (~0x7000)) | (MAX_READ_REQSIZE_256B<<8); // Set MAX_REQ_SIZE to 256B,default
//io and mem limit, setting to no litmit
REG32(rc_cfg+ 0x1c) = (2<<4) | (0<<12); // [7:4]=base [15:12]=limit
REG32(rc_cfg+ 0x20) = (2<<4) | (0<<20); // [15:4]=base [31:20]=limit
REG32(rc_cfg+ 0x24) = (2<<4) | (0<<20); // [15:4]=base [31:20]=limit
#endif
}
return 1;
}
int PCIE_PowerDown(int argc, char* argv[])
{
#define PCIE_PHY0 0xb8b01008
if( argc < 1 )
{
dprintf("epdn mode.\n");
dprintf("epdn 0: D0 ->L0 \n");
dprintf("epdn 3: D3hot ->L1 \n");
dprintf("epdn 4: board cast PME_TurnOff \n");
dprintf("epdn 7: enable aspm and L0 entry \n");
dprintf("epdn 8: enable aspm and L1 entry \n");
dprintf("epdn 9: diable aspm \n");
dprintf("Link status=%x \n", REG32(0xb8b00728)&0x1f );
return 0;
}
int mode = strtoul((const char*)(argv[0]), (char **)NULL, 10);
int tmp;
if(mode==0)
{
#if 1 //saving more power, leave L1 write
HostPCIe_SetPhyMdioWrite(0xf, 0x0f0f);
#endif
tmp = REG32(0xb8b10044) &( ~(3)); //D0
REG32(0xb8b10044) = tmp| (0); //D0
dprintf("D0 \n");
}
if(mode==3)
{
#if 1 //saving more power
REG32(0xb8b10080)|= (0x100); //enable clock PM
#endif
tmp = REG32(0xb8b10044) &( ~(3)); //D0
REG32(0xb8b10044) = tmp| (3); //D3
//HostPCIe_SetPhyMdioWrite(0xd, 0x15a6);
dprintf("D3 hot \n");
#if 1 //saving more power
HostPCIe_SetPhyMdioWrite(0xf, 0x0708);
#endif
}
if(mode==4)
{
#if 1 //saving more power leave L1 write
HostPCIe_SetPhyMdioWrite(0xf, 0x0f0f);
#endif
REG32(0xb8b01008) |= (0x200);
dprintf("Host boardcase PME_TurnOff \n");
}
if(mode==7)
{
REG32(0xb8b1070c) &= ~ ((0x7 <<27)|(0x7<<24));
REG32(0xb8b1070c) |= ((3)<<27) | ((1)<<24); //L1=3us, L0s=1us
REG32(0xb8b00080) &= ~(0x3);
REG32(0xb8b10080) &= ~(0x3);
REG32(0xb8b00080) |= 1; //L0s
REG32(0xb8b10080) |= 1;
}
if(mode==8)
{
REG32(0xb8b1070c) &= ~ ((0x7 <<27)|(0x7<<24));
REG32(0xb8b1070c) |= ((1)<<27) | ((3)<<24); //L1=1us, L0s=3us
REG32(0xb8b00080) &= ~(0x3);
REG32(0xb8b10080) &= ~(0x3);
REG32(0xb8b00080) |= 3; //L1
REG32(0xb8b10080) |= 3; //L1
}
if(mode==9)
{
REG32(0xb8b00080) &= ~(0x3);
REG32(0xb8b10080) &= ~(0x3);
}
#if 0
if(powerdown==1)
{
// REG32(0xb8b00044) &= ~(3); //D0
HostPCIe_SetPhyMdioWrite(0xd, 0x15b6);
REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
// __delay(9000000); //OK
__delay(9000000);
// HostPCIe_SetPhyMdioWrite(0xd, 0x15b6);
REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
// REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0 bit0 Enable LTSSM=1
// REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
// REG32(0xb8b10044) &= ~(3); //D0
dprintf("333 \n");
dprintf("status=%x \n", REG32(0xb8b00728) );
}
#endif
dprintf("Link status=%x \n", REG32(0xb8b00728)&0x1f );
};
void PCIE_reset_procedure(int PCIE_Port0and1_8196B_208pin, int Use_External_PCIE_CLK, int mdio_reset)
{
#define SYS_PCIE_PHY0 (0xb8000000 +0x50)
//PCIE Register
#define CLK_MANAGE 0xb8000010
//#define PCIE_PHY0_REG 0xb8b01000
//#define PCIE_PHY1_REG 0xb8b21000
#define PCIE_PHY0 0xb8b01008
// #define PCIE_PHY1 0xb8b21008
//JSW:PCIE reset procedure
#if 0
//1. "Enable internal PCIE PLL
//#if Use_External_PCIE_CLK
if(Use_External_PCIE_CLK)
REG32(PIE_PLL) = 0x358; //Use External PCIE CLK (clock chip)
//#else
else
REG32(PCIE_PLL) = 0x9; //Use Internal PCIE CLK and PCIE fine-tune
//#endif
//prom_printf("\nPCIE_PLL(0x%x)=0x%x\n",PCIE_PLL,READ_MEM32(PCIE_PLL));
__delay(1000);
#endif
//2.Active LX & PCIE Clock
REG32(CLK_MANAGE) |= (1<<11); //enable active_pcie0
__delay(1000);
#if 1
if(mdio_reset)
{
dprintf("Do MDIO_RESET\n");
// 3.MDIO Reset
REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (0<<0); //mdio reset=0,
REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (1<<0); //mdio reset=1,
REG32(SYS_PCIE_PHY0) = (1<<3) |(1<<1) | (1<<0); //bit1 load_done=1
}
//4. PCIE PHY Reset
REG32(PCIE_PHY0) = 0x01; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
__delay(100000);
#endif
__delay(100000);
#if 0
//#if Use_External_PCIE_CLK
if(Use_External_PCIE_CLK)
{
//5. PCIE P0 PHY external clock
__delay(1000);
REG32(PCIE_PHY0_REG) = 0xC3930301; //bit[3] must be "0" for external clock
//REG32(PCIE_PHY0_REG) = 0xC39B0301; //20090304:RDC for for PCIE port 0 Refine-tune
__delay(1000);
REG32(PCIE_PHY0_REG) = 0x3c011901; //close PHY 0 ,"0"=R,"1"=W
__delay(1000);
}
//#endif
#endif
//----------------------------------------
if(mdio_reset)
{
//fix 8196C test chip pcie tx problem.
/*
HostPCIe_SetPhyMdioWrite( 8, HostPCIe_SetPhyMdioRead(8) | (1<<3) );
HostPCIe_SetPhyMdioWrite(0x0d, HostPCIe_SetPhyMdioRead(0x0d) | (5<<5) );
HostPCIe_SetPhyMdioWrite(0x0d, HostPCIe_SetPhyMdioRead(0x0d) | (1<<4) );
HostPCIe_SetPhyMdioWrite(0x0f, HostPCIe_SetPhyMdioRead(0x0f) & ~(1<<4));
HostPCIe_SetPhyMdioWrite(0x06, HostPCIe_SetPhyMdioRead(0x06) | (1<<11) );
*/
#define PHY_USE_TEST_CHIP 1 // 1: test chip, 0: fib chip
#define PHY_EAT_40MHZ 1 // 0: 25MHz, 1: 40MHz
HostPCIe_SetPhyMdioWrite(0, 0x5027);
HostPCIe_SetPhyMdioWrite(2, 0x6d18);
HostPCIe_SetPhyMdioWrite(6, 0x8828);
HostPCIe_SetPhyMdioWrite(7, 0x30ff);
#if PHY_USE_TEST_CHIP
HostPCIe_SetPhyMdioWrite(8, 0x18dd); //FIB dont use
#endif
HostPCIe_SetPhyMdioWrite(0xa, 0xe9);
HostPCIe_SetPhyMdioWrite(0xb, 0x0511);
#if PHY_USE_TEST_CHIP
HostPCIe_SetPhyMdioWrite(0xd, 0x15b6); //FIB dont use
#endif
HostPCIe_SetPhyMdioWrite(0xf, 0x0f0f);
#if 0 //saving more power
HostPCIe_SetPhyMdioWrite(0xa, 0xeb);
HostPCIe_SetPhyMdioWrite(0x9, 0x538c);
// HostPCIe_SetPhyMdioWrite(0xc, 0xC828); //original
// HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix
HostPCIe_SetPhyMdioWrite(0xc, 0x8828); //new
HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix
#endif
#if PHY_EAT_40MHZ
HostPCIe_SetPhyMdioWrite(5, 0xbcb); //[9:3]=1111001 (binary) 121 (10)
HostPCIe_SetPhyMdioWrite(6, 0x8128); //[11]=0 [9:8]=01
#endif
}
//---------------------------------------
// 6. PCIE Device Reset
REG32(CLK_MANAGE) &= ~(1<<12); //perst=0 off.
__delay(100000);
__delay(100000);
__delay(100000);
REG32(CLK_MANAGE) |= (1<<12); //PERST=1
//prom_printf("\nCLK_MANAGE(0x%x)=0x%x\n\n",CLK_MANAGE,READ_MEM32(CLK_MANAGE));
//4. PCIE PHY Reset
REG32(PCIE_PHY0) = 0x01; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
#if 1 //wait for LinkUP
int i=1000;
while(--i)
{
if( (REG32(0xb8b00728)&0x1f)==0x11)
break;
__delay(100000);
}
if(i==0)
{ if(at2_mode==0) //not auto test, show message
dprintf("i=%x Cannot LinkUP \n",i);
}
#endif
}
