/******************************************************************************* * Function Name: I2C_Stop ******************************************************************************** * * Summary: * Disables I2C hardware and disables I2C interrupt. Disables Active mode power * template bits or clock gating as appropriate. * * Parameters: * None * * Return: * None * *******************************************************************************/ void I2C_Stop(void) { #if((I2C_FF_IMPLEMENTED) || \ (I2C_UDB_IMPLEMENTED && I2C_MODE_SLAVE_ENABLED)) uint8 enableInterrupts; #endif /* ((I2C_FF_IMPLEMENTED) || \ (I2C_UDB_IMPLEMENTED && I2C_MODE_SLAVE_ENABLED)) */ I2C_DisableInt(); I2C_DISABLE_INT_ON_STOP; /* Interrupt on Stop can be enabled by write */ (void) I2C_CSR_REG; /* Clear CSR reg */ #if(I2C_TIMEOUT_ENABLED) I2C_TimeoutStop(); #endif /* End (I2C_TIMEOUT_ENABLED) */ #if(I2C_FF_IMPLEMENTED) #if(CY_PSOC3 || CY_PSOC5LP) /* Store registers which are held in reset when Master and Slave bits are cleared */ #if(I2C_MODE_SLAVE_ENABLED) I2C_backup.addr = I2C_ADDR_REG; #endif /* (I2C_MODE_SLAVE_ENABLED) */ I2C_backup.clkDiv1 = I2C_CLKDIV1_REG; I2C_backup.clkDiv2 = I2C_CLKDIV2_REG; /* Reset FF block */ I2C_CFG_REG &= ((uint8) ~I2C_ENABLE_MS); CyDelayUs(I2C_FF_RESET_DELAY); I2C_CFG_REG |= ((uint8) I2C_ENABLE_MS); /* Restore registers */ #if(I2C_MODE_SLAVE_ENABLED) I2C_ADDR_REG = I2C_backup.addr; #endif /* (I2C_MODE_SLAVE_ENABLED) */ I2C_CLKDIV1_REG = I2C_backup.clkDiv1; I2C_CLKDIV2_REG = I2C_backup.clkDiv2; #endif /* (CY_PSOC3 || CY_PSOC5LP) */ /* Disable power to I2C block */ enableInterrupts = CyEnterCriticalSection(); I2C_ACT_PWRMGR_REG &= ((uint8) ~I2C_ACT_PWR_EN); I2C_STBY_PWRMGR_REG &= ((uint8) ~I2C_STBY_PWR_EN); CyExitCriticalSection(enableInterrupts); #else #if(I2C_MODE_SLAVE_ENABLED) /* Disable slave bit counter */ enableInterrupts = CyEnterCriticalSection(); I2C_COUNTER_AUX_CTL_REG &= ((uint8) ~I2C_CNT7_ENABLE); CyExitCriticalSection(enableInterrupts); #endif /* (I2C_MODE_SLAVE_ENABLED) */ I2C_CFG_REG &= ((uint8) ~I2C_ENABLE_MS); #endif /* (I2C_FF_IMPLEMENTED) */ I2C_ClearPendingInt(); /* Clear interrupt triggers on reset */ I2C_state = I2C_SM_IDLE; /* Reset software FSM */ }
/******************************************************************************* * Function Name: I2C_Stop ******************************************************************************** * * Summary: * Disables I2C hardware and disables I2C interrupt. Disables Active mode power * template bits or clock gating as appropriate. * * Parameters: * None. * * Return: * None. * *******************************************************************************/ void I2C_Stop(void) { I2C_DisableInt(); #if (I2C_TIMEOUT_ENABLED) I2C_TimeoutStop(); #endif /* End (I2C_TIMEOUT_ENABLED) */ #if (I2C_FF_IMPLEMENTED) { uint8 intState; uint16 blockResetCycles; /* Store registers effected by block disable */ I2C_backup.addr = I2C_ADDR_REG; I2C_backup.clkDiv1 = I2C_CLKDIV1_REG; I2C_backup.clkDiv2 = I2C_CLKDIV2_REG; /* Calculate number of cycles to reset block */ blockResetCycles = ((uint16) ((uint16) I2C_CLKDIV2_REG << 8u) | I2C_CLKDIV1_REG) + 1u; /* Disable block */ I2C_CFG_REG &= (uint8) ~I2C_CFG_EN_SLAVE; /* Wait for block reset before disable power */ CyDelayCycles((uint32) blockResetCycles); /* Disable power to block */ intState = CyEnterCriticalSection(); I2C_ACT_PWRMGR_REG &= (uint8) ~I2C_ACT_PWR_EN; I2C_STBY_PWRMGR_REG &= (uint8) ~I2C_STBY_PWR_EN; CyExitCriticalSection(intState); /* Enable block */ I2C_CFG_REG |= (uint8) I2C_ENABLE_MS; /* Restore registers effected by block disable. Ticket ID#198004 */ I2C_ADDR_REG = I2C_backup.addr; I2C_ADDR_REG = I2C_backup.addr; I2C_CLKDIV1_REG = I2C_backup.clkDiv1; I2C_CLKDIV2_REG = I2C_backup.clkDiv2; } #else /* Disable slave or master bits */ I2C_CFG_REG &= (uint8) ~I2C_ENABLE_MS; #if (I2C_MODE_SLAVE_ENABLED) { /* Disable bit counter */ uint8 intState = CyEnterCriticalSection(); I2C_COUNTER_AUX_CTL_REG &= (uint8) ~I2C_CNT7_ENABLE; CyExitCriticalSection(intState); } #endif /* (I2C_MODE_SLAVE_ENABLED) */ /* Clear interrupt source register */ (void) I2C_CSR_REG; #endif /* (I2C_FF_IMPLEMENTED) */ /* Disable interrupt on stop (enabled by write transaction) */ I2C_DISABLE_INT_ON_STOP; I2C_ClearPendingInt(); /* Reset FSM to default state */ I2C_state = I2C_SM_IDLE; /* Clear busy statuses */ #if (I2C_MODE_SLAVE_ENABLED) I2C_slStatus &= (uint8) ~(I2C_SSTAT_RD_BUSY | I2C_SSTAT_WR_BUSY); #endif /* (I2C_MODE_SLAVE_ENABLED) */ }