/*
* called early in main.c, after machinit:
* using board and architecture specific registers, initialise
* 8xx registers that need it and complete initialisation of the Mach structure.
*/
void
archinit(void)
{
IMM *io;
int mf, isfads, sysmhz, t;
ulong v;
v = getimmr() & 0xFFFF;
isfads = 0; /* assume it's the 860/821 board */
sysmhz = 40;
switch(v>>8){
case 0x00: t = 0x86000; break;
case 0x20: t = 0x82300; isfads = 1; break;
case 0x21: t = 0x823a0; isfads = 1; break;
default: t = 0; break;
}
m->cputype = t;
m->bcsr = KADDR(BCSRMEM);
m->bcsr[1] |= DisableRS232a | DisableIR | DisableEther | DisablePCMCIA | DisableRS232b;
m->bcsr[1] &= ~(DisableDRAM|DisableFlash);
if(isfads){
sysmhz = 50;
m->bcsr[1] &= ~EnableSDRAM;
m->bcsr[4] &= ~(EnableVideoClock|EnableVideoPort);
m->bcsr[4] |= DisableVideoLamp;
}
io = m->iomem;
if(1 || io->sccr & IBIT(7)){ /* RTDIV=1 */
/* oscillator frequency can't be determined independently: check a switch */
if((m->bcsr[2]>>19)&(1<<2))
m->clockgen = 5*MHz;
else
m->clockgen = 4*MHz;
} else
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "archpaq.h"
/*
* board-specific support for the 82x PowerPAQ
*/
enum {
SYSMHZ = 50, /* desired system clock in MHz */
/* sccr */
RTSEL = IBIT(8), /* =0, select main oscillator (OSCM); =1, select external crystal (EXTCLK) */
RTDIV = IBIT(7), /* =0, divide by 4; =1, divide by 512 */
CRQEN = IBIT(9), /* =1, switch to high frequency when CPM active */
PRQEN = IBIT(10), /* =1, switch to high frequency when interrupt pending */
/* plprcr */
CSRC = IBIT(21), /* =0, clock is DFNH; =1, clock is DFNL */
};
/*
* called early in main.c, after machinit:
* using board and architecture specific registers, initialise
* 8xx registers that need it and complete initialisation of the Mach structure.
*/
void
archinit(void)
arm_instr_t arm_decode_instr(reg instr)
{
arm_instr_t t = ARM_INSTR_ILLEGAL;
if (IBITS(24, 4) == 0xF) return (ARM_INSTR_SWI);
if (IBITS(25, 3) == BPAT3(1,0,1)) return (ARM_INSTR_B);
if (IBITS(26, 2) == BPAT2(0,0)) {
if (!IBIT(25) && !IBIT(4)) return (ARM_INSTR_AND + IBITS(21, 4));
if (!IBIT(25) && IBIT(4) && !IBIT(7)) return (ARM_INSTR_AND + IBITS(21, 4));
if ( IBIT(25)) return (ARM_INSTR_AND + IBITS(21, 4));
}
if (IBITS(22,6) == 0 && IBITS(4,4) == 9) return ARM_INSTR_MUL;
if (IBITS(23,5) == 1 && IBITS(4,4) == 9) return ARM_INSTR_MULL;
if (IBITS(25,3) == 2) {
/* Load/Store 12bit imm */
if (IBIT(20)) return (ARM_INSTR_LDR);
else return (ARM_INSTR_STR);
}
if (IBITS(25,3) == 3 && !IBIT(4)) {
if (IBIT(20)) return (ARM_INSTR_LDR);
else return (ARM_INSTR_STR);
}
if (!IBITS(25,3) && IBIT(7) && IBIT(4)) {
if (IBIT(20)) {
if (IBIT(22)) {
if ( IBIT(6) && IBIT(5)) return (ARM_INSTR_LDSH);
if ( IBIT(6) && !IBIT(5)) return (ARM_INSTR_LDSB);
if (!IBIT(6) && IBIT(5)) return (ARM_INSTR_LDUH);
}
if (!IBIT(22) && !IBITS(8,4)) {
if ( IBIT(6) && IBIT(5)) return (ARM_INSTR_LDSH);
if ( IBIT(6) && !IBIT(5)) return (ARM_INSTR_LDSB);
if (!IBIT(6) && IBIT(5)) return (ARM_INSTR_LDUH);
}
} else {
if (IBIT(22)) {
if (!IBIT(6) && IBIT(5)) return (ARM_INSTR_STH);
}
if (!IBIT(22) && !IBITS(8,4)) {
if (!IBIT(6) && IBIT(5)) return (ARM_INSTR_STH);
}
}
}
if (IBITS(25, 3) == BPAT3(1,0,0)) {
if (IBIT(20)) return (ARM_INSTR_LDM);
else return (ARM_INSTR_STM);
}
return t;
}
/*
* TO DO: most of the data could come from a table
*/
static void
lcdinit(Mode *mode)
{
IMM *io;
int i, d;
long hz;
io = m->iomem;
mode->y = ROWS;
mode->x = COLS;
mode->d = LDEPTH;
mode->aperture = ialloc(mode->x*mode->y, 16);
mode->apsize = mode->x*mode->y;
io->sdcr &= ~LAM; /* MPC823 errata: turn off LAM before disabling controller */
io->lcfaa = PADDR(mode->aperture);
io->lccr = (((mode->x*mode->y*(1<<LDEPTH)+127)/128) << 17) | (LDEPTH << 5) | IsColour | IsTFT | OELow | VsyncLow | ClockLow;
switch(LDEPTH) {
default:
case 0:
/* monochrome/greyscale identity map */
for(i=0; i<16; i++)
io->lcdmap[i] = i;
break;
case 2:
/* 4-bit grey scale map */
for(i=0; i<16; i++)
io->lcdmap[0] = (i<<8)|(i<<4)|i;
break;
case 3:
/* 8-bit linear map */
for(i=0; i<256; i++)
io->lcdmap[i] = (i<<8)|(i<<4)|i;
break;
}
io->lcvcr = (mode->y << 11) | (1<<28) | 33; /* 2 line vsync pulse, 34 line wait between frames */
io->lchcr = (mode->x<<10) | BigEndian | 228; /* clock cycles between lines */
hz = m->cpuhz;
d = hz/LCDFREQ;
if(hz/d > LCDFREQ)
d++;
if(d >= 16)
d = 16;
/*
* enable LCD outputs
*/
io->pddat = 0;
io->pdpar = 0x1fff;
io->pdpar &= ~SIBIT(6); /* 823 bug fix? */
io->pddir = 0x1fff;
io->pbpar |= IBIT(31) | IBIT(19) | IBIT(17);
io->pbdir |= IBIT(31) | IBIT(19) | IBIT(17);
io->pbodr &= ~(IBIT(31) | IBIT(19) | IBIT(17));
eieio();
io->sccrk = KEEP_ALIVE_KEY;
eieio();
io->sccr = (io->sccr & ~0x1F) | lcdclock[d];
eieio();
io->sccrk = ~KEEP_ALIVE_KEY;
eieio();
gscreen.width = gscreen.width; /* access external memory before enabling (mpc823 errata) */
io->lcsr = 7; /* clear status */
eieio();
io->lccr |= Enable;
archbacklight(1);
}