void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; ICPState *icp = xics_icp_get(xi, cs->cpu_index); ICPStateClass *icpc; assert(icp); icp->cs = cs; icpc = ICP_GET_CLASS(icp); if (icpc->cpu_setup) { icpc->cpu_setup(icp, cpu); } switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_POWER7: icp->output = env->irq_inputs[POWER7_INPUT_INT]; break; case PPC_FLAGS_INPUT_970: icp->output = env->irq_inputs[PPC970_INPUT_INT]; break; default: error_report("XICS interrupt controller does not support this CPU " "bus model"); abort(); } }
static void icp_dispatch_pre_save(void *opaque) { ICPState *ss = opaque; ICPStateClass *info = ICP_GET_CLASS(ss); if (info->pre_save) { info->pre_save(ss); } }
static int icp_dispatch_post_load(void *opaque, int version_id) { ICPState *ss = opaque; ICPStateClass *info = ICP_GET_CLASS(ss); if (info->post_load) { return info->post_load(ss, version_id); } return 0; }