HalSci5::HalSci5(){
int i;
PORTC.ICR.BIT.B2 = 1;
PORTC.DDR.BIT.B2 = 0;
PORTC.DDR.BIT.B3 = 1;
MSTP(SCI5) = 0;
SCI5.SCR.BYTE = 0x00;
SCI5.SMR.BYTE = 0x00;
SCI5.SCMR.BIT.SMIF= 0;
SCI5.SCMR.BIT.SINV= 0;
SCI5.SCMR.BIT.SDIR= 0;
SCI5.BRR = 12;
//SCI5.SEMR.BIT.ABCS = 1;
for(i=0;i<0x800000;i++);
SCI5.SCR.BYTE = 0x30;
SCI5.SCR.BIT.TE=1;
SCI5.SCR.BIT.TIE=1;
SCI5.SCR.BIT.RE=1;
SCI5.SCR.BIT.RIE=1;
IEN(SCI5,RXI5)=0;
IEN(SCI5,TXI5)=1;
IPR(SCI5,TXI5)=GeneralConfig::gpsIpr;
IPR(SCI5,RXI5)=GeneralConfig::gpsIpr;
}
void vInitialiseTimerForIntQueueTest( void )
{
/* Ensure interrupts do not start until full configuration is complete. */
portENTER_CRITICAL();
{
/* Give write access. */
SYSTEM.PRCR.WORD = 0xa502;
/* Cascade two 8bit timer channels to generate the interrupts.
8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
utilised for this test. */
/* Enable the timers. */
SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
/* Enable compare match A interrupt request. */
TMR0.TCR.BIT.CMIEA = 1;
TMR2.TCR.BIT.CMIEA = 1;
/* Clear the timer on compare match A. */
TMR0.TCR.BIT.CCLR = 1;
TMR2.TCR.BIT.CCLR = 1;
/* Set the compare match value. */
TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
/* 16 bit operation ( count from timer 1,2 ). */
TMR0.TCCR.BIT.CSS = 3;
TMR2.TCCR.BIT.CSS = 3;
/* Use PCLK as the input. */
TMR1.TCCR.BIT.CSS = 1;
TMR3.TCCR.BIT.CSS = 1;
/* Divide PCLK by 8. */
TMR1.TCCR.BIT.CKS = 2;
TMR3.TCCR.BIT.CKS = 2;
/* Enable TMR 0, 2 interrupts. */
TMR0.TCR.BIT.CMIEA = 1;
TMR2.TCR.BIT.CMIEA = 1;
/* Set interrupt priority and enable. */
IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
IR( TMR0, CMIA0 ) = 0U;
IEN( TMR0, CMIA0 ) = 1U;
/* Do the same for TMR2, but to vector 129. */
IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2;
IR( TMR2, CMIA2 ) = 0U;
IEN( TMR2, CMIA2 ) = 1U;
}
portEXIT_CRITICAL();
}
char HalSci0::getchar(){
char buf;
IEN(SCI0,RXI0)=0;
while(!SCI0.SSR.BIT.RDRF){}
buf = SCI0.RDR;
SCI0.SSR.BYTE=(char)(SCI0.SSR.BYTE & 0x80);
stdout->putChar(buf);
IR(SCI0,RXI0)=0;
IEN(SCI0,RXI0)=1;
return buf;
}
void pl_emergencia_init(void)
{
ICU.IRQCR[8].BIT.IRQMD = 2;
IR(ICU, IRQ8) = 0; //Clear any previously pending interrupts
IPR(ICU, IRQ8) = 3; //Set interrupt priority
IEN(ICU, IRQ8) = 0; // Enable interrupt
IR(ICU, IRQ8) = 0; //Clear any previously pending interrupts
IEN(ICU, IRQ8) = 1; // Enable interrupt
xTaskCreate((pdTASK_CODE)emergencia_task, "Emergencia task", 256, NULL, 3, &xEmergenciaTaskHandle );
R_CMT_CreatePeriodic(10000,timer_motorPower_callback,&timerMotorPower);
}
/******************************************************************************
* Function name : cmt_init
* Description : Create one-shot timers based on PCLK / 3
* Arguments : None
* Return Value : None
******************************************************************************/
void cmt_init(void)
{
#ifdef PLATFORM_BOARD_RDKRX63N
SYSTEM.PRCR.WORD = 0xA50B; /* Protect off */
#endif
/* Cancel CMT module stop state. */
MSTP(CMT0) = 0;
MSTP(CMT1) = 0;
#ifdef PLATFORM_BOARD_RDKRX63N
SYSTEM.PRCR.WORD = 0xA500; /* Protect on */
#endif
/* Compare Match Timer Control Register (CMCR)
b15:b8 reserved: Read/Write value always 0
b7 reserved: Read undef. Write value always 1
b6 CMIE: Compare Match Interrupt Enable
b5:b2 reserved: Read/Write value always 0
b1:b0 CKS: clock select 3 = count on PCLK / 512
*/
CMT0.CMCR.WORD = 0x0003; /* Just set clock divisor for now. */
CMT1.CMCR.WORD = 0x0003;
CMT2.CMCR.WORD = 0x0003;
/* Compare Match Timer Counter (CMCNT)
b15:b0 16-bit readable/writable up-counter to generate interrupt requests.
*/
CMT0.CMCNT = 0x00; /* Clear the count (default value). */
CMT1.CMCNT = 0x00;
CMT2.CMCNT = 0x00;
/* Compare Match Timer Constant Register (CMCOR))
b15:b0 16-bit register sets the value for a compare match with CMCNT.
*/
CMT0.CMCOR = 0xFFFF; /* Set to max (default value). */
CMT1.CMCOR = 0xFFFF;
CMT2.CMCOR = 0xFFFF;
IR (CMT0, CMI0); /* Interrupt reset. */
IR (CMT1, CMI1);
IR (CMT2, CMI2);
IPR(CMT0, CMI0) = 4; /* Interrupt priority set. */
IPR(CMT1, CMI1) = 4;
IPR(CMT2, CMI2) = 4;
IEN(CMT0, CMI0) = 1; /* Interrupt enable. */
IEN(CMT1, CMI1) = 1;
IEN(CMT2, CMI2) = 1;
} /* End of function cmt_init() */
void vInitialiseTimerForIntQueueTest( void )
{
/* Ensure interrupts do not start until full configuration is complete. */
portENTER_CRITICAL();
{
/* Cascade two 8bit timer channels to generate the interrupts.
8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are
utilised for this test. */
/* Enable the timers. */
SYSTEM.MSTPCRA.BIT.MSTPA5 = 0;
SYSTEM.MSTPCRA.BIT.MSTPA4 = 0;
/* Enable compare match A interrupt request. */
TMR0.TCR.BIT.CMIEA = 1;
TMR2.TCR.BIT.CMIEA = 1;
/* Clear the timer on compare match A. */
TMR0.TCR.BIT.CCLR = 1;
TMR2.TCR.BIT.CCLR = 1;
/* Set the compare match value. */
TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 );
/* 16 bit operation ( count from timer 1,2 ). */
TMR0.TCCR.BIT.CSS = 3;
TMR2.TCCR.BIT.CSS = 3;
/* Use PCLK as the input. */
TMR1.TCCR.BIT.CSS = 1;
TMR3.TCCR.BIT.CSS = 1;
/* Divide PCLK by 8. */
TMR1.TCCR.BIT.CKS = 2;
TMR3.TCCR.BIT.CKS = 2;
/* Enable TMR 0, 2 interrupts. */
IEN( TMR0, CMIA0 ) = 1;
IEN( TMR2, CMIA2 ) = 1;
/* Set the timer interrupts to be above the kernel. The interrupts are
assigned different priorities so they nest with each other. */
IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1;
IPR( TMR2, CMIA2 ) = ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 );
}
portEXIT_CRITICAL();
/* Ensure the interrupts are clear as they are edge detected. */
IR( TMR0, CMIA0 ) = 0;
IR( TMR2, CMIA2 ) = 0;
}
void BSP_Ser_WrByteUnlocked (CPU_INT08U c)
{
/* Enable the Transmission Complete interrupt. */
IEN(SCI2, TEI2) = 1;
SCI2.SCR.BIT.TIE = 1; /* Enable Transmit Interrupts */
SCI2.TDR = c; /* Place character to be transmitted into register */
BSP_OS_SemWait(&BSP_SerTxWait, 0);
IEN(SCI2, TEI2) = 0;
SCI2.SCR.BIT.TIE = 0; /* Disable Transmit Interrupts */
}
//#pragma interrupt (DD_PixelsLineISR(vect=VECT_MTU0_TGIB0, enable))
void DD_PixelsLineISR(void)
{
// We have just got an interrupt to start sending out data.
// Depending on which line we are processing changes what we do.
if (DD_CurrentLine < (V_LINES_PULSE + V_LINES_BACK_PORCH + DD_FRAME_HEIGHT)) {
// We are a standard line of data about to go out.
// Determine the address of the line of pixels to send.
// And send a single line of pixels.
EXDMAC0.EDMSAR = (TUInt32)(DD_ActiveRegionLines.pLine);
EXDMAC0.EDMCRB = 1;
EXDMAC0.EDMCRA = /*(DD_FRAME_WIDTH << 16) + */DD_FRAME_WIDTH;
EXDMAC0.EDMCNT.BIT.DTE = 1;
// Setup for the next line to go out by moving to the next address
DD_ActiveRegionLines.pLine += DD_ActiveRegionLines.LineNext;
// Have we reached the last line of the frame data?
if (DD_CurrentLine >= (V_LINES_PULSE + V_LINES_BACK_PORCH
+ DD_FRAME_HEIGHT - 1)) {
// Yes, end of frame. Turn back on the blank period interrupt
// calls to DD_BlankLineISR() after making sure its interrupt flag
// is cleared. We'll still get one more interrupt in this
// routine (see below)
ICU.IR[IR_MTU0_TGIA0].BIT.IR = 0;
//ICU.IER[IER_MTU0_TGIA0].BIT.IEN0 = 1;
IEN(MTU0, TGIA0) = 1;
}
} else {
// We have just reached the end of the frame.
// Now keep the Data Enable line initially high and transiting to
// high on matches.
MTU4.TIORL.BIT.IOC = 0x6;
// We are no longer using the bus to get data
DD_IsBusActive = 0;
// Turn off this interrupt (DD_PixelsLineISR) now.
//ICU.IER[IER_MTU0_TGIB0].BIT.IEN1 = 0;
IEN(MTU0, TGIB0) = 0;
// Let the frame interrupt occur
//ICU.IER[IER_MTU3_TGIC3].BIT.IEN3 = 1;
IEN(MTU3, TGIC3) = 1;
}
// Next line please
DD_CurrentLine++;
}
void rtc_init(void)
{
/* For detailed description please refer to hardware manual */
SYSTEM.SUBOSCCR.BIT.SUBSTOP = 0; /* Enable SubClock circuit */
RTC.RCR2.BIT.START = 0;
while (0 != RTC.RCR2.BIT.START);
RTC.RCR2.BIT.RESET = 1;
while (1 == RTC.RCR2.BIT.RESET);
/* Set initial time and date */
RTC.RSECCNT.BYTE = 0;
RTC.RMINCNT.BYTE = 0;
RTC.RHRCNT.BYTE = 0;
RTC.RDAYCNT.BYTE = 0;
RTC.RWKCNT.BYTE = 0;
RTC.RMONCNT.BYTE = 0;
RTC.RYRCNT.WORD = 0x2000;
/* Set periodic interrupt */
RTC.RCR1.BYTE = 0;
RTC.RCR1.BIT.PES = 1; /* Set periodic interrupts frequency to 256 Hz */
RTC.RCR1.BIT.PIE = 1; /* Enable periodic interrupts */
_isr_vectors[VECT(RTC,PRD)] = rtc_irq_handler;
IR(RTC,PRD) = 0; /* Clear interrupt flag */
IPR(RTC,PRD) = 15; /* Set priority level */
IEN(RTC,PRD) = 1; /* Enable interrupt in ICU */
RTC.RCR2.BIT.START = 1; /* Start RTC */
while (1 != RTC.RCR2.BIT.START);
}
int sound_start (
WAVFIFO* fcb, /* Pointer to the sound FIFO control structure */
uint32_t fs /* Sampling frequency [Hz] */
)
{
if (fs < 8000 || fs > 48000) return 0; /* Check fs range */
WavFifo = fcb; /* Register FIFO control structure */
fcb->ri = 0; fcb->wi = 0; fcb->ct = 0; /* Flush FIFO */
/* Configure DAC0/DAC1 as audio output */
MSTP_DA = 0; /* Enable DAC0/1 power */
DA.DADPR.BIT.DPSEL = 1; /* DADR0/1 register left-justfied */
DA.DACR.BYTE = 0xE0; /* Enable DAC0/1 */
/* Configure CMT3 as sampling interval timer */
MSTP_CMT2 = 0; /* Enable CMT2/3 power */
CMT3.CMCOR = (uint16_t)(F_PCLK / 8 / fs - 1); /* Audio sampling interval */
CMT3.CMCNT = 0;
IPR(CMT3, CMI3) = 9; /* Interrupt priority = 9 */
IEN(CMT3, CMI3) = 1; /* Enable CMT3 compare match irq */
CMT3.CMCR.BIT.CMIE = 1;
CMT.CMSTR1.BIT.STR3 = 1; /* Start CMT3 */
return 1;
}
/****************************************************************************
* Attach interval timer function
*
* The callback function is called every 1ms interval
* @param[in] fFunction Specify callback function
*
* @return none
*
***************************************************************************/
void attachIntervalTimerHandler(void (*fFunction)(unsigned long u32Milles))
{
g_fITInterruptFunc = fFunction;
startModule(MstpIdTPU0);
// Stop the timer.
TPUA.TSTR.BIT.CST5 = 0U;
// Set the counter to run at the desired frequency.
TPU5.TCR.BIT.TPSC = 0b011;
// Set TGRA compare match to clear TCNT.
TPU5.TCR.BIT.CCLR = 0b001;
// Set the count to occur on rising edge of PCLK.
TPU5.TCR.BIT.CKEG = 0b01;
// Set Normal.
TPU5.TMDR.BIT.MD = 0b0000;
// Set the period.
TPU5.TGRA = 750 - 1; //1ms setting at PCLK/64(750kHz)
// Set the count to occur on rising edge of PCLK.
TPU5.TSR.BIT.TGFA = 0U;
/* Set TGI6A interrupt priority level to 5*/
IPR(TPU5,TGI5A) = 0x5;
/* Enable TGI6A interrupts */
IEN(TPU5,TGI5A) = 0x1;
/* Clear TGI6A interrupt flag */
IR(TPU5,TGI5A) = 0x0;
// Enable the module interrupt for the ms timer.
TPU5.TIER.BIT.TGIEA = 1U;
// Start the timer.
TPUA.TSTR.BIT.CST5 = 1U;
}
void rx63nEthEnableIrq(NetInterface *interface)
{
//Enable Ethernet MAC interrupts
IEN(ETHER, EINT) = 1;
//Enable Ethernet PHY interrupts
interface->phyDriver->enableIrq(interface);
}
void rx63nEthDisableIrq(NetInterface *interface)
{
//Disable Ethernet MAC interrupts
IEN(ETHER, EINT) = 0;
//Disable Ethernet PHY interrupts
interface->phyDriver->disableIrq(interface);
}
/***********************************************************************************************************************
* Function Name: R_CMT0_Stop
* Description : This function stops the CMT0 channel counter.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_CMT0_Stop(void)
{
/* Disable CMI0 interrupt in ICU */
IEN(CMT0,CMI0) = 0U;
/* Stop CMT0 count */
CMT.CMSTR0.BIT.STR0 = 0U;
}
/***********************************************************************************************************************
* Function Name: R_CMT0_Start
* Description : This function starts the CMT0 channel counter.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_CMT0_Start(void)
{
/* Enable CMI0 interrupt in ICU */
IEN(CMT0,CMI0) = 1U;
/* Start CMT0 count */
CMT.CMSTR0.BIT.STR0 = 1U;
}
CPU_INT08U BSP_Ser_RdByteUnlocked (void)
{
CPU_INT08U rx_byte;
IEN(SCI2, RXI2) = 1; /* Enable the Receive Data Register Full interrupt. */
SCI2.SCR.BIT.RIE = 1; /* Enable Receive Interrupts */
BSP_OS_SemWait(&BSP_SerRxWait, 0); /* Wait until a data is received */
IEN(SCI2, RXI2) = 0; /* Disable the Receive Data Register Full interrupt. */
SCI2.SCR.BIT.RIE = 0; /* Disable Receive Interrupts */
rx_byte = BSP_SerRxData; /* Read the data form the temporal register. */
return (rx_byte);
}
void cet_init(void){
// CMT.CMSTR1.BIT.STR2 = 1; //カウント開始
MTU5.TCRV.BIT.TPSC = 3; //クロック周波数φ/64 (MTUのクロックは48Mhz)
MTU5.TCRU.BIT.TPSC = 3; //クロック周波数φ/64 (MTUのクロックは48Mhz)
MTU5.TIORV.BIT.IOC = 17; // 立ち上がりエッジでインプットキャプチャ
MTU5.TIORU.BIT.IOC = 17; // 立ち上がりエッジでインプットキャプチャ
MTU5.TSTR.BIT.CSTV5 = 1; // MU25Vカウントスタート
MTU5.TSTR.BIT.CSTU5 = 1; // MU25Wカウントスタート
IEN(MTU5,TGIV5) = 0; //割り込み禁止
IEN(MTU5,TGIU5) = 0; //割り込み禁止
IPR(MTU5,TGIV5) = 11; // 割り込みレベル設定(CMT0)0〜15 0:最低 15:最高
IPR(MTU5,TGIU5) = 11; // 割り込みレベル設定(CMT0)0〜15 0:最低 15:最高
MTU5.TIER.BIT.TGIE5V = 1; // 割り込み許可
MTU5.TIER.BIT.TGIE5U = 1; // 割り込み許可
IEN(MTU5,TGIV5) = 1; //割り込み許可
IEN(MTU5,TGIU5) = 1; //割り込み許可
/*SH
MTU24.TCR.BIT.TPSC = 0; // クロック周波数φ/1 (MTUのクロックは25Mhz)
MTU24.TIER.BIT.TCIEV = 1; //オーバーフロー割り込み許可
INTC.IPRF.BIT._MTU24C= 13; // 割り込みレベル設定(CMT1)0〜15 0:最低 15:最高
MTU2.TSTR.BIT.CST4 = 1; // MTU24カウントスタート
MTU25.TIORV.BIT.IOC = 17; // 立ち上がりエッジでインプットキャプチャ
MTU25.TIORW.BIT.IOC = 17; // 立ち上がりエッジでインプットキャプチャ
PFC.PBCRL1.BIT.PB1MD = 3; // ポートB1をMTU2に設定
PFC.PBIORL.BIT.B1 = 0; // 入力ポートに設定
PFC.PBCRL1.BIT.PB3MD = 3; // ポートB3をMTU2に設定
PFC.PBIORL.BIT.B3 = 0; // 入力ポートに設定
MTU25.TIER.BIT.TGIEV = 1; //割り込み許可(TCLKA)
MTU25.TIER.BIT.TGIEW = 1; //割り込み許可(TCLKC)
INTC.IPRF.BIT._MTU25= 12;
*/
}
/******************************************************************************
* タイトル ： タイマーの設定
* 関数名 ： init_cmt0
* 戻り値 ： void型 タイマーの設定
* 引数 ： なし
* 作成者 ： 石井
* 作成日 ： 2014/06/21
******************************************************************************/
void init_CMT0(void)
{
SYSTEM.MSTPCRA.BIT.MSTPA15 = 0;//CMT0のモジュールストップ状態を解除
CMT.CMSTR0.BIT.STR0 = 0;//カウント停止
CMT0.CMCR.BIT.CKS = 2;//クロック選択 PCLK/128
CMT0.CMCOR = 375; //CMCORの決定 48000000/128/1000 = 375
CMT0.CMCNT = 0;//初期化
CMT0.CMCR.BIT.CMIE = 1;
IEN(CMT0,CMI0) = 1;//割り込み要求許可レジスタ
IPR(CMT0,CMI0) = 14;//優先度
}
//#pragma interrupt (DD_FrameISR(vect=VECT_MTU3_TGIC3, enable))
void DD_FrameISR(void)
{
//extern void DirectDriveHook_FrameEnd();
// Disable this interrupt (DD_FrameISR)
//ICU.IER[IER_MTU3_TGIC3].BIT.IEN3 = 0;
IEN(MTU3, TGIC3) = 0;
// One more frame counted
DD_FrameCount++;
// Call a hook for when the end of the screen has occurred
//DirectDriveHook_FrameEnd();
}
/***********************************************************************************************************************
* Function Name: R_ICU_Create
* Description : This function initializes ICU module.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_ICU_Create(void)
{
/* Disable IRQ interrupts */
ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE | _00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE |
_00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE | _00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE;
ICU.IER[0x09].BYTE = _00_ICU_IRQ8_DISABLE | _00_ICU_IRQ9_DISABLE | _00_ICU_IRQ10_DISABLE | _00_ICU_IRQ11_DISABLE |
_00_ICU_IRQ12_DISABLE | _00_ICU_IRQ13_DISABLE | _00_ICU_IRQ14_DISABLE | _00_ICU_IRQ15_DISABLE;
/* Disable group interrupts */
IEN(ICU,GROUPBL0) = 0U;
/* Set IRQ settings */
ICU.IRQCR[2].BYTE = _04_ICU_IRQ_EDGE_FALLING;
ICU.IRQCR[5].BYTE = _04_ICU_IRQ_EDGE_FALLING;
/* Set IRQ2 priority level */
IPR(ICU,IRQ2) = _0F_ICU_PRIORITY_LEVEL15;
/* Set IRQ5 priority level */
IPR(ICU,IRQ5) = _0F_ICU_PRIORITY_LEVEL15;
/* Set Group BL0 priority level */
IPR(ICU,GROUPBL0) = _0F_ICU_PRIORITY_LEVEL15;
/* Enable group BL0 interrupt */
IEN(ICU,GROUPBL0) = 1U;
/* Set IRQ2 pin */
MPC.P12PFS.BYTE = 0x40U;
PORT1.PDR.BYTE &= 0xFBU;
PORT1.PMR.BYTE &= 0xFBU;
/* Set IRQ5 pin */
MPC.P15PFS.BYTE = 0x40U;
PORT1.PDR.BYTE &= 0xDFU;
PORT1.PMR.BYTE &= 0xDFU;
}
HalSci0::HalSci0(){
int i;
PORT2.ICR.BIT.B1 = 1;
PORT2.DDR.BIT.B1 = 0;
MSTP(SCI0) = 0;
SCI0.SCR.BYTE = 0x00;
SCI0.SMR.BYTE = 0x00;
SCI0.SCMR.BIT.SMIF= 0;
SCI0.SCMR.BIT.SINV= 0;
SCI0.SCMR.BIT.SDIR= 0;
SCI0.BRR = 12;
//SCI0.SEMR.BIT.ABCS = 1;
for(i=0;i<0x800000;i++);
SCI0.SCR.BYTE = 0x30;
SCI0.SCR.BIT.TE=1;
SCI0.SCR.BIT.TIE=1;
SCI0.SCR.BIT.RE=1;
SCI0.SCR.BIT.RIE=1;
IEN(SCI0,RXI0)=0;
IEN(SCI0,TXI0)=1;
IPR(SCI0,TXI0)=GeneralConfig::uartIpr;
IPR(SCI0,RXI0)=GeneralConfig::uartIpr;
SCI0.SSR.BYTE=(char)(SCI0.SSR.BYTE & 0x80);
echo =0;
}
/***********************************************************************************************************************
* Function name: interrupts_configure
* Description : Configures interrupts used
* Arguments : none
* Return value : none
***********************************************************************************************************************/
void interrupts_configure(void)
{
/* Enable the bus error interrupt to catch accesses to illegal/reserved areas
of memory. */
/* Clear any pending interrupts */
IR(BSC,BUSERR) = 0;
/* Make this the highest priority interrupt (adjust as necessary for your
application) */
IPR(BSC,BUSERR) = 0x0F;
/* Enable the interrupt in the ICU */
IEN(BSC,BUSERR) = 1;
/* Enable illegal address interrupt in the BSC */
BSC.BEREN.BIT.IGAEN = 1;
}
/***********************************************************************************************************************
* Function Name: R_CMT0_Create
* Description : This function initializes the CMT0 channel.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_CMT0_Create(void)
{
/* Disable CMI interrupt */
IEN(CMT0, CMI0) = 0U;
/* Cancel CMT stop state in LPC */
MSTP(CMT0) = 0U;
/* Set control registers */
CMT0.CMCR.WORD = _0002_CMT_CMCR_CKS_PCLK128 | _0040_CMT_CMCR_CMIE_ENABLE;
CMT0.CMCOR = _B71B_CMT0_CMCOR_VALUE;
/* Set CMI0 priority level */
IPR(CMT0,CMI0) = _08_CMT_PRIORITY_LEVEL8;
}
void emergencia_task(void)
{
uint32_t keyEntry = 0;
uint8_t emergencyCount = 0;
bool realease = false;
while(1)
{
emergenciaFlag = false;
realease = false;
IR(ICU, IRQ8) = 0; //Clear any previously pending interrupts
IEN(ICU, IRQ8) = 1; // Enable interrupt
ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
IR(ICU, IRQ8) = 0; //Clear any previously pending interrupts
IEN(ICU, IRQ8) = 0; // Enable interrupt
while(EMERGENCIA && !realease)
{
vTaskDelay(1 / portTICK_PERIOD_MS);
emergencyCount++;
if(emergencyCount == 100)
{
static mn_screen_event_t mn_emergencia;
emergenciaFlag = true;
if (isCuttingGet() == true)
{
stopDuringCut_Set(true);
}
//machine_pause();
mn_emergencia.event = EMERGENCIA_SIGNAL_EVENT;
xQueueSend( menu.qEvent, &mn_emergencia, 0 );
ulTaskNotifyTake( pdTRUE, portMAX_DELAY );
realease = true;
emergencyCount = 0;
}
}
}
}
void ADC_HALInit(void) {
/***** 10ビットA/Dコンバータの初期設定 *****/
/* AD0モジュールストップ解除 */
MSTP(AD0) = 0;
/* ADTRG0#からのトリガ選択 ,PCLK/8(6MHz≧4MHz),シングルモード選択 */
AD0.ADCR.BIT.TRGS = 0x3;
AD0.ADCR.BIT.MODE = 0;
AD0.ADCR.BIT.CKS = 0;
/* AN0選択, 変換停止, ADI0割り込み要求の発生を許可 */
AD0.ADCSR.BIT.CH = 0;
AD0.ADCSR.BIT.ADIE = 1;
/* 割り込みステータスフラグクリア */
IR ( AD0, ADI0 )= 0;
IEN( AD0, ADI0 )= 0;
IPR( AD0, ADI0 )= 2;
}
void init_Sci_2(void)//追加
{
int i= 0;
SYSTEM.MSTPCRB.BIT.MSTPB29 = 0; //SCI1モジュールSTOP状態を解除
//河原 0x01→0x00 で通信速度を最大に．分周1
PORT1.DDR.BIT.B2 = 0; //
PORT1.ICR.BIT.B2 = 1; //
PORT1.DDR.BIT.B3 = 0; //追加
PORT1.ICR.BIT.B3 = 1; //追加
SCI2.SCR.BIT.TEIE = 0; //TEIE割込み要求を禁止 P815
SCI2.SCR.BIT.MPIE = 0; //通常の受信動作 P815
SCI2.SCR.BIT.RIE = 1; //RXIおよびERI割込み要求を許可 P815
SCI2.SCR.BIT.TIE = 1; //TXI割込み要求を許可 P815
SCI2.SCR.BIT.RE = 0; //シリアル受信動作を禁止 P815
SCI2.SCR.BIT.TE = 0; //シリアル送信動作を禁止 P815
SCI2.SCR.BIT.CKE = 0; //内臓ポーレートジェネレータ。P815
SCI2.SMR.BIT.CM = 0; //調歩同期式モード P813
SCI2.SMR.BIT.CHR = 0; //データ長8ビットで送受信 P813
SCI2.SMR.BIT.PE = 0; //パリティビットなし P813
SCI2.SMR.BIT.PM = 0; //偶数パリティで送受信 P813
SCI2.SMR.BIT.STOP = 0; //1ストップビット
SCI2.SMR.BIT.MP = 0; //ﾏﾙﾁﾌﾟﾛｾｯｻ通信機能を禁止
SCI2.SMR.BIT.CKS = 0; //PCLKクロック(n=0)
SCI2.BRR = PCLK * 1000000 / ( 64 * 0.5 * BITRATE_2 ) - 1; //BRRレジスタの設定値 P822
for(i=0;i > 80000;i++);
SCI2.SCR.BIT.RE = 1; //シリアル受信動作を許可 P815
SCI2.SCR.BIT.TE = 1; //シリアル送信動作を許可 P815
IEN(SCI2,RXI2) = 1;
IPR(SCI2,RXI2) = 11;
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
enter_critical_section();
LTRACEF("callback %p, arg %p, interval %lu\n", callback, arg, interval);
t_callback = callback;
periodic_interval = interval;
uint32_t ticks = periodic_interval * 1000; /* timer is running close to 1Mhz */
ASSERT(ticks <= 0xffff);
TIMREG(IEN(0)) = (1<<0); // interval interrupt
TIMREG(INTERVAL_VAL(0)) = ticks;
TIMREG(CNT_CTRL(0)) = (1<<5) | (1<<4) | (1<<1); // no wave, reset, interval mode
unmask_interrupt(TTC0_A_INT);
exit_critical_section();
return NO_ERROR;
}
/******************************************************************************
* タイトル ： sci通信初期化
* 関数名 ： init_Sci
* 戻り値 ： void型
* 引数 ： なし
******************************************************************************/
void init_Sci_0(void)
{
int bit_count = 0;
SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; //SCI0モジュールSTOP状態を解除
SCI0.SCR.BYTE = 0x00; //シリアルコントロールレジスタ
//河原 0x01→0x00 で通信速度を最大に．分周1
PORT2.DDR.BIT.B1 = 0; //
PORT2.ICR.BIT.B1 = 1; //
PORT2.DDR.BIT.B0 = 0; //追加
PORT2.ICR.BIT.B0 = 1; //
SCI0.SMR.BYTE = 0x00; //シリアルモードレジスタ
SCI0.SEMR.BIT.ABCS = 1; //調歩同期基本クロックを８サイクルの期間を１ビット期間の転送レートとする
SCI0.BRR = ((48*1000000)/((64/(1+SCI0.SEMR.BIT.ABCS))*powf(2,2*SCI0.SMR.BIT.CKS-1)*BITRATE_0)-1);; //ビットレートレジスタ77 9600bpsなら0x01の77
for( bit_count = 0; bit_count < 0x80000; bit_count++ ){ //１ビット待つため
}
SCI0.SCR.BYTE = 0x70; //送受信動作を許可
IEN(SCI0,RXI0) = 1;
IPR(SCI0,RXI0) = 13;
}
void HalSci0::start(){
SCI0.SSR.BYTE=(char)(SCI0.SSR.BYTE & 0x80);
IEN(SCI0,RXI0)=1;
}
inline void HalSci0::unlock(){
IEN(SCI0,TXI0)=1;
}
