static void c_can_setup_receive_object(struct net_device *dev, int iface, int objno, unsigned int mask, unsigned int id, unsigned int mcont) { struct c_can_priv *priv = netdev_priv(dev); priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), IFX_WRITE_LOW_16BIT(mask)); /* According to C_CAN documentation, the reserved bit * in IFx_MASK2 register is fixed 1 */ priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), IFX_WRITE_LOW_16BIT(id)); priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); }
static void c_can_setup_receive_object(struct net_device *dev, int iface, int objno, unsigned int mask, unsigned int id, unsigned int mcont) { struct c_can_priv *priv = netdev_priv(dev); priv->write_reg(priv, &priv->regs->ifregs[iface].mask1, IFX_WRITE_LOW_16BIT(mask)); /* According to C_CAN documentation, the reserved bit * in IFx_MASK2 register is fixed 1 */ priv->write_reg(priv, &priv->regs->ifregs[iface].mask2, IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, IFX_WRITE_LOW_16BIT(id)); priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, mcont); c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, c_can_read_reg32(priv, &priv->regs->msgval1)); }
static void c_can_write_msg_object(struct net_device *dev, int iface, struct can_frame *frame, int objno) { int i; u16 flags = 0; unsigned int id; struct c_can_priv *priv = netdev_priv(dev); if (!(frame->can_id & CAN_RTR_FLAG)) flags |= IF_ARB_TRANSMIT; if (frame->can_id & CAN_EFF_FLAG) { id = frame->can_id & CAN_EFF_MASK; flags |= IF_ARB_MSGXTD; } else id = ((frame->can_id & CAN_SFF_MASK) << 18); flags |= IF_ARB_MSGVAL; priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), IFX_WRITE_LOW_16BIT(id)); priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | IFX_WRITE_HIGH_16BIT(id)); for (i = 0; i < frame->can_dlc; i += 2) { priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, frame->data[i] | (frame->data[i + 1] << 8)); } /* enable interrupt for this message object */ priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | frame->can_dlc); c_can_object_put(dev, iface, objno, IF_COMM_ALL); }
static void c_can_setup_receive_object(struct net_device *dev, int iface, int objno, unsigned int mask, unsigned int id, unsigned int mcont) { struct c_can_priv *priv = netdev_priv(dev); priv->write_reg(priv, &priv->regs->ifregs[iface].mask1, IFX_WRITE_LOW_16BIT(mask)); priv->write_reg(priv, &priv->regs->ifregs[iface].mask2, IFX_WRITE_HIGH_16BIT(mask)); priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, IFX_WRITE_LOW_16BIT(id)); priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, mcont); c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, c_can_read_reg32(priv, &priv->regs->msgval1)); }