static int
xel_probe(paddr_t addr)
{
u_int32_t b1, b2;
volatile u_int16_t *start = (volatile u_int16_t *)IIOV(addr);
label_t faultbuf;
volatile u_int32_t *sram = (volatile u_int32_t *)IIOV(XEL_RAM_ADDR_HIGHER);
if (badaddr(start))
return 0;
nofault = (int *) &faultbuf;
if (setjmp(&faultbuf)) {
nofault = NULL;
return 0;
}
b1 = sram[0];
b2 = sram[1];
/* Try to map the Xellent local memory. */
start[0] = XEL_MODE_RAM_HIGHER | XEL_MODE_MAP_RAM | XEL_MODE_MPU_030;
#if 0
/* the contents should be deferent. */
if (b1 == sram[0] && b2 == sram[1]) {
nofault = (int *) 0;
return 0;
}
#else
/* Try to write to the local memory. */
sram[0] = 0x55555555;
sram[1] = 0xaaaaaaaa;
if (sram[0] != 0x55555555 || sram[1] != 0xaaaaaaaa) {
sram[0] = b1;
sram[1] = b2;
nofault = (int *) 0;
return 0;
}
sram[0] = 0xaaaaaaaa;
sram[1] = 0x55555555;
if (sram[0] != 0xaaaaaaaa || sram[1] != 0x55555555) {
sram[0] = b1;
sram[1] = b2;
nofault = (int *) 0;
return 0;
}
sram[0] = b1;
sram[1] = b2;
#endif
/* Unmap. */
start[0] = XEL_MODE_UNMAP_RAM | XEL_MODE_MPU_030;
nofault = NULL;
return 1;
}
void
nextdisplay_attach(device_t parent, device_t self, void *aux)
{
struct nextdisplay_softc *sc = device_private(self);
struct wsemuldisplaydev_attach_args waa;
int isconsole;
int iscolor;
paddr_t addr;
if (rom_machine_type == NeXT_WARP9C ||
rom_machine_type == NeXT_TURBO_COLOR) {
iscolor = 1;
addr = colorbase;
} else {
iscolor = 0;
addr = monobase;
}
isconsole = nextdisplay_is_console(addr);
if (isconsole) {
sc->sc_dc = &nextdisplay_console_dc;
sc->nscreens = 1;
} else {
sc->sc_dc = (struct nextdisplay_config *)
malloc(sizeof(struct nextdisplay_config), M_DEVBUF, M_WAITOK);
nextdisplay_init(sc->sc_dc, iscolor);
}
printf(": %d x %d, %dbpp\n", sc->sc_dc->dc_wid, sc->sc_dc->dc_ht,
sc->sc_dc->dc_depth);
if (iscolor) {
#if 0
uint8_t x;
x = *(volatile uint8_t *)IIOV(NEXT_P_C16_CMD_REG);
aprint_debug_dev(sc->sc_dev, "cmd=%02x\n", x);
#endif
*(volatile uint8_t *)IIOV(NEXT_P_C16_CMD_REG) = 0x05;
isrlink_autovec(nextdisplay_intr, sc, NEXT_I_IPL(NEXT_I_C16_VIDEO), 1, NULL);
INTR_ENABLE(NEXT_I_C16_VIDEO);
}
/* initialize the raster */
waa.console = isconsole;
waa.scrdata = iscolor ? &nextdisplay_screenlist_color : &nextdisplay_screenlist_mono;
waa.accessops = &nextdisplay_accessops;
waa.accesscookie = sc;
#if 0
printf("nextdisplay: access cookie is %p\n", sc);
#endif
config_found(self, &waa, wsemuldisplaydevprint);
}
int
dnkbd_init()
{
/*
* 362, 382, 400, 425, and 433 models can have a Domain keyboard.
* Note that we do not tell 360 from 362 in the bootblocks.
*/
switch (machineid) {
case HP_360:
case HP_382:
case HP_400:
case HP_425:
case HP_433:
break;
default:
return (0);
}
/*
* Look for a Frodo utility chip. If we find one, assume there
* is a Domain keyboard attached.
*/
if (badaddr((caddr_t)IIOV(FRODO_BASE + FRODO_APCI_OFFSET(0))))
return (0);
/*
* XXX Any other initialization? This appears to work ok.
*/
return (1);
}
void
lrcattach(struct device *parent, struct device *self, void *aux)
{
struct confargs *ca = aux;
struct lrcsoftc *sc = (struct lrcsoftc *)self;
sc->sc_paddr = ca->ca_paddr;
sc->sc_vaddr = IIOV(sc->sc_paddr);
sys_lrc = sc->sc_regs = (struct lrcreg *)sc->sc_vaddr;
printf("\n");
/* sync serial clock with DUART */
sc->sc_regs->lrc_gcr &= ~GCR_SCFREQ;
/* disable VSB */
sc->sc_regs->lrc_bcr &= ~(BCR_VA24 | BCR_VSBEN | BCR_ROEN);
/* set up vector base */
sc->sc_regs->lrc_icr1 = LRC_VECBASE;
/* enable interrupts */
sc->sc_regs->lrc_icr0 = ICR0_GIE;
sc->sc_abortih.ih_fn = lrcabort;
sc->sc_abortih.ih_ipl = IPL_HIGH;
sc->sc_abortih.ih_wantframe = 1;
lrcintr_establish(LRCVEC_ABORT, &sc->sc_abortih, self->dv_xname);
config_search(lrcscan, self, aux);
}
/*
* Is the zs chip present?
*/
static int
zs_match(device_t parent, cfdata_t cf, void *aux)
{
struct intio_attach_args *ia = aux;
struct zsdevice *zsaddr = (void *)ia->ia_addr;
int i;
if (strcmp(ia->ia_name, "zsc") != 0)
return 0;
for (i = 0; i < ZS_MAXDEV; i++)
if (zsaddr == (void *)zs_physaddr[i]) /* XXX */
break;
ia->ia_size = 8;
if (intio_map_allocate_region(parent, ia, INTIO_MAP_TESTONLY))
return 0;
if (zsaddr != (void *)zs_physaddr[i])
return 0;
if (badaddr((void *)IIOV(zsaddr)))
return 0;
return (1);
}
int
nextdisplay_intr(void *arg)
{
#if 0
uint8_t x;
#endif
if (!INTR_OCCURRED(NEXT_I_C16_VIDEO))
return (0);
#if 0
x = *(volatile uint8_t *)IIOV(NEXT_P_C16_CMD_REG);
printf("I%02x", x);
#endif
*(volatile uint8_t *)IIOV(NEXT_P_C16_CMD_REG) = 0x05;
return (1);
}
int
clock_intr(void *arg)
{
volatile struct timer_reg *timer;
int whilecount = 0;
if (!INTR_OCCURRED(NEXT_I_TIMER)) {
return(0);
}
do {
static int in_hardclock = 0;
int s;
timer = (volatile struct timer_reg *)IIOV(NEXT_P_TIMER);
timer->csr |= TIMER_REG_UPDATE;
if (! in_hardclock) {
in_hardclock = 1;
s = splclock ();
hardclock(arg);
splx(s);
in_hardclock = 0;
}
if (whilecount++ > 10)
panic ("whilecount");
} while (INTR_OCCURRED(NEXT_I_TIMER));
return(1);
}
int
topcat_intio_match(struct device *parent, void *match, void *aux)
{
struct intio_attach_args *ia = aux;
struct diofbreg *fbr;
fbr = (struct diofbreg *)IIOV(GRFIADDR);
if (badaddr((caddr_t)fbr))
return (0);
if (fbr->id == GRFHWID) {
switch (fbr->fbid) {
case GID_TOPCAT:
case GID_LRCATSEYE:
case GID_HRCCATSEYE:
case GID_HRMCATSEYE:
#if 0
case GID_XXXCATSEYE:
#endif
ia->ia_addr = (caddr_t)GRFIADDR;
return (1);
}
}
return (0);
}
void
dnkbd_attach(struct device *parent, struct device *self, void *aux)
{
struct dnkbd_softc *sc = (struct dnkbd_softc *)self;
struct frodo_attach_args *fa = aux;
printf(": ");
sc->sc_regs = (struct apciregs *)IIOV(FRODO_BASE + fa->fa_offset);
timeout_set(&sc->sc_bellstop_tmo, dnkbd_bellstop, sc);
#ifdef WSDISPLAY_COMPAT_RAWKBD
timeout_set(&sc->sc_rawrepeat_ch, dnkbd_rawrepeat, sc);
#endif
/* reset the port */
apciinit(sc->sc_regs, 1200, CFCR_8BITS | CFCR_PEVEN | CFCR_PENAB);
sc->sc_isr.isr_func = dnkbd_intr;
sc->sc_isr.isr_arg = sc;
sc->sc_isr.isr_priority = IPL_TTY;
frodo_intr_establish(parent, fa->fa_line, &sc->sc_isr, self->dv_xname);
/* probe for keyboard */
if (dnkbd_probe(sc) != 0) {
printf("no keyboard\n");
return;
}
dnkbd_attach_subdevices(sc);
}
int
dnkbd_init(void)
{
/*
* 400, 425, and 433 models can have a Domain keyboard.
*/
switch (machineid) {
case HP_400:
case HP_425:
case HP_433:
break;
default:
return 0;
}
/*
* Look for a Frodo utility chip. If we find one, assume there
* is a Domain keyboard attached.
*/
if (badaddr((void *)IIOV(FRODO_BASE + FRODO_APCI_OFFSET(0))))
return 0;
/*
* XXX Any other initialization? This appears to work ok.
*/
return 1;
}
/*
* NB: This code should probably be converted to a _true_ device, then this
* initialization could happen in attach. The printf could get fixed then,
* too.
*/
void
rtc_init(void)
{
static struct todr_chip_handle tch;
u_char val;
scr2 = (u_int *)IIOV(NEXT_P_SCR2);
val = rtc_read(RTC_STATUS);
new_clock = (val & RTC_NEW_CLOCK) ? 1 : 0;
printf("Looks like a %s clock chip.\n",
(new_clock?
"MCS1850 (new style)":
"MC68HC68T1 (old style)"));
#ifdef RTC_DEBUG
rtc_print();
#endif
if (new_clock) {
tch.todr_gettime = gettime_new;
tch.todr_settime = settime_new;
tch.todr_gettime_ymdhms = NULL;
tch.todr_settime_ymdhms = NULL;
} else {
tch.todr_gettime_ymdhms = gettime_old;
tch.todr_settime_ymdhms = settime_old;
tch.todr_gettime = NULL;
tch.todr_settime = NULL;
}
tch.todr_setwen = NULL;
todr_attach(&tch);
}
static int
slhci_intio_match(device_t parent, cfdata_t cf, void *aux)
{
struct intio_attach_args *ia = aux;
bus_space_tag_t iot = ia->ia_bst;
bus_space_handle_t ioh;
bus_space_handle_t nch;
int nc_addr;
int nc_size;
if (ia->ia_addr == INTIOCF_ADDR_DEFAULT)
ia->ia_addr = SLHCI_INTIO_ADDR1;
if (ia->ia_intr == INTIOCF_INTR_DEFAULT)
ia->ia_intr = SLHCI_INTIO_INTR1;
/* fixed parameters */
if ( !(ia->ia_addr == SLHCI_INTIO_ADDR1 &&
ia->ia_intr == SLHCI_INTIO_INTR1 ) &&
!(ia->ia_addr == SLHCI_INTIO_ADDR2 &&
ia->ia_intr == SLHCI_INTIO_INTR2 ) )
return 0;
/* Whether the SL811 port is accessible or not */
if (badaddr((void *)IIOV(ia->ia_addr)))
return 0;
/* Whether the control port is accessible or not */
nc_addr = ia->ia_addr + NEREID_ADDR_OFFSET;
nc_size = 0x02;
if (badbaddr((void *)IIOV(nc_addr)))
return 0;
/* Map two I/O spaces */
ia->ia_size = SL11_PORTSIZE * 2;
if (bus_space_map(iot, ia->ia_addr, ia->ia_size,
BUS_SPACE_MAP_SHIFTED, &ioh))
return 0;
if (bus_space_map(iot, nc_addr, nc_size,
BUS_SPACE_MAP_SHIFTED, &nch))
return 0;
bus_space_unmap(iot, ioh, ia->ia_size);
bus_space_unmap(iot, nch, nc_size);
return 1;
}
int
mainbus_map(bus_addr_t addr, bus_size_t size, int flags,
bus_space_handle_t *ret)
{
if (ISIIOPA(addr)) {
*ret = (bus_space_handle_t)IIOV(addr);
return (0);
} else
return (ENOMEM);
}
static int
bmd_match(device_t parent, cfdata_t cf, void *aux)
{
struct intio_attach_args *ia = aux;
bus_space_tag_t iot = ia->ia_bst;
bus_space_handle_t ioh;
int window;
int r;
if (ia->ia_addr == INTIOCF_ADDR_DEFAULT)
ia->ia_addr = BMD_ADDR1;
/* fixed parameter */
if (ia->ia_addr != BMD_ADDR1 && ia->ia_addr != BMD_ADDR2)
return (0);
/* Check CTRL addr */
if (badaddr((void *)IIOV(ia->ia_addr)))
return (0);
ia->ia_size = 2;
if (bus_space_map(iot, ia->ia_addr, ia->ia_size, 0, &ioh))
return (0);
/* Check window addr */
r = bus_space_read_1(iot, ioh, BMD_CTRL);
bus_space_unmap(iot, ioh, ia->ia_size);
if ((r & BMD_CTRL_WINDOW))
window = 0xef0000;
else
window = 0xee0000;
if (badaddr((void *)IIOV(window)))
return (0);
return (1);
}
int
hil_intio_match(struct device *parent, void *match, void *aux)
{
struct intio_attach_args *ia = aux;
static int hil_matched = 0;
/* Allow only one instance. */
if (hil_matched != 0)
return (0);
if (badaddr((caddr_t)IIOV(HILADDR))) /* should not happen! */
return (0);
ia->ia_addr = (caddr_t)HILADDR;
return (1);
}
int
dnkbd_getc(void)
{
struct apciregs *apci =
(struct apciregs *)IIOV(FRODO_BASE + FRODO_APCI_OFFSET(0));
int c;
/* default to `no key' */
c = 0;
/* Is data in the UART? */
if (apci->ap_lsr & LSR_RXRDY) {
/* Get the character. */
c = apci->ap_data;
/* Ignoring mouse? */
if (dnkbd_ignore) {
dnkbd_ignore--;
return 0;
}
/* Is this the start of a mouse packet? */
if (c == 0xdf) {
dnkbd_ignore = 3; /* 3 bytes of junk */
return 0;
}
/* It's a keyboard event. */
switch (dnkbd_keymap[c]) {
case 0x00:
/* passthrough */
break;
case 0xff:
/* ignore */
c = 0;
break;
default:
c = dnkbd_keymap[c];
break;
}
}
return c;
}
static int
ne_intio_match(device_t parent, cfdata_t cf, void *aux)
{
struct intio_attach_args *ia = aux;
bus_space_tag_t iot = ia->ia_bst;
bus_space_handle_t ioh;
bus_space_tag_t asict;
bus_space_handle_t asich;
int rv = 0;
if (ia->ia_addr == INTIOCF_ADDR_DEFAULT)
ia->ia_addr = NE_INTIO_ADDR;
if (ia->ia_intr == INTIOCF_INTR_DEFAULT)
ia->ia_intr = NE_INTIO_INTR;
/* fixed parameters */
if (!(ia->ia_addr == NE_INTIO_ADDR && ia->ia_intr == NE_INTIO_INTR ) &&
!(ia->ia_addr == NE_INTIO_ADDR2 && ia->ia_intr == NE_INTIO_INTR2) )
return 0;
/* Make sure this is a valid NE2000 I/O address */
if ((ia->ia_addr & 0x1f) != 0)
return 0;
/* Check whether the board is inserted or not */
if (badaddr((void *)IIOV(ia->ia_addr)))
return 0;
/* Map I/O space */
if (bus_space_map(iot, ia->ia_addr, NE2000_NPORTS*2,
BUS_SPACE_MAP_SHIFTED_EVEN, &ioh))
return 0;
asict = iot;
if (bus_space_subregion(iot, ioh, NE2000_ASIC_OFFSET*2,
NE2000_ASIC_NPORTS*2, &asich))
goto out;
/* Look for an NE2000 compatible card */
rv = ne2000_detect(iot, ioh, asict, asich);
out:
bus_space_unmap(iot, ioh, NE2000_NPORTS);
return (rv != 0) ? 1 : 0;
}
int
rbox_intio_match(struct device *parent, void *match, void *aux)
{
struct intio_attach_args *ia = aux;
struct diofbreg *fbr;
fbr = (struct diofbreg *)IIOV(GRFIADDR);
if (badaddr((caddr_t)fbr))
return (0);
if (fbr->id == GRFHWID && fbr->fbid == GID_RENAISSANCE) {
ia->ia_addr = (caddr_t)GRFIADDR;
return (1);
}
return (0);
}
void
topcat_intio_attach(struct device *parent, struct device *self, void *aux)
{
struct topcat_softc *sc = (struct topcat_softc *)self;
struct diofbreg *fbr;
fbr = (struct diofbreg *)IIOV(GRFIADDR);
sc->sc_scode = CONSCODE_INTERNAL;
if (sc->sc_scode == conscode) {
sc->sc_fb = &diofb_cn;
} else {
sc->sc_fb = &sc->sc_fb_store;
topcat_reset(sc->sc_fb, sc->sc_scode, fbr);
}
topcat_end_attach(sc, fbr->fbid);
}
/* ARGSUSED */
int
bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
{
vaddr_t kva;
vsize_t offset;
int error;
if (t->bustype == HP300_BUS_SPACE_INTIO) {
/*
* Intio space is direct-mapped in pmap_bootstrap(); just
* do the translation.
*/
*bshp = (bus_space_handle_t)IIOV(INTIOBASE + bpa);
return 0;
}
if (t->bustype != HP300_BUS_SPACE_DIO &&
t->bustype != HP300_BUS_SPACE_SGC)
panic("%s: bad space tag", __func__);
/*
* Allocate virtual address space from the extio extent map.
*/
offset = m68k_page_offset(bpa);
size = m68k_round_page(offset + size);
error = extent_alloc(extio_ex, size, PAGE_SIZE, 0,
EX_FAST | EX_NOWAIT | (extio_ex_malloc_safe ? EX_MALLOCOK : 0),
&kva);
if (error)
return error;
/*
* Map the range. The range is always cache-inhibited on the hp300.
*/
physaccess((void *)kva, (void *)bpa, size, PG_RW|PG_CI);
/*
* All done.
*/
*bshp = (bus_space_handle_t)(kva + offset);
return 0;
}
void
rbox_intio_attach(struct device *parent, struct device *self, void *aux)
{
struct rbox_softc *sc = (struct rbox_softc *)self;
struct diofbreg *fbr;
fbr = (struct diofbreg *)IIOV(GRFIADDR);
sc->sc_scode = CONSCODE_INTERNAL;
if (sc->sc_scode == conscode) {
sc->sc_fb = &diofb_cn;
} else {
sc->sc_fb = &sc->sc_fb_store;
rbox_reset(sc->sc_fb, sc->sc_scode, fbr);
}
diofb_end_attach(sc, &rbox_accessops, sc->sc_fb,
sc->sc_scode == conscode, NULL);
}
/*
* Set up the real-time and statistics clocks. Leave stathz 0 only
* if no alternative timer is available.
*
* The frequencies of these clocks must be an even number of microseconds.
*/
void
cpu_initclocks(void)
{
int s, cnt;
volatile struct timer_reg *timer;
rtc_init();
hz = 100;
s = splclock();
timer = (volatile struct timer_reg *)IIOV(NEXT_P_TIMER);
cnt = 1000000/hz; /* usec timer */
timer->csr = 0;
timer->msb = (cnt >> 8);
timer->lsb = cnt;
timer->csr = TIMER_REG_ENABLE|TIMER_REG_UPDATE;
isrlink_autovec(clock_intr, NULL, NEXT_I_IPL(NEXT_I_TIMER), 0, NULL);
INTR_ENABLE(NEXT_I_TIMER);
splx(s);
}
/*
* Is the zs chip present?
*/
static int
zs_match(device_t parent, cfdata_t cf, void *aux)
{
struct hb_attach_args *ha = aux;
u_int addr;
if (strcmp(ha->ha_name, "zsc"))
return 0;
/* XXX no default address */
if (ha->ha_address == (u_int)-1)
return 0;
addr = IIOV(ha->ha_address);
/* This returns -1 on a fault (bus error). */
if (badaddr((void *)addr, 1))
return 0;
return 1;
}
void
apciprobe(struct consdev *cp)
{
apcicnaddr = (void *)IIOV(FRODO_BASE + FRODO_APCI_OFFSET(1));
cp->cn_pri = CN_DEAD;
/*
* Only a 425e can have an APCI console. On all other 4xx models,
* the "first" serial port is mapped to the DCA at select code 9.
*/
if (machineid != HP_425 || mmuid != MMUID_425_E)
return;
#ifdef FORCEAPCICONSOLE
cp->cn_pri = CN_REMOTE;
#else
cp->cn_pri = CN_NORMAL;
#endif
curcons_scode = -2;
}
void
zscninit(struct consdev *cn)
{
volatile struct zschan *cnchan = (volatile void *)IIOV(ZSCN_PHYSADDR);
int s;
memset(&zscn_cs, 0, sizeof(struct zs_chanstate));
zscn_cs.cs_reg_csr = &cnchan->zc_csr;
zscn_cs.cs_reg_data = &cnchan->zc_data;
zscn_cs.cs_channel = 0;
zscn_cs.cs_brg_clk = PCLK / 16;
memcpy(zscn_cs.cs_preg, zs_init_reg, 16);
zscn_cs.cs_preg[4] = ZSWR4_CLK_X16 | ZSWR4_ONESB; /* XXX */
zscn_cs.cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
zs_set_speed(&zscn_cs, ZSCN_SPEED);
s = splzs();
zs_write_reg(&zscn_cs, 9, 0);
zs_write_reg(&zscn_cs, 9, ZSWR9_HARD_RESET);
zs_loadchannelregs(&zscn_cs);
splx(s);
conschan = cnchan;
}
/*
* Initialize the sti device for ite's needs.
* We don't bother to check for failures since
* - we are in tight space already
* - since romputchar() does not work with sti devices, there is no way we
* can report errors (although we could switch to serial...)
*/
void
sti_iteinit(struct ite_data *ip)
{
int slotno, i;
size_t codesize, memsize;
u_int8_t *va, *code;
u_int addr, eaddr, reglist, tmp;
struct sti_inqconfout cfg;
struct sti_einqconfout ecfg;
bzero(&sti, sizeof sti);
slotno = (int)ip->fbbase;
ip->fbbase = va = (u_int8_t *)IIOV(SGC_BASE + (slotno * SGC_DEVSIZE));
/*
* Read the microcode.
*/
for (i = 0; i < STI_CODECNT; i++)
sti.codeptr[i] =
parseword1(va, (STI_CODEBASE_M68K << 2) + i * 0x10);
for (i = STI_END; sti.codeptr[i] == 0; i--);
codesize = sti.codeptr[i] - sti.codeptr[STI_BEGIN];
codesize = (codesize + 3) / 4;
sti.code = (u_int8_t *)alloc(codesize);
code = sti.code;
addr = (u_int)va + sti.codeptr[STI_BEGIN];
eaddr = addr + codesize * 4;
for (; addr < eaddr; addr += 4)
*code++ = *(u_int8_t *)addr;
for (i = STI_CODECNT - 1; i != 0; i--)
if (sti.codeptr[i] != 0) {
sti.codeptr[i] -= sti.codeptr[0];
sti.codeptr[i] /= 4;
}
sti.codeptr[0] = 0;
for (i = STI_END; sti.codeptr[i] == 0; i--);
sti.codeptr[i] = 0;
/*
* Read the regions list.
*/
reglist = parseword1(va, 0x60);
for (i = 0; i < STI_REGION_MAX; i++) {
tmp = parseword1(va, (reglist & ~3) + i * 0x10);
sti.cfg.regions[i] = (u_int)va + ((tmp >> 18) << 12);
if (tmp & 0x4000)
break;
}
/*
* Allocate scratch memory for the microcode if it needs it.
*/
sti.cfg.ext_cfg = &sti.ecfg;
memsize = parseword1(va, 0xa0);
if (memsize != 0)
sti.ecfg.addr = alloc(memsize);
/*
* Initialize the display, and get geometry information.
*/
sti_init(0);
bzero(&cfg, sizeof cfg);
bzero(&ecfg, sizeof ecfg);
cfg.ext = &ecfg;
sti_inqcfg(&cfg);
if (cfg.owidth == cfg.width && cfg.oheight == cfg.height) {
sti.cfg.oscr_width = cfg.owidth = cfg.fbwidth - cfg.width;
sti.cfg.oscr_height = cfg.oheight = cfg.fbheight - cfg.height;
}
ip->dheight = cfg.height;
ip->dwidth = cfg.width;
ip->fbheight = cfg.fbheight;
ip->fbwidth = cfg.fbwidth;
/*
* Get ready for ite operation!
*/
sti_init(1);
sti_fontinfo(ip);
sti_clear(ip, 0, 0, ip->rows, ip->cols); /* necessary? */
}
/*
* Locate all bitmapped displays
*/
void
iteconfig()
{
extern struct hp_hw sc_table[];
int dtype, fboff, slotno, i;
u_int8_t *va;
struct hp_hw *hw;
struct diofbreg *fb;
struct ite_data *ip;
i = 0;
for (hw = sc_table; hw < &sc_table[MAXCTLRS]; hw++) {
if (!HW_ISDEV(hw, D_BITMAP))
continue;
fb = (struct diofbreg *)hw->hw_kva;
/* XXX: redundent but safe */
if (badaddr((caddr_t)fb) || fb->id != GRFHWID)
continue;
for (dtype = 0; dtype < nitems(itesw); dtype++)
if (itesw[dtype].ite_hwid == fb->fbid)
break;
if (dtype == nitems(itesw))
continue;
if (i >= NITE)
break;
ip = &ite_data[i];
ip->scode = hw->hw_sc;
ip->isw = &itesw[dtype];
ip->regbase = (caddr_t)fb;
fboff = (fb->fbomsb << 8) | fb->fbolsb;
ip->fbbase = (caddr_t) (*((u_char *)ip->regbase+fboff) << 16);
/* DIO II: FB offset is relative to select code space */
if (DIO_ISDIOII(ip->scode))
ip->fbbase += (int)ip->regbase;
ip->fbwidth = fb->fbwmsb << 8 | fb->fbwlsb;
ip->fbheight = fb->fbhmsb << 8 | fb->fbhlsb;
ip->dwidth = fb->dwmsb << 8 | fb->dwlsb;
ip->dheight = fb->dhmsb << 8 | fb->dhlsb;
/*
* XXX some displays (e.g. the davinci) appear
* to return a display height greater than the
* returned FB height. Guess we should go back
* to getting the display dimensions from the
* fontrom...
*/
if (ip->dwidth > ip->fbwidth)
ip->dwidth = ip->fbwidth;
if (ip->dheight > ip->fbheight)
ip->dheight = ip->fbheight;
/* confirm hardware is what we think it is */
if (itesw[dtype].ite_probe != NULL &&
(*itesw[dtype].ite_probe)(ip) != 0)
continue;
ip->alive = 1;
i++;
}
/*
* Now probe for SGC frame buffers.
*/
switch (machineid) {
case HP_400:
case HP_425:
case HP_433:
break;
default:
return;
}
/* SGC frame buffers can only be STI... */
for (dtype = 0; dtype < nitems(itesw); dtype++)
if (itesw[dtype].ite_hwid == GID_STI)
break;
if (dtype == nitems(itesw))
return;
for (slotno = 0; slotno < SGC_NSLOTS; slotno++) {
va = (u_int8_t *)IIOV(SGC_BASE + (slotno * SGC_DEVSIZE));
/* Check to see if hardware exists. */
if (badaddr(va) != 0)
continue;
/* Check hardware. */
if (va[3] == STI_DEVTYPE1) {
if (i >= NITE)
break;
ip = &ite_data[i];
ip->scode = slotno;
ip->isw = &itesw[dtype];
ip->regbase = (caddr_t)GRFIADDR; /* to get CN_MIDPRI */
/* ...and do not need an ite_probe() check */
ip->alive = 1;
i++;
/* we only support one SGC frame buffer at the moment */
break;
}
}
}
/*
* Attach a found zs.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct cfdata *cf = device_cfdata(self);
struct hb_attach_args *ha = aux;
struct zsc_attach_args zsc_args;
struct zsdevice *zs;
struct zschan *zc;
struct zs_chanstate *cs;
int s, channel, clk;
zsc->zsc_dev = self;
zs = (void *)IIOV(ha->ha_address);
clk = cf->cf_flags;
if (clk < 0 || clk >= NPCLK)
clk = 0;
aprint_normal("\n");
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
zsc_args.channel = channel;
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
zc = (channel == 0) ? &zs->zs_chan_a : &zs->zs_chan_b;
if (ha->ha_vect != -1)
zs_init_reg[2] = ha->ha_vect;
if (zc == zc_cons) {
memcpy(cs, zs_conschan, sizeof(struct zs_chanstate));
zs_conschan = cs;
zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
} else {
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_defspeed = zs_defspeed;
zsc_args.hwflags = 0;
}
zs_lock_init(cs);
cs->cs_defcflag = zs_def_cflag;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = pclk[clk] / 16;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
s = splhigh();
zs_write_reg(cs, 9, 0);
splx(s);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
if (!config_found(self, (void *)&zsc_args, zs_print)) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splhigh();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Now safe to install interrupt handlers.
*/
hb_intr_establish(zs_init_reg[2], zshard, ZSHARD_PRI, zsc);
zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splhigh();
/* interrupt vector */
zs_write_reg(cs, 2, zs_init_reg[2]);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
/*
* Locate all bitmapped displays
*/
void
iteconfig()
{
extern struct hp_hw sc_table[];
int dtype, fboff, slotno, i;
u_int8_t *va;
struct hp_hw *hw;
struct grfreg *gr;
struct ite_data *ip;
i = 0;
for (hw = sc_table; hw < &sc_table[MAXCTLRS]; hw++) {
if (!HW_ISDEV(hw, D_BITMAP))
continue;
gr = (struct grfreg *) hw->hw_kva;
/* XXX: redundent but safe */
if (badaddr((caddr_t)gr) || gr->gr_id != GRFHWID)
continue;
for (dtype = 0; dtype < nitesw; dtype++)
if (itesw[dtype].ite_hwid == gr->gr_id2)
break;
if (dtype == nitesw)
continue;
if (i >= NITE)
break;
ip = &ite_data[i];
ip->isw = &itesw[dtype];
ip->regbase = (caddr_t) gr;
fboff = (gr->gr_fbomsb << 8) | gr->gr_fbolsb;
ip->fbbase = (caddr_t) (*((u_char *)ip->regbase+fboff) << 16);
/* DIO II: FB offset is relative to select code space */
if (ip->regbase >= (caddr_t)DIOIIBASE)
ip->fbbase += (int)ip->regbase;
ip->fbwidth = gr->gr_fbwidth_h << 8 | gr->gr_fbwidth_l;
ip->fbheight = gr->gr_fbheight_h << 8 | gr->gr_fbheight_l;
ip->dwidth = gr->gr_dwidth_h << 8 | gr->gr_dwidth_l;
ip->dheight = gr->gr_dheight_h << 8 | gr->gr_dheight_l;
/*
* XXX some displays (e.g. the davinci) appear
* to return a display height greater than the
* returned FB height. Guess we should go back
* to getting the display dimensions from the
* fontrom...
*/
if (ip->dwidth > ip->fbwidth)
ip->dwidth = ip->fbwidth;
if (ip->dheight > ip->fbheight)
ip->dheight = ip->fbheight;
ip->alive = 1;
i++;
}
/*
* Now probe for SGC frame buffers.
* Note that we do not tell 360 from 362 in the bootblocks.
*/
switch (machineid) {
case HP_360:
case HP_382:
case HP_400:
case HP_425:
case HP_433:
break;
default:
return;
}
for (dtype = 0; dtype < nitesw; dtype++)
if (itesw[dtype].ite_hwid == GID_STI)
break;
if (dtype == nitesw)
return;
for (slotno = 0; slotno < SGC_NSLOTS; slotno++) {
va = (u_int8_t *)IIOV(SGC_BASE + (slotno * SGC_DEVSIZE));
/* Check to see if hardware exists. */
if (badaddr(va) != 0)
continue;
/* Check hardware. */
if (va[3] == STI_DEVTYPE1) {
if (i >= NITE)
break;
ip = &ite_data[i];
ip->isw = &itesw[dtype];
ip->regbase = (caddr_t)GRFIADDR; /* to get CN_MIDPRI */
ip->fbbase = (caddr_t)slotno;
ip->alive = 1;
i++;
/* we only support one SGC frame buffer at the moment */
break;
}
}
}
/*
* Attach a found zs.
*/
static void
zs_attach(device_t parent, device_t self, void *aux)
{
struct zsc_softc *zsc = device_private(self);
struct intio_attach_args *ia = aux;
struct zsc_attach_args zsc_args;
volatile struct zschan *zc;
struct zs_chanstate *cs;
int r, s, zs_unit, channel;
zsc->zsc_dev = self;
aprint_normal("\n");
zs_unit = device_unit(self);
zsc->zsc_addr = (void *)ia->ia_addr;
ia->ia_size = 8;
r = intio_map_allocate_region(parent, ia, INTIO_MAP_ALLOCATE);
#ifdef DIAGNOSTIC
if (r)
panic("zs: intio IO map corruption");
#endif
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
device_t child;
zsc_args.channel = channel;
zsc_args.hwflags = 0;
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
zs_lock_init(cs);
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
if (channel == 0)
zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_a);
else
zc = (volatile void *)IIOV(&zsc->zsc_addr->zs_chan_b);
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
zs_init_reg[2] = ia->ia_intr;
memcpy(cs->cs_creg, zs_init_reg, 16);
memcpy(cs->cs_preg, zs_init_reg, 16);
if (zc == conschan) {
zsc_args.hwflags |= ZS_HWFLAG_CONSOLE;
cs->cs_defspeed = zs_get_speed(cs);
cs->cs_defcflag = zscn_def_cflag;
} else {
cs->cs_defspeed = 9600;
cs->cs_defcflag = zs_def_cflag;
}
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
s = splzs();
zs_write_reg(cs, 9, 0);
splx(s);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
child = config_found(self, (void *)&zsc_args, zs_print);
#if ZSTTY > 0
if (zc == conschan &&
((child && strcmp(device_xname(child), "zstty0")) ||
child == NULL)) /* XXX */
panic("%s: console device mismatch", __func__);
#endif
if (child == NULL) {
/* No sub-driver. Just reset it. */
uint8_t reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splzs();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Now safe to install interrupt handlers.
*/
if (intio_intr_establish(ia->ia_intr, "zs", zshard, zsc))
panic("%s: interrupt vector busy", __func__);
zsc->zsc_softintr_cookie = softint_establish(SOFTINT_SERIAL,
(void (*)(void *))zsc_intr_soft, zsc);
/* XXX; evcnt_attach() ? */
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splzs();
/* interrupt vector */
zs_write_reg(cs, 2, ia->ia_intr);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}