void __init imx_init_irq(void) { unsigned int irq; DEBUG_IRQ("Initializing imx interrupts\n"); /* Mask all interrupts initially */ IMR(0) = 0; IMR(1) = 0; IMR(2) = 0; IMR(3) = 0; for (irq = 0; irq < IMX_IRQS; irq++) { set_irq_chip(irq, &imx_internal_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, IRQF_VALID); } for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { set_irq_chip(irq, &imx_gpio_chip); set_irq_handler(irq, do_edge_IRQ); set_irq_flags(irq, IRQF_VALID); } set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler); set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler); set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler); set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler); /* Disable all interrupts initially. */ /* In IMX this is done in the bootloader. */ }
static void i2s_stop(struct dw_i2s_dev *dev, struct snd_pcm_substream *substream) { u32 i = 0, irq; i2s_clear_irqs(dev, substream->stream); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { i2s_write_reg(dev->i2s_base, ITER, 0); for (i = 0; i < 4; i++) { irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); } } else { i2s_write_reg(dev->i2s_base, IRER, 0); for (i = 0; i < 4; i++) { irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); } } if (!dev->active) { i2s_write_reg(dev->i2s_base, CER, 0); i2s_write_reg(dev->i2s_base, IER, 0); } }
static void imx21_gpio_handler(unsigned int irq_unused, struct irqdesc *desc, struct pt_regs *regs) { unsigned int mask; unsigned int port; unsigned int irq_base; unsigned int irq = 0; for (port = 0; port < 6; port++) { if (ISR(port) & IMR(port)) { break; } } mask = ISR(port); irq_base = IRQ_GPIOA(0) + (port * 32); desc = irq_desc + irq_base; while (mask) { if (mask & 1) { DEBUG_IRQ("handling irq %d (port %d)\n", irq, port); desc->handle(irq + irq_base, desc, regs); ISR(port) = (1 << irq); } irq++; desc++; mask >>= 1; } }
static void imx21_gpio_unmask_irq(unsigned int irq) { DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); PMASK = PMASK | (1 << IRQ_TO_REG(irq)); }
static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, int chan_nr) { u32 i, irq; if (stream == SNDRV_PCM_STREAM_PLAYBACK) { for (i = 0; i < (chan_nr / 2); i++) { irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); } } else { for (i = 0; i < (chan_nr / 2); i++) { irq = i2s_read_reg(dev->i2s_base, IMR(i)); i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); } } }
void __init imx_init_irq(void) { unsigned int irq; DEBUG_IRQ("Initializing imx interrupts\n"); /* Disable all interrupts initially. */ /* Do not rely on the bootloader. */ __raw_writel(0, IMX_AITC_INTENABLEH); __raw_writel(0, IMX_AITC_INTENABLEL); /* Mask all GPIO interrupts as well */ IMR(0) = 0; IMR(1) = 0; IMR(2) = 0; IMR(3) = 0; for (irq = 0; irq < IMX_IRQS; irq++) { set_irq_chip(irq, &imx_internal_chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) { set_irq_chip(irq, &imx_gpio_chip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID); } set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler); set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler); set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler); set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler); /* Release masking of interrupts according to priority */ __raw_writel(-1, IMX_AITC_NIMASK); #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(); #endif }
void __init imx21_init_irq(void) { unsigned int irq; DEBUG_IRQ("Initializing imx21 interrupts\n"); /* Mask all interrupts initially */ IMR(0) = 0; IMR(1) = 0; IMR(2) = 0; IMR(3) = 0; IMR(4) = 0; IMR(5) = 0; for (irq = 0; irq < IMX21_IRQS; irq++) { set_irq_chip(irq, &imx21_internal_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, IRQF_VALID); } for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOF(32); irq++) { set_irq_chip(irq, &imx21_gpio_chip); set_irq_handler(irq, do_edge_IRQ); set_irq_flags(irq, IRQF_VALID); } set_irq_chained_handler(INT_GPIO, imx21_gpio_handler); /* Disable all interrupts initially. */ /* In IMX21 this is done in the bootloader. */ }
static int dw_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); struct i2s_clk_config_data *config = &dev->config; u32 ccr, xfer_resolution, ch_reg, irq; int ret; switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: config->data_width = 16; ccr = 0x00; xfer_resolution = 0x02; break; case SNDRV_PCM_FORMAT_S24_LE: config->data_width = 24; ccr = 0x08; xfer_resolution = 0x04; break; case SNDRV_PCM_FORMAT_S32_LE: config->data_width = 32; ccr = 0x10; xfer_resolution = 0x05; break; default: dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt"); return -EINVAL; } config->chan_nr = params_channels(params); switch (config->chan_nr) { case EIGHT_CHANNEL_SUPPORT: ch_reg = 3; break; case SIX_CHANNEL_SUPPORT: ch_reg = 2; break; case FOUR_CHANNEL_SUPPORT: ch_reg = 1; break; case TWO_CHANNEL_SUPPORT: ch_reg = 0; break; default: dev_err(dev->dev, "channel not supported\n"); return -EINVAL; } i2s_disable_channels(dev, substream->stream); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution); i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); } else { i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution); i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); } i2s_write_reg(dev->i2s_base, CCR, ccr); config->sample_rate = params_rate(params); if (!dev->i2s_clk_cfg) return -EINVAL; ret = dev->i2s_clk_cfg(config); if (ret < 0) { dev_err(dev->dev, "runtime audio clk config fail\n"); return ret; } return 0; }
static void imx21_gpio_mask_irq(unsigned int irq) { DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq); IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32)); }
static void imx_gpio_unmask_irq(unsigned int irq) { DEBUG_IRQ("%s: irq %d\n", __func__, irq); IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32); }