void __bare_init __naked barebox_arm_reset_vector(void)
{
unsigned long r;
arm_cpu_lowlevel_init();
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0xa0000000 && r < 0xc0000000)
imx27_barebox_entry(0);
/* 399 MHz */
writel(IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0);
/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0);
writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
sdram_init();
imx27_barebox_boot_nand_external(0);
}
void __bare_init __naked barebox_arm_reset_vector(void)
{
uint32_t r;
volatile int v;
arm_cpu_lowlevel_init();
writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
for (v = 0; v < 0x4000; v++);
writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
MX31_CCM_CCMR);
writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
writel(MX31_PDR0_CSI_PODF(0xff1) | \
MX31_PDR0_PER_PODF(7) | \
MX31_PDR0_HSP_PODF(3) | \
MX31_PDR0_NFC_PODF(5) | \
MX31_PDR0_IPG_PODF(1) | \
MX31_PDR0_MAX_PODF(3) | \
MX31_PDR0_MCU_PODF(0), \
MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) |
IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd),
MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
MX31_CCM_SPCTL);
/*
* Configure IOMUXC
* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched),
* 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
* (behaviour copied by sha, source unknown)
*/
writel(0, 0x43fac26c);
writel(0, 0x43fac270);
writel(0, 0x43fac274);
writel(0x1000, 0x43fac27c);
for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
writel(0, r);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0x80000000 && r < 0xa0000000)
imx31_barebox_entry(0);
#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
#define ROWS0 ESDCTL0_ROW13
#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
#define ROWS0 ESDCTL0_ROW14
#endif
writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x12344321, MX31_CSD0_BASE_ADDR);
writel(0x12344321, MX31_CSD0_BASE_ADDR);
writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
#define ROWS1 ESDCTL0_ROW13
#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
#define ROWS1 ESDCTL0_ROW14
#endif
writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1);
writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00);
writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
writel(0x12344321, MX31_CSD1_BASE_ADDR);
writel(0x12344321, MX31_CSD1_BASE_ADDR);
writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33);
writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000);
writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1);
writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR);
writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
#endif
#ifdef CONFIG_NAND_IMX_BOOT
/* setup a stack to be able to call imx31_barebox_boot_nand_external() */
arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
imx31_barebox_boot_nand_external();
#else
imx31_barebox_entry(0);
#endif
}
static int pcm038_power_init(void)
{
int ret;
printf("initialising PLLs\n");
console_flush();
ret = pmic_power();
if (ret) {
printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
return 0;
}
/* wait for good power level */
udelay(100000);
#define CSCR_VAL CSCR_USB_DIV(3) | \
CSCR_SD_CNT(3) | \
CSCR_MSHC_SEL | \
CSCR_H264_SEL | \
CSCR_SSI1_SEL | \
CSCR_SSI2_SEL | \
CSCR_MCU_SEL | \
CSCR_ARM_SRC_MPLL | \
CSCR_SP_SEL | \
CSCR_ARM_DIV(0) | \
CSCR_FPM_EN | \
CSCR_SPEN | \
CSCR_MPEN
/*
* pll clock initialization - see section 3.4.3 of the i.MX27 manual
*/
MPCTL0 = IMX_PLL_PD(0) |
IMX_PLL_MFD(51) |
IMX_PLL_MFI(7) |
IMX_PLL_MFN(35); /* MPLL = 399 MHz */
SPCTL0 = IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
IMX_PLL_MFN(3); /* SPLL = 240 MHz */
/*
* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
* System clock (HCLK) = 133 MHz
*/
pll_wait();
CSCR = CSCR_VAL | CSCR_AHB_DIV(1) | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
pll_wait();
/* clock gating enable */
GPCR = 0x00050f08;
PCDR0 = 0x130410c3;
PCDR1 = 0x09030911;
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
return 0;
}
static noinline __noreturn void mx31moboard_startup(void)
{
uint32_t r;
volatile int c;
/* Enable IPU Display interface */
writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
for (c = 0; c < 0x4000; c++) ;
writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
MX31_CCM_CCMR);
writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
writel(MX31_PDR0_CSI_PODF(0x1ff) | \
MX31_PDR0_PER_PODF(7) | \
MX31_PDR0_HSP_PODF(3) | \
MX31_PDR0_NFC_PODF(5) | \
MX31_PDR0_IPG_PODF(1) | \
MX31_PDR0_MAX_PODF(3) | \
MX31_PDR0_MCU_PODF(0), \
MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0x33) |
IMX_PLL_MFI(0xa) | IMX_PLL_MFN(0x0C),
MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
MX31_CCM_SPCTL);
/*
* Configure IOMUXC
* Clears 0x43fa_c26c - 0x43fa_c2dc with 0,
* except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000)
* and 0x43fa_c280 (untouched)
* (behaviour copied by sha, source unknown)
*/
writel(0, 0x43fac26c); /* SDCLK */
writel(0, 0x43fac270); /* CAS */
writel(0, 0x43fac274); /* RAS */
writel(0x1000, 0x43fac27c); /* CSD0 */
/* DQM3, DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 */
for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
writel(0, r);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0x80000000 && r < 0xa0000000)
imx31_barebox_entry(NULL);
writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
writel(0x00695727, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
writel(0x92100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
writel(0xa2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0x12344321, MX31_CSD0_BASE_ADDR);
writel(0x12344321, MX31_CSD0_BASE_ADDR);
writel(0xb2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
writel(0x82226080, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
imx31_barebox_entry(NULL);
}
