// *************************************************************************************************
// Continuous TX - used for spectrum analysis and high current check
// *************************************************************************************************
void start_continuous_tx(void)
{
// Disable IRQ
INT_ENABLE(INUM_RFTXRX, INT_OFF);
INT_ENABLE(INUM_RF, INT_OFF);
#ifdef TX_SIMPLE_TEST
CHANNR = 0;
#else
// Send on far away channel
CHANNR = 0xFF;
#endif
// Max output power
PA_TABLE0 = RFTEST_OUTPUT_POWER_MAX;
// Packet length is 1
PKTLEN = 1;
// Write first byte to RFD register
RFD = 0x55;
// Transmit
STX();
}
void UART1_Write( const uint8_t byte)
{
INT_DISABLE();
*uart1_obj.txTail = byte;
uart1_obj.txTail++;
if (uart1_obj.txTail == (uart1_txByteQ + UART1_CONFIG_TX_BYTEQ_LENGTH))
{
uart1_obj.txTail = uart1_txByteQ;
}
uart1_obj.txStatus.s.empty = false;
if (uart1_obj.txHead == uart1_obj.txTail)
{
uart1_obj.txStatus.s.full = true;
}
INT_ENABLE();
if (IEC0bits.U1TXIE == false)
{
IEC0bits.U1TXIE = true ;
}
}
//-----------------------------------------------------------------------------
// See cul.h for a description of this function.
//-----------------------------------------------------------------------------
void culDmaInit(void){
// Clearing all channels
memset((void*)dmaChannel1to4, 0, sizeof(dmaChannel1to4));
// Clearing the DMA table
memset((void*)dmaTable, 0, sizeof(dmaTable));
// Clearing any arming of channels 1 to 4, but leaving staus of channel 0.
DMAARM &= DMA_CHANNEL_0;
// Clearing all starting of DMA channels 1 to 4, but leaving status of channel 0.
DMAREQ &= DMA_CHANNEL_0;
// Clearing all DMA interrupt flags of channels 1 to 4, but leaving status of channel 0.
DMAIRQ &= DMA_CHANNEL_0;
// Clearing the interrupt flag of the DMA and enabling DMA interrupt.
INT_SETFLAG(INUM_DMA, INT_CLR);
INT_ENABLE(INUM_DMA, INT_ON);
// Setting the address of the DMA descriptors
DMA_SET_ADDR_DESC1234(dmaChannel1to4);
} // ends culDmaInit()
void __init s3c4510b_init_irq(void)
{
int irq;
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &s3c4510b_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* mask and disable all further interrupts */
outl(INT_MASK_DIS, REG_INTMASK);
/* set all to IRQ mode, not FIQ */
outl(INT_MODE_IRQ, REG_INTMODE);
/* Clear Intrerrupt pending register */
outl( 0x1FFFFF, REG_INTPEND);
/*
* enable the gloabal interrupt flag, this should be
* safe now, all sources are masked out and acknowledged
*/
INT_ENABLE( INT_GLOBAL);
}
/*******************************************************************************
* ow_write_byte
*******************************************************************************/
void ow_write_byte(const _Gpio_Descriptor *Gpio, u8 Val)
{
u8 i;
INT_DISABLE();
for (i = 0 ; i < 8 ; i++) ow_write_bit(Gpio, (Val >> i) & 0x01);
INT_ENABLE();
}
/*******************************************************************************
* ow_read_byte
*******************************************************************************/
u8 ow_read_byte(const _Gpio_Descriptor *Gpio)
{
u8 i;
u8 val = 0;
INT_DISABLE();
for (i = 0 ; i < 8 ; i++) if (ow_read_bit(Gpio)) val |= 1 << i;
INT_ENABLE();
return(val);
}
/*******************************************************************************
* ow_reset
*******************************************************************************/
u8 ow_reset(const _Gpio_Descriptor *Gpio)
{
u8 val;
INT_DISABLE();
DQ_LO(Gpio);
OW_DELAY_480();
DQ_HI(Gpio);
OW_DELAY_70();
val = !DQ_VAL(Gpio);
OW_DELAY_410();
INT_ENABLE();
return(val); //1 = Dectected / 0 = Not detected
}
/******************************************************************************
* @fn initStopWatch
*
* @brief
* Initializes components for the stopwatch application example.
*
* Parameters:
*
* @param void
*
* @return void
*
******************************************************************************/
void initStopWatch(void)
{
//interrupts[INUM_T3] = stop_watch_T3_IRQ;
INIT_GLED();
SET_MAIN_CLOCK_SOURCE(CRYSTAL);
CLKCON &= ~0x38;
// Enabling overflow interrupt from timer 3
TIMER34_INIT(3);
halSetTimer34Period(3, 1000);
INT_ENABLE(INUM_T3, INT_ON);
TIMER34_ENABLE_OVERFLOW_INT(3,INT_ON);
INT_GLOBAL_ENABLE(INT_ON);
}
/*******************************************************************************
* @brief init timer. Mainly to start timer2, open timer interrupt.
* @author zhanggaoxin
* @date 2012-12-26
* @param T_VOID
* @return T_VOID
*******************************************************************************/
T_VOID timer_init(T_VOID)
{
T_U32 i;
for (i=0; i<TIMER_NUM_MAX; i++)
{
timer_data[i].state = TIMER_INACTIVE;
}
//关闭TIMER1，需要的时候启动TIMER1
//REG32(REG_TIMER1_CTRL) = CLK_TIMER1;
//REG32(REG_TIMER1_CTRL) |= (TIMER_LOAD_BIT | TIMER_ENABLE_BIT);
REG32(REG_TIMER2_CTRL) = CLK_TIMER2; //2ms timer
REG32(REG_TIMER2_CTRL) |= (TIMER_LOAD_BIT | TIMER_ENABLE_BIT);
//enable timer interrupt
INT_ENABLE(INT_EN_SYSCTL);
//INT_ENABLE_SCM(INT_EN_TIMER1); //关闭TIMER1
INT_ENABLE_SCM(INT_EN_TIMER2);
}
// *************************************************************************************************
// Test RF reception
// *************************************************************************************************
void test_rf(void)
{
u16 time1, time2, packet1, packet2, div;
s16 ref, delta;
u8 i;
s16 freqest;
u8 freqest1;
s16 freqest0;
u8 continue_test = YES;
// Config radio for RX
rftest_init();
// Set timeout in 1.5 seconds
reset_timer1();
set_timer1(32768*1.5);
T1CCTL0 = 0x44;
T1CTL = 0x02;
// Clear RF interrupts
S1CON &= ~(BIT1 | BIT0); // Clear MCU interrupt flag
RFIF &= ~BIT4; // Clear "receive/transmit done" interrupt
RFIM |= BIT4; // Enable "receive/transmit done" interrupt
// Enable IRQ
INT_ENABLE(INUM_RFTXRX, INT_ON);
INT_ENABLE(INUM_RF, INT_ON);
INT_ENABLE(INUM_T1, INT_ON);
// Clear test result variable
test_result = 0;
// Continue to receive packets until timeout
while ((rftest_count < RFTEST_PACKET_COUNT) && (!sTimer1.iflag))
{
// Start new RX if radio is IDLE
if (MARCSTATE == 0x01) SRX();
}
SIDLE();
// Analyze received packets
if (sTimer1.iflag || rftest_count < RFTEST_PACKET_COUNT/2)
{
// Timeout - no or not enough packets received
test_result = 0x8000;
continue_test = NO;
}
else
{
// Store last and first packet
for (i=0; i<RFTEST_PACKET_COUNT; i++)
{
if (rftest[i].valid)
{
time1 = rftest[i].time;
packet1 = rftest[i].packet_nb;
break;
}
}
for (i=RFTEST_PACKET_COUNT-1; i>0; i--)
{
if (rftest[i].valid)
{
time2 = rftest[i].time;
packet2 = rftest[i].packet_nb;
break;
}
}
// Calculate mean freqest
freqest = 0;
div = 0;
for (i=0; i<RFTEST_PACKET_COUNT; i++)
{
if (rftest[i].valid)
{
// Sign extend negative numbers
if ((rftest[i].freqoffset & BIT7) == BIT7)
{
freqest += (s16)(0xFF00 | rftest[i].freqoffset);
}
else
{
freqest += (s16)(rftest[i].freqoffset);
}
div++;
}
}
// FREQEST range check
freqest0 = freqest/(s16)div;
if ((freqest0 < RFTEST_FREQEST_MIN) || (freqest0 > RFTEST_FREQEST_MAX))
{
test_result = 0x2000 | (u8)freqest0;
continue_test = NO;
}
else
{ // FREQEST range ok
// Calculate distance between 1 and 2
// TX sends packet each 3276 ACLK ticks (= 1145 T1CLK ticks)
ref = (packet2 - packet1)*3276;
delta = time2 - time1;
if ((ref - delta) < RFTEST_ACLK_DEVIATION_MAX)
{
// Store ACLK deviation in test result
test_result = ((ref - delta)&0x0F) << 8;
// Store average FREQEST
if (freqest < 0)
{
freqest1 = (u8)((freqest*(-1))/div);
freqest1 = ~freqest1 + 1;
test_result |= freqest1;
}
else
{
test_result |= (u8)(freqest/div);
}
}
else if ((delta - ref) < RFTEST_ACLK_DEVIATION_MAX)
{
// Store ACLK deviation in test result
test_result = ((delta - ref)&0x0F) << 8;
// Store average FREQEST
if (freqest < 0)
{
freqest1 = (u8)((freqest*(-1))/div);
freqest1 = ~freqest1 + 1;
test_result |= freqest1;
}
else
{
test_result |= (u8)(freqest/div);
}
}
else
{
// Too high ACLK deviation
test_result = 0x4000;
continue_test = NO;
}
}
}
// 2nd test stage - use RF offset to catch another few packets
if (continue_test == YES)
{
rftest_count = 0;
// Clear RX variables
for (i=0; i<RFTEST_PACKET_COUNT; i++)
{
rftest[i].valid = 0;
rftest[i].time = 0;
rftest[i].packet_nb = 0;
rftest[i].freqoffset = 0;
}
// Set frequency offset
FSCTRL0 = freqest0;
// Set timeout in 0.5 seconds
reset_timer1();
set_timer1(32768*0.5);
// Try to receive just 1 packet
while ((rftest_count < 1) && (!sTimer1.iflag))
{
// Start new RX if radio is IDLE
if (MARCSTATE == 0x01) SRX();
}
SIDLE();
// Analyze received packets frequency offset - should be close to 0
if (rftest_count > 0)
{
if (!((rftest[0].freqoffset >= 0xFE) || (rftest[0].freqoffset <= 0x02)))
{
test_result = 0x1000;
}
}
else
{
test_result = 0x1000;
}
}
// Disable IRQ
INT_ENABLE(INUM_RFTXRX, INT_OFF);
INT_ENABLE(INUM_RF, INT_OFF);
INT_ENABLE(INUM_T1, INT_OFF);
// Stop Timer1
T1CTL = 0x00;
T1CNTL = 0x55;
reset_timer1();
}
/*!
* \brief Initialize system timer.
*
* This function is automatically called by Nut/OS
* during system initialization.
*
* Nut/OS uses on-chip timer 0 for its timer services.
* Applications should not modify any registers of this
* timer, but make use of the Nut/OS timer API. Timer 1
* and timer 2 are available to applications.
*/
void NutRegisterTimer(void (*handler) (void *))
{
os_handler = handler;
#if defined(MCU_AT91R40008)
/* Disable the Clock Counter */
outr(TC0_CCR, TC_CLKDIS);
/* Disable all interrupts */
outr(TC0_IDR, 0xFFFFFFFF);
/* Clear the status register. */
dummy = inr(TC0_SR);
/* Select divider and compare trigger */
outr(TC0_CMR, TC_CLKS_MCK32 | TC_CPCTRG);
/* Enable the Clock counter */
outr(TC0_CCR, TC_CLKEN);
/* Validate the RC compare interrupt */
outr(TC0_IER, TC_CPCS);
/* Disable timer 0 interrupts. */
outr(AIC_IDCR, _BV(TC0_ID));
/* Set the TC0 IRQ handler address */
outr(AIC_SVR(4), (unsigned int)Timer0Entry);
/* Set the trigg and priority for timer 0 interrupt */
/* Level 7 is highest, level 0 lowest. */
outr(AIC_SMR(4), (AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 0x4));
/* Clear timer 0 interrupt */
outr(AIC_ICCR, _BV(TC0_ID));
/* Enable timer 0 interrupts */
outr(AIC_IECR, _BV(TC0_ID));
/* Set compare value for 1 ms. */
outr(TC0_RC, 0x80F);
/* Software trigger starts the clock. */
outr(TC0_CCR, TC_SWTRG);
#elif defined(MCU_S3C4510B)
INT_DISABLE(IRQ_TIMER);
CSR_WRITE(TCNT0, 0);
CSR_WRITE(TDATA0, CLOCK_TICK_RATE);
CSR_WRITE(TMOD, TMOD_TIMER0_VAL);
CLEAR_PEND_INT(IRQ_TIMER);
NutRegisterIrqHandler(
&InterruptHandlers[IRQ_TIMER], handler, 0);
INT_ENABLE(IRQ_TIMER);
#elif defined(MCU_GBA)
/* Disable master interrupt. */
outw(REG_IME, 0);
/* Set global interrupt vector. */
NutRegisterIrqHandler(&sig_TMR3, Timer3Entry, 0);
/* Enable timer and timer interrupts. */
outdw(REG_TMR3CNT, TMR_IRQ_ENA | TMR_ENA | 48756);
/* Enable timer 3 interrupts. */
outw(REG_IE, inw(REG_IE) | INT_TMR3);
/* Enable master interrupt. */
outw(REG_IME, 1);
#else
#warning "MCU not defined"
#endif
}
////////////////////////////////////////////////////////////////////////////////
/// @brief Application main function.
////////////////////////////////////////////////////////////////////////////////
void main(void) {
// Initializations
SET_MAIN_CLOCK_SOURCE(CRYSTAL);
SET_MAIN_CLOCK_SPEED(MHZ_26);
CLKCON = (CLKCON & 0xC7);
init_peripherals();
P0 &= ~0x40; // Pulse the Codec Reset line (high to low, low to high)
P0 |= 0x40;
init_codec(); // Initilize the Codec
INT_SETFLAG(INUM_DMA, INT_CLR); // clear the DMA interrupt flag
I2SCFG0 |= 0x01; // Enable the I2S interface
DMA_SET_ADDR_DESC0(&DmaDesc0); // Set up DMA configuration table for channel 0
DMA_SET_ADDR_DESC1234(&DmaDesc1_4[0]); // Set up DMA configuration table for channels 1 - 4
dmaMemtoMem(AF_BUF_SIZE); // Set up DMA Channel 0 for memmory to memory data transfers
initRf(); // Set radio base frequency and reserve DMA channels 1 and 2 for RX/TX buffers
dmaAudio(); // Set up DMA channels 3 and 4 for the Audio In/Out buffers
DMAIRQ = 0;
DMA_ARM_CHANNEL(4); // Arm DMA channel 4
macTimer3Init();
INT_ENABLE(INUM_T1, INT_ON); // Enable Timer 1 interrupts
INT_ENABLE(INUM_DMA, INT_ON); // Enable DMA interrupts
INT_GLOBAL_ENABLE(INT_ON); // Enable Global interrupts
MAStxData.macPayloadLen = TX_PAYLOAD_LEN;
MAStxData.macField = MAC_ADDR;
while (1) { // main program loop
setChannel(channel[band][ActiveChIdx]); // SetChannel will set the MARCSTATE to IDLE
ActiveChIdx = (ActiveChIdx + 1) & 0x03;
SCAL(); // Start PLL calibration at new channel
if ((P1 & 0x08) != aux_option_status) { // if the 'SEL AUX IN' option bit has changed state
if ((P1 & 0x08) == 0) { // SEL AUX IN has changed state to true
I2Cwrite(MIC1LP_LEFTADC, 0xFC); // Disconnect MIC1LP/M from the Left ADC, Leave Left DAC enabled
I2Cwrite(MIC2L_MIC2R_LEFTADC, 0x2F); // Connect AUX In (MIC2L) to Left ADC
I2Cwrite(LEFT_ADC_PGA_GAIN, 0x00); // Set PGA gain to 0 dB
aux_option_status &= ~0x08;
}
else { // SEL AUX IN has changed state to false
I2Cwrite(MIC2L_MIC2R_LEFTADC, 0xFF); // Disconnect AUX In (MIC2L) from Left ADC
I2Cwrite(MIC1LP_LEFTADC, 0x84); // Connect the internal microphone to the Left ADC using differential inputs (gain = 0 dB); Power Up the Left ADC
I2Cwrite(LEFT_ADC_PGA_GAIN, 0x3C); // Enable PGA and set gain to 30 dB
aux_option_status |= 0x08;
}
}
if ((P1 & 0x04) != agc_option_status) { // if the 'ENA AGC' option bit has changed state
if ((P1 & 0x04) == 0) { // ENA AGC has changed state to true
I2Cwrite(LEFT_AGC_CNTRL_A, 0x90); // Left AGC Control Register A - Enable, set target level to -8 dB
I2Cwrite(LEFT_AGC_CNTRL_B, 0xC8); // Left AGC Control Register B - Set maximum gain to to 50 dB
I2Cwrite(LEFT_AGC_CNTRL_C, 0x00); // Left AGC Control Register C - Disable Silence Detection
agc_option_status &= ~0x04;
}
else { // SEL AUX IN has changed state to false
I2Cwrite(LEFT_AGC_CNTRL_A, 0x10); // Left AGC Control Register A - Disable
agc_option_status |= 0x04;
}
}
// Check the band selection bits
band = 2; // if the switch is not in position 1 or 2, in must be in position 3
if ((P1 & 0x10) == 0) // check if switch is in position 1
band = 0;
else if ((P0 & 0x04) == 0) // check if switch is in position 2
band = 1;
// Now wait for the "audio frame ready" signal
while (audioFrameReady == FALSE); // Wait until an audioframe is ready to be transmitted
audioFrameReady = FALSE; // Reset the flag
// Move data from the CODEC (audioOut) buffer to the TX buffer using DMA Channel 0
SET_WORD(DmaDesc0.SRCADDRH, DmaDesc0.SRCADDRL, audioOut[activeOut]);
SET_WORD(DmaDesc0.DESTADDRH, DmaDesc0.DESTADDRL, MAStxData.payload);
DmaDesc0.SRCINC = SRCINC_1; // Increment Source address
DMAARM |= DMA_CHANNEL_0;
DMAREQ |= DMA_CHANNEL_0; // Enable memory-to-memory transfer using DMA channel 0
while ((DMAARM & DMA_CHANNEL_0) > 0); // Wait for transfer to complete
while (MARCSTATE != 0x01); // Wait for calibration to complete
P2 |= 0x08; // Debug - Set P2_3 (TP2)
rfSendPacket(MASTER_TX_TIMEOUT_WO_CALIB);
P2 &= ~0x08; // Debug - Reset P2_3 (TP2)
} // end of 'while (1)' loop
}
//-----------------------------------------------------------------------------
// See cul.h for a description of this function.
//-----------------------------------------------------------------------------
BOOL sppInit(UINT32 frequency, BYTE address){
BYTE res = 0;
BOOL status = TRUE;
sppSetAddress(address);
// Clearing the states of the spp.
sppTxStatus = TX_IDLE;
sppRxStatus = RX_IDLE;
retransmissionCounter = 0;
ackTimerNumber = 0;
pAckData = 0;
// Clearing the RF interrupt flags and enable mask and enabling RF interrupts
RFIF = 0;
RFIM = 0;
INT_SETFLAG(INUM_RF,INT_CLR);
INT_ENABLE(INUM_RF,INT_ON);
// Setting the frequency and initialising the radio
res = halRfConfig(FREQUENCY_4_CC1110);
if(res == FALSE){
status = FALSE;
}
// Always in RX unless sending.
//debug:
MCSM1 = 0x2F;
// MCSM1 = 0x3F;
SRX();
// Using the timer 4 administrator to generate interrupt to check if a message is unacked...
culTimer4AdmInit();
// Initialising the DMA administrator
culDmaInit();
// Requesting a DMA channel for transmit data. No callback function is used. Instead the TX_DONE
// interrupt is used to determine when a transfer is finished. Configuring the DMA channel for
// transmit. The data address and length will be set prior to each specific transmission.
dmaTx = culDmaAllocChannel(&dmaNumberTx, 0);
if((dmaNumberTx == 0) || (dmaNumberTx > 4)){
status = FALSE;
}
culDmaToRadio(dmaTx, SPP_MAX_PAYLOAD_LENGTH + SPP_HEADER_AND_FOOTER_LENGTH, 0, FALSE);
// Requesting a DMA channel for receiving data. Giving the address of the callback function.
// Configuring the DMA channel for receive. The data address will be set prior to each specific
// reception.
dmaRx = culDmaAllocChannel(&dmaNumberRx, &rxCallBack);
if((dmaNumberRx == 0) || (dmaNumberRx > 4)){
status = FALSE;
}
culDmaFromRadio(dmaRx, 0, TRUE);
// Making sure that none of the channels are armed.
DMA_ABORT_CHANNEL(dmaNumberRx);
DMA_ABORT_CHANNEL(dmaNumberTx);
INT_ENABLE(INUM_DMA, INT_ON);
return status;
} // ends sppInit
static int __s3c4510b_open(struct net_device *dev)
{
unsigned long status;
/* Disable interrupts */
INT_DISABLE(INT_BDMARX);
INT_DISABLE(INT_MACTX);
/**
** install RX ISR
**/
__rx_irqaction.dev_id = (void *)dev;
status = setup_irq( INT_BDMARX, &__rx_irqaction);
if ( unlikely(status)) {
printk( KERN_ERR "Unabled to hook irq %d for ethernet RX\n", INT_BDMARX);
return status;
}
/**
** install TX ISR
**/
__tx_irqaction.dev_id = (void *)dev;
status = setup_irq( INT_MACTX, &__tx_irqaction);
if ( unlikely(status)) {
printk( KERN_ERR "Unabled to hook irq %d for ethernet TX\n", INT_MACTX);
return status;
}
/* setup DBMA and MAC */
outl( ETH_BRxRS, REG_BDMARXCON); /* reset BDMA RX machine */
outl( ETH_BTxRS, REG_BDMATXCON); /* reset BDMA TX machine */
outl( ETH_SwReset, REG_MACCON); /* reset MAC machine */
outl( sizeof( ETHFrame), REG_BDMARXLSZ);
outl( ETH_FullDup, REG_MACCON); /* enable full duplex */
/* init frame descriptors */
TxFDinit( dev);
RxFDinit( dev);
outl( (dev->dev_addr[0] << 24) |
(dev->dev_addr[1] << 16) |
(dev->dev_addr[2] << 8) |
(dev->dev_addr[3]) , REG_CAM_BASE);
outl( (dev->dev_addr[4] << 24) |
(dev->dev_addr[5] << 16) , REG_CAM_BASE + 4);
outl( 0x0001, REG_CAMEN);
outl( ETH_CompEn | /* enable compare mode (check against the CAM) */
ETH_BroadAcc, /* accept broadcast packetes */
REG_CAMCON);
INT_ENABLE(INT_BDMARX);
INT_ENABLE(INT_MACTX);
/* enable RX machinery */
outl( ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */
ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */
ETH_BRxMAINC | /* BDMA Rx Memory Address increment */
ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */
ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */
ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */
ETH_BRxLittle | /* BDMA Rx Little endian */
ETH_BRxWA10 | /* BDMA Rx Word Alignment- two invalid bytes */
ETH_BRxEn, /* BDMA Rx Enable */
REG_BDMARXCON);
outl( ETH_RxEn | /* enable MAC RX */
ETH_StripCRC | /* check and strip CRC */
ETH_EnCRCErr | /* interrupt on CRC error */
ETH_EnOver | /* interrupt on overflow error */
ETH_EnLongErr | /* interrupt on long frame error */
ETH_EnRxPar, /* interrupt on MAC FIFO parity error */
REG_MACRXCON);
netif_start_queue(dev);
return 0;
}
void s3c4510b_int_init()
{
IntPend = 0x1FFFFF;
IntMode = INT_MODE_IRQ;
INT_ENABLE(INT_GLOBAL);
}
void s3c4510b_unmask_irq(unsigned int irq)
{
INT_ENABLE(irq);
}
