/*FUNCTION**********************************************************************
*
* Function Name : FTM_DRV_Init
* Description : Initializes the FTM driver.
*
*END**************************************************************************/
ftm_status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t * info)
{
assert(instance < FTM_INSTANCE_COUNT);
assert(g_ftmBase[instance] != NULL);
FTM_Type *ftmBase = g_ftmBase[instance];
uint8_t chan = g_ftmChannelCount[instance];
/* clock setting initialization*/
CLOCK_SYS_EnableFtmClock(instance);
FTM_HAL_Reset(ftmBase);
/* Reset the channel registers */
for(int i = 0; i < chan; i++)
{
FTM_WR_CnSC(ftmBase, i, 0);
FTM_WR_CnV(ftmBase, i, 0);
}
FTM_HAL_Init(ftmBase);
FTM_HAL_SetSyncMode(ftmBase, info->syncMethod);
FTM_HAL_SetTofFreq(ftmBase, info->tofFrequency);
FTM_HAL_SetWriteProtectionCmd(ftmBase, info->isWriteProtection);
FTM_HAL_SetBdmMode(ftmBase,info->BDMMode);
NVIC_ClearPendingIRQ(g_ftmIrqId[instance]);
INT_SYS_EnableIRQ(g_ftmIrqId[instance]);
return kStatusFtmSuccess;
}
/*FUNCTION**********************************************************************
*
* Function Name : GPIO_DRV_InputPinInit
* Description : Initialize one GPIO input pin used by board.
*
*END**************************************************************************/
void GPIO_DRV_InputPinInit(const gpio_input_pin_user_config_t *inputPin)
{
/* Get actual port and pin number.*/
uint32_t port = GPIO_EXTRACT_PORT(inputPin->pinName);
uint32_t pin = GPIO_EXTRACT_PIN(inputPin->pinName);
uint32_t gpioBaseAddr = g_gpioBaseAddr[port];
uint32_t portBaseAddr = g_portBaseAddr[port];
/* Un-gate port clock*/
CLOCK_SYS_EnablePortClock(port);
/* Set current pin as digital input.*/
GPIO_HAL_SetPinDir(gpioBaseAddr, pin, kGpioDigitalInput);
/* Configure GPIO input features. */
PORT_HAL_SetPullCmd(portBaseAddr, pin, inputPin->config.isPullEnable);
PORT_HAL_SetPullMode(portBaseAddr, pin, inputPin->config.pullSelect);
PORT_HAL_SetPassiveFilterCmd(portBaseAddr, pin,
inputPin->config.isPassiveFilterEnabled);
#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
PORT_HAL_SetDigitalFilterCmd(portBaseAddr, pin,
inputPin->config.isDigitalFilterEnabled);
#endif
PORT_HAL_SetPinIntMode(portBaseAddr, pin, inputPin->config.interrupt);
/* Configure NVIC */
if ((inputPin->config.interrupt) && (g_portIrqId[port]))
{
/* Enable GPIO interrupt.*/
INT_SYS_EnableIRQ(g_portIrqId[port]);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : I2C_DRV_SlaveInit
* Description : initializes the I2C module.
* This function will save the application callback info, turn on the clock of
* I2C instance, setup according to user configuration.
*
*END**************************************************************************/
void I2C_DRV_SlaveInit(uint32_t instance,
const i2c_slave_user_config_t * userConfigPtr,
i2c_slave_state_t * slave)
{
assert(slave);
assert(instance < HW_I2C_INSTANCE_COUNT);
uint32_t baseAddr = g_i2cBaseAddr[instance];
/* Exit if current instance is already initialized. */
if (g_i2cStatePtr[instance])
{
return;
}
/* Init driver instance structure */
memset(slave, 0, sizeof(i2c_slave_state_t));
slave->slaveListening = userConfigPtr->slaveListening;
slave->slaveCallback = userConfigPtr->slaveCallback;
slave->callbackParam = userConfigPtr->callbackParam;
/* Enable clock for I2C.*/
CLOCK_SYS_EnableI2cClock(instance);
/* Init instance to known state. */
I2C_HAL_Init(baseAddr);
/* Set slave address.*/
I2C_HAL_SetAddress7bit(baseAddr, userConfigPtr->address);
/* Save runtime structure pointer.*/
g_i2cStatePtr[instance] = slave;
/* Create Event for irqSync */
OSA_EventCreate(&slave->irqEvent, kEventAutoClear);
#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT
/* Enable I2C START&STOP signal detect interrupt in the peripheral.*/
if(userConfigPtr->startStopDetect)
{
I2C_HAL_SetStartStopIntCmd(baseAddr,true);
}
#endif
#if FSL_FEATURE_I2C_HAS_STOP_DETECT
/* Enable STOP signal detect interrupt in the peripheral.*/
if(userConfigPtr->stopDetect)
{
I2C_HAL_SetStopIntCmd(baseAddr,true);
}
#endif
/* Enable I2C interrupt as default if setup slave listening mode */
I2C_HAL_SetIntCmd(baseAddr, slave->slaveListening);
/* Enable I2C interrupt from NVIC */
INT_SYS_EnableIRQ(g_i2cIrqId[instance]);
/* Enable the peripheral operation.*/
I2C_HAL_Enable(baseAddr);
}
/*FUNCTION**********************************************************************
*
* Function Name : SAI_DRV_RxInit
* Description : Initialize sai rx module, and initialize sai state.
*
*END**************************************************************************/
sai_status_t SAI_DRV_RxInit(uint32_t instance, sai_user_config_t * config, sai_state_t *state)
{
uint32_t reg_base = g_saiBaseAddr[instance];
/* Open clock gate for sai instance */
CLOCK_SYS_EnableSaiClock(instance);
/*Check if the device is busy */
if(sai_state_ids[instance][1] != NULL)
{
return kStatus_SAI_DeviceBusy;
}
sai_state_ids[instance][1] = state;
SAI_HAL_RxInit(reg_base);
/* Mclk source select */
if (config->slave_master == kSaiMaster)
{
SAI_HAL_SetMclkSrc(reg_base, config->mclk_source);
SAI_HAL_RxSetBclkSrc(reg_base, config->bclk_source);
}
SAI_HAL_RxSetSyncMode(reg_base, config->sync_mode);
SAI_HAL_RxSetMasterSlave(reg_base, config->slave_master);
SAI_HAL_RxSetProtocol(reg_base, config->protocol);
SAI_HAL_RxSetDataChn(reg_base, config->channel);
SAI_HAL_RxSetWatermark(reg_base, config->watermark);
/* Fill the state strucutre */
sai_state_ids[instance][1]->sync_mode = config->sync_mode;
sai_state_ids[instance][1]->fifo_channel = config->channel;
sai_state_ids[instance][1]->watermark = config->watermark;
sai_state_ids[instance][1]->master_slave = config->slave_master;
INT_SYS_EnableIRQ(g_saiRxIrqId[instance]);
return kStatus_SAI_Success;
}
void edma_dspi_rx_setup(uint32_t dmaChl, uint32_t destAddr)
{
// Configure the DMAMUX for eDMA channel
DMAMUX_HAL_SetChannelCmd(DMAMUX_BASE, dmaChl, false);
DMAMUX_HAL_SetTriggerSource(DMAMUX_BASE, dmaChl, kDmaRequestMux0SPI0Rx & 0xFF);
DMAMUX_HAL_SetChannelCmd(DMAMUX_BASE, dmaChl, true);
// Configure TCD
EDMA_HAL_HTCDClearReg(DMA_BASE, dmaChl);
edma_software_tcd_t stcd;
edma_transfer_config_t config;
config.destAddr = destAddr;
config.destLastAddrAdjust = 0;
config.destModulo = kEDMAModuloDisable;
config.destOffset = 4;
config.destTransferSize = kEDMATransferSize_4Bytes;
config.srcAddr = (uint32_t)&SPI0->POPR;
config.srcLastAddrAdjust = 0;
config.srcModulo = kEDMAModuloDisable;
config.srcOffset = 0;
config.srcTransferSize = kEDMATransferSize_4Bytes;
config.majorLoopCount = TEST_DATA_LEN;
config.minorLoopCount = 4;
EDMA_HAL_STCDSetBasicTransfer(DMA_BASE, &stcd, &config, true, true);
EDMA_HAL_PushSTCDToHTCD(DMA_BASE, dmaChl, &stcd);
// Configure interrupt
IRQn_Type irqNumber;
irqNumber = g_edmaIrqId[0][dmaChl];
INT_SYS_EnableIRQ(irqNumber);
}
void RTC_DRV_Init(uint32_t instance)
{
uint32_t rtcBaseAddr = g_rtcBaseAddr[instance];
/* Enable clock gate to RTC module */
CLOCK_SYS_EnableRtcClock( 0U);
/* Initialize the general configuration for RTC module.*/
RTC_HAL_Init(rtcBaseAddr);
RTC_HAL_Enable(rtcBaseAddr);
NVIC_ClearPendingIRQ(g_rtcIrqId[instance]);
NVIC_ClearPendingIRQ(g_rtcSecondsIrqId[instance]);
INT_SYS_EnableIRQ(g_rtcIrqId[instance]);
INT_SYS_EnableIRQ(g_rtcSecondsIrqId[instance]);
}
/*FUNCTION*********************************************************************
*
* Function Name : XBAR_DRV_Init
* Description : Initialize the XBAR module to the reset state. This API
* should be called before any operation of the XBAR module.
*
*END*************************************************************************/
xbar_status_t XBAR_DRV_Init(xbar_state_t * xbarStatePtr)
{
XBARA_Type * xbara_base = g_xbaraBase[0];
g_xbarState = xbarStatePtr;
/* Clear the state structure. */
memset(xbarStatePtr, 0, sizeof(xbar_state_t));
CLOCK_SYS_EnableXbarClock(XBARA_MODULE);
XBARA_HAL_Init(xbara_base);
#if !defined(FSL_FEATURE_XBAR_HAS_SINGLE_MODULE)
XBARB_Type * xbarb_base = g_xbarbBase[0];
CLOCK_SYS_EnableXbarClock(XBARB_MODULE);
XBARB_HAL_Init(xbarb_base);
#endif /* FSL_FEATURE_XBAR_HAS_SINGLE_MODULE */
/* Enable XBAR interrupt on NVIC level. */
INT_SYS_EnableIRQ(g_xbarIrqId[XBARA_MODULE]);
return kStatus_XBAR_Success;
}
/*See fsl_ftm_driver.h for documentation of this function.*/
void FTM_DRV_Init(uint8_t instance, ftm_user_config_t * info)
{
assert(instance < HW_FTM_INSTANCE_COUNT);
uint32_t ftmBaseAddr = g_ftmBaseAddr[instance];
uint8_t chan = FSL_FEATURE_FTM_CHANNEL_COUNTn(instance);
/* clock setting initialization*/
CLOCK_SYS_EnableFtmClock(instance);
FTM_HAL_Reset(ftmBaseAddr);
/* Reset the channel registers */
for(int i = 0; i < chan; i++)
{
HW_FTM_CnSC_WR(ftmBaseAddr, i, 0);
HW_FTM_CnV_WR(ftmBaseAddr, i, 0);
}
FTM_HAL_Init(ftmBaseAddr);
FTM_HAL_SetSyncMode(ftmBaseAddr, info->syncMethod);
FTM_HAL_SetTofFreq(ftmBaseAddr, info->tofFrequency);
FTM_HAL_SetWriteProtectionCmd(ftmBaseAddr, info->isWriteProtection);
FTM_HAL_SetBdmMode(ftmBaseAddr,info->BDMMode);
NVIC_ClearPendingIRQ(g_ftmIrqId[instance]);
INT_SYS_EnableIRQ(g_ftmIrqId[instance]);
}
/*FUNCTION*********************************************************************
*
* Function Name : PDB_DRV_Init
* Description : Initialize the PDB counter and trigger input for PDB module.
* It resets PDB registers and enables the clock for PDB. So it should be
* called before any operation to PDB module. After initialized, the PDB can
* ack as a triggered timer, which lays the foundation for other features in
* PDB module.
*
*END*************************************************************************/
pdb_status_t PDB_DRV_Init(uint32_t instance, const pdb_timer_config_t *userConfigPtr)
{
assert(instance < PDB_INSTANCE_COUNT);
PDB_Type * base = g_pdbBase[instance];
if (!userConfigPtr)
{
return kStatus_PDB_InvalidArgument;
}
/* Enable the clock gate from clock manager. */
CLOCK_SYS_EnablePdbClock(instance);
/* Reset the registers for PDB module to reset state. */
PDB_HAL_Init(base);
PDB_HAL_Enable(base);
PDB_HAL_ConfigTimer(base, userConfigPtr);
/* Configure NVIC. */
if (userConfigPtr->intEnable)
{
INT_SYS_EnableIRQ(g_pdbIrqId[instance] );/* Enable PDB interrupt in NVIC level.*/
}
else
{
INT_SYS_DisableIRQ(g_pdbIrqId[instance] );/* Disable PDB interrupt in NVIC level.*/
}
return kStatus_PDB_Success;
}
rtc_status_t RTC_DRV_Init(uint32_t instance)
{
RTC_Type *rtcBase = g_rtcBase[instance];
/* Enable clock gate to RTC module */
CLOCK_SYS_EnableRtcClock(0U);
/* Initialize the general configuration for RTC module.*/
RTC_HAL_Init(rtcBase);
RTC_HAL_Enable(rtcBase);
NVIC_ClearPendingIRQ(g_rtcIrqId[instance]);
NVIC_ClearPendingIRQ(g_rtcSecondsIrqId[instance]);
INT_SYS_EnableIRQ(g_rtcIrqId[instance]);
INT_SYS_EnableIRQ(g_rtcSecondsIrqId[instance]);
return kStatusRtcSuccess;
}
void gpioEnableWakeUp(void)
{
// enables falling edge interrupt for switch SWx
PORT_HAL_SetPinIntMode(BOARD_SW_LLWU_BASE, BOARD_SW_LLWU_PIN, kPortIntFallingEdge);
INT_SYS_EnableIRQ(BOARD_SW_LLWU_IRQ_NUM);
LLWU_HAL_ClearExternalPinWakeupFlag(LLWU_BASE_PTR, (llwu_wakeup_pin_t)BOARD_SW_LLWU_EXT_PIN);
LLWU_HAL_SetExternalInputPinMode(LLWU_BASE_PTR,kLlwuExternalPinFallingEdge, (llwu_wakeup_pin_t)BOARD_SW_LLWU_EXT_PIN);
}
OSStatus internal_uart_init( mico_uart_t uart, const mico_uart_config_t* config, ring_buffer_t* optional_rx_buffer )
{
#ifndef NO_MICO_RTOS
mico_rtos_init_semaphore(&uart_interfaces[uart].tx_complete, 1);
mico_rtos_init_semaphore(&uart_interfaces[uart].rx_complete, 1);
#else
uart_interfaces[uart].tx_complete = false;
uart_interfaces[uart].rx_complete = false;
#endif
MicoMcuPowerSaveConfig(false);
/* Configure the UART TX/RX pins */
configure_uart_pins(BOARD_APP_UART_INSTANCE);
#if ADD_OS_CODE
#ifndef NO_MICO_RTOS
if(config->flags & UART_WAKEUP_ENABLE){
current_uart = uart;
mico_rtos_init_semaphore( &uart_interfaces[uart].sem_wakeup, 1 );
mico_rtos_create_thread(NULL, MICO_APPLICATION_PRIORITY, "UART_WAKEUP", thread_wakeup, 0x100, ¤t_uart);
}
#endif
#endif
//OSA_Init();
#ifdef UART_IRQ_APP
/****************************************************************/
uartConfig.baudRate = 115200;
uartConfig.bitCountPerChar = kUart8BitsPerChar;
uartConfig.parityMode = kUartParityDisabled;
uartConfig.stopBitCount = kUartOneStopBit;
/***************************************************************/
UART_DRV_Init(BOARD_APP_UART_INSTANCE, &uartState, &uartConfig);
#else
userConfig_app.chnArbitration = kEDMAChnArbitrationRoundrobin;
userConfig_app.notHaltOnError = false;
uartConfig_app.bitCountPerChar = kUart8BitsPerChar;
uartConfig_app.parityMode = kUartParityDisabled;
uartConfig_app.stopBitCount = kUartOneStopBit;
uartConfig_app.baudRate = 115200;
EDMA_DRV_Init(&state_app, &userConfig_app);
UART_DRV_EdmaInit(BOARD_APP_UART_INSTANCE, &uartStateEdma_app, &uartConfig_app);
INT_SYS_EnableIRQ(g_uartRxTxIrqId[BOARD_APP_UART_INSTANCE]);
#endif
#if RING_BUFF_ON
if (optional_rx_buffer != NULL)
{
// Note that the ring_buffer should've been initialised first
uart_interfaces[uart].rx_buffer = optional_rx_buffer;
uart_interfaces[uart].rx_size = 0;
platform_uart_receive_bytes( uart, optional_rx_buffer->buffer, optional_rx_buffer->size, 0 );
}
#endif
MicoMcuPowerSaveConfig(true);
return kNoErr;
}
void Components_Init(void)
{
/*! DMA_controller Auto initialization start */
EDMA_DRV_Init(&DMA_controller_State,&DMA_controller_InitConfig0);
/*! DMA_controller Auto initialization end */
/*! OLED_SPI Auto initialization start */
DSPI_DRV_EdmaMasterInit(FSL_OLED_SPI, &OLED_SPI_MasterState, &OLED_SPI_MasterConfig, &OLED_SPI_dmaTcd);
DSPI_DRV_EdmaMasterConfigureBus(FSL_OLED_SPI, &OLED_SPI_BusConfig, &OLED_SPI_calculatedBaudRate);
/*! OLED_SPI Auto initialization end */
/*! FLASH_SPI Auto initialization start */
DSPI_DRV_EdmaMasterInit(FSL_FLASH_SPI, &FLASH_SPI_MasterState, &FLASH_SPI_MasterConfig, &FLASH_SPI_dmaTcd);
DSPI_DRV_EdmaMasterConfigureBus(FSL_FLASH_SPI, &FLASH_SPI_BusConfig, &FLASH_SPI_calculatedBaudRate);
/*! FLASH_SPI Auto initialization end */
/*! GPIO Auto initialization start */
GPIO_DRV_Init(NULL,NULL);
/*! GPIO Auto initialization end */
/*! KW40_UART Auto initialization start */
UART_DRV_Init(FSL_KW40_UART,&KW40_UART_State,&KW40_UART_InitConfig0);
/*! KW40_UART Auto initialization end */
/*! DEBUG_UART Auto initialization start */
UART_DRV_Init(FSL_DEBUG_UART,&DEBUG_UART_State,&DEBUG_UART_InitConfig0);
/*! DEBUG_UART Auto initialization end */
/*! FS_I2C Auto initialization start */
I2C_DRV_MasterInit(FSL_FS_I2C, &FS_I2C_MasterState);
I2C_DRV_MasterSetBaudRate(FSL_FS_I2C, &FS_I2C_MasterConfig);
/*! FS_I2C Auto initialization end */
/*! NFS_I2C Auto initialization start */
I2C_DRV_MasterInit(FSL_NFS_I2C, &NFS_I2C_MasterState);
I2C_DRV_MasterSetBaudRate(FSL_NFS_I2C, &NFS_I2C_MasterConfig);
/*! NFS_I2C Auto initialization end */
/*! PWR_Manager Auto initialization start */
// POWER_SYS_Init(powerConfigsArr, 2U, NULL , 0U);
INT_SYS_EnableIRQ(LLWU_IRQn);
/*! PWR_Manager Auto initialization end */
/*! CLOCK Auto initialization start */
RTC_DRV_Init(FSL_CLOCK);
/*! CLOCK Auto initialization end */
/*! BATTERY_ADC Auto initialization start */
ADC16_DRV_Init(FSL_BATTERY_ADC, &BATTERY_ADC_InitConfig);
ADC16_DRV_ConfigConvChn(FSL_BATTERY_ADC, 0U, &BATTERY_ADC_ChnConfig);
/*! BATTERY_ADC Auto initialization end */
/*! sensor_timer Auto initialization start */
LPTMR_DRV_Init(FSL_SENSOR_TIMER,&sensor_timer_State,&sensor_timer_cfg);
/*! sensor_timer Auto initialization end */
}
/*FUNCTION**********************************************************************
*
* Function Name : LPSCI_DRV_Init
* Description : This function initializes a LPSCI instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the LPSCI module, initialize the
* module to user defined settings and default settings, configure the IRQ state
* structure and enable the module-level interrupt to the core, and enable the
* LPSCI module transmitter and receiver.
* The following is an example of how to set up the lpsci_state_t and the
* lpsci_user_config_t parameters and how to call the LPSCI_DRV_Init function
* by passing in these parameters:
* lpsci_user_config_t lpsciConfig;
* lpsciConfig.clockSource = kClockLpsciSrcPllFllSel;
* lpsciConfig.baudRate = 9600;
* lpsciConfig.bitCountPerChar = kLpsci8BitsPerChar;
* lpsciConfig.parityMode = kLpsciParityDisabled;
* lpsciConfig.stopBitCount = kLpsciOneStopBit;
* lpsci_state_t lpsciState;
* LPSCI_DRV_Init(instance, &lpsciState, &lpsciConfig);
*
*END**************************************************************************/
lpsci_status_t LPSCI_DRV_Init(uint32_t instance,
lpsci_state_t * lpsciStatePtr,
const lpsci_user_config_t * lpsciUserConfig)
{
assert(lpsciStatePtr && lpsciUserConfig);
assert(instance < HW_UART0_INSTANCE_COUNT);
uint32_t baseAddr = g_lpsciBaseAddr[instance];
uint32_t lpsciSourceClock;
/* Exit if current instance is already initialized. */
if (g_lpsciStatePtr[instance])
{
return kStatus_LPSCI_Initialized;
}
/* Clear the state structure for this instance. */
memset(lpsciStatePtr, 0, sizeof(lpsci_state_t));
/* Save runtime structure pointer.*/
g_lpsciStatePtr[instance] = lpsciStatePtr;
/* Un-gate LPSCI module clock */
CLOCK_SYS_EnableLpsciClock(instance);
/* Set LPSCI clock source */
CLOCK_SYS_SetLpsciSrc(instance, lpsciUserConfig->clockSource);
/* Initialize LPSCI to a known state. */
LPSCI_HAL_Init(baseAddr);
/* Create Semaphore for txIrq and rxIrq. */
OSA_SemaCreate(&lpsciStatePtr->txIrqSync, 0);
OSA_SemaCreate(&lpsciStatePtr->rxIrqSync, 0);
lpsciSourceClock = CLOCK_SYS_GetLpsciFreq(instance);
/* Initialize LPSCI baud rate, bit count, parity and stop bit. */
LPSCI_HAL_SetBaudRate(baseAddr, lpsciSourceClock, lpsciUserConfig->baudRate);
LPSCI_HAL_SetBitCountPerChar(baseAddr, lpsciUserConfig->bitCountPerChar);
LPSCI_HAL_SetParityMode(baseAddr, lpsciUserConfig->parityMode);
#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT
LPSCI_HAL_SetStopBitCount(baseAddr, lpsciUserConfig->stopBitCount);
#endif
/* Enable LPSCI interrupt on NVIC level. */
INT_SYS_EnableIRQ(g_lpsciRxTxIrqId[instance]);
/* Finally, enable the LPSCI transmitter and receiver*/
LPSCI_HAL_EnableTransmitter(baseAddr);
LPSCI_HAL_EnableReceiver(baseAddr);
return kStatus_LPSCI_Success;
}
/*FUNCTION*********************************************************************
*
* Function Name : MMAU_DRV_Init
* Description : Initialize the MMAU module according to the userConfig
* structure. This API should be called before any operation of the MMAU module.
*
*END*************************************************************************/
mmau_status_t MMAU_DRV_Init(mmau_user_config_t * userConfigPtr)
{
MMAU_HAL_Init(MMAU);
MMAU_HAL_Config(MMAU, userConfigPtr);
/* Enable MMAU interrupt on NVIC level. */
INT_SYS_EnableIRQ(g_mmauIrqId[0]);
return kStatus_MMAU_Success;
}
/*************************************************************************
* Function Name: FTM2_init
* Parameters: none
* Return: none
* Description: FlexTimer 2 initialization
*************************************************************************/
void FTM2_init(void)
{
FTM_HAL_SetWriteProtectionCmd(FTM2_BASE_PTR, false);//false: Write-protection is disabled
FTM_HAL_Enable(FTM2_BASE_PTR, true);//true: all registers including FTM-specific registers are available
FTM_HAL_SetMod(FTM2_BASE_PTR, (uint16_t)0xffff);// Free running timer
FTM_HAL_SetClockSource(FTM2_BASE_PTR, kClock_source_FTM_SystemClk);//clock The FTM peripheral clock selection\n
FTM_HAL_SetClockPs(FTM2_BASE_PTR, kFtmDividedBy2); // system clock, divide by 2
FTM_HAL_EnableChnInt(FTM2_BASE_PTR, 0);//Enables the FTM peripheral timer channel(n) interrupt.
FTM_HAL_SetChnMSnBAMode(FTM2_BASE_PTR, 0, 1);//Sets the FTM peripheral timer channel mode.
INT_SYS_EnableIRQ(FTM2_IRQn);
set_irq_priority(FTM2_IRQn, ISR_PRIORITY_SLOW_TIMER);
}
/*FUNCTION**********************************************************************
*
* Function Name : LPUART_DRV_Init
* Description : This function initializes a LPUART instance for operation.
* This function will initialize the run-time state structure to keep track of
* the on-going transfers, ungate the clock to the LPUART module, initialize the
* module to user defined settings and default settings, configure the IRQ state
* structure and enable the module-level interrupt to the core, and enable the
* LPUART module transmitter and receiver.
* The following is an example of how to set up the lpuart_state_t and the
* lpuart_user_config_t parameters and how to call the LPUART_DRV_Init function
* by passing in these parameters:
* lpuart_user_config_t lpuartConfig;
* lpuartConfig.clockSource = kClockLpuartSrcPllFllSel;
* lpuartConfig.baudRate = 9600;
* lpuartConfig.bitCountPerChar = klpuart8BitsPerChar;
* lpuartConfig.parityMode = klpuartParityDisabled;
* lpuartConfig.stopBitCount = klpuartOneStopBit;
* lpuart_state_t lpuartState;
* LPUART_DRV_Init(instance, &lpuartState, &lpuartConfig);
*
*END**************************************************************************/
lpuart_status_t LPUART_DRV_Init(uint32_t instance, lpuart_state_t * lpuartStatePtr,
const lpuart_user_config_t * lpuartUserConfig)
{
assert(lpuartStatePtr && lpuartUserConfig);
assert(instance < LPUART_INSTANCE_COUNT);
uint32_t lpuartSourceClock;
LPUART_Type * base = g_lpuartBase[instance];
/* Exit if current instance is already initialized. */
if (g_lpuartStatePtr[instance])
{
return kStatus_LPUART_Initialized;
}
/* Clear the state struct for this instance. */
memset(lpuartStatePtr, 0, sizeof(lpuart_state_t));
/* Save runtime structure pointer.*/
g_lpuartStatePtr[instance] = lpuartStatePtr;
/* Set LPUART clock source */
CLOCK_SYS_SetLpuartSrc(instance, lpuartUserConfig->clockSource);
/* ungate lpuart module clock */
CLOCK_SYS_EnableLpuartClock(instance);
/* initialize the LPUART instance */
LPUART_HAL_Init(base);
/* Init the interrupt sync object. */
OSA_SemaCreate(&lpuartStatePtr->txIrqSync, 0);
OSA_SemaCreate(&lpuartStatePtr->rxIrqSync, 0);
/* LPUART clock source is either system clock or bus clock depending on the instance */
lpuartSourceClock = CLOCK_SYS_GetLpuartFreq(instance);
/* initialize the parameters of the LPUART config structure with desired data */
LPUART_HAL_SetBaudRate(base, lpuartSourceClock, lpuartUserConfig->baudRate);
LPUART_HAL_SetBitCountPerChar(base, lpuartUserConfig->bitCountPerChar);
LPUART_HAL_SetParityMode(base, lpuartUserConfig->parityMode);
LPUART_HAL_SetStopBitCount(base, lpuartUserConfig->stopBitCount);
/* finally, enable the LPUART transmitter and receiver */
LPUART_HAL_SetTransmitterCmd(base, true);
LPUART_HAL_SetReceiverCmd(base, true);
/* Enable LPUART interrupt. */
INT_SYS_EnableIRQ(g_lpuartRxTxIrqId[instance]);
return kStatus_LPUART_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : QUADTMR_DRV_Init
* Description : Initializes the Quad Timer driver.
* Initialize the Quad Timer registers, ungates the module clock and enables Quad Timer
* interrupt in the system interrupt controller.
*
*END**************************************************************************/
quadtmr_status_t QUADTMR_DRV_Init(uint32_t instance)
{
assert(instance < TMR_INSTANCE_COUNT);
TMR_Type *tmrBase = g_quadtmrBase[instance];
/* clock setting initialization*/
CLOCK_SYS_EnableQuadTmrClock(instance);
QUADTMR_HAL_Init(tmrBase);
NVIC_ClearPendingIRQ(g_quadtmrIrqId[instance]);
INT_SYS_EnableIRQ(g_quadtmrIrqId[instance]);
return kStatusQuadTmrSuccess;
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_DRV_MasterInit
* Description : Initialize a SPI instance for master mode operation.
* This function uses a CPU interrupt driven method for transferring data.
* This function initializes the run-time state structure to track the ongoing
* transfers, ungates the clock to the SPI module, resets and initializes the module
* to default settings, configures the IRQ state structure, enables
* the module-level interrupt to the core, and enables the SPI module.
*
*END**************************************************************************/
spi_status_t SPI_DRV_MasterInit(uint32_t instance, spi_master_state_t * spiState)
{
SPI_Type *base = g_spiBase[instance];
/* Clear the state for this instance.*/
memset(spiState, 0, sizeof(* spiState));
/* Enable clock for SPI*/
CLOCK_SYS_EnableSpiClock(instance);
/* configure the run-time state struct with the source clock value */
spiState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Reset the SPI module to it's default state, which includes SPI disabled */
SPI_HAL_Init(base);
/* Init the interrupt sync object.*/
OSA_SemaCreate(&spiState->irqSync, 0);
/* Set SPI to master mode */
SPI_HAL_SetMasterSlave(base, kSpiMaster);
/* Set slave select to automatic output mode */
SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput);
/* Set the SPI pin mode to normal mode */
SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[instance] != 0)
{
/* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
}
#endif
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_spiStatePtr[instance] = spiState;
/* Enable SPI interrupt.*/
INT_SYS_EnableIRQ(g_spiIrqId[instance]);
/* SPI system Enable*/
SPI_HAL_Enable(base);
return kStatus_SPI_Success;
}
/*!
* @cond DOXYGEN_PRIVATE
*
* @brief This function initializes caller allocated structure according to given
* numerical identifier of the timer.
*
* Called by hwtimer_init().
* Initializes the HWTIMER structure.
* Sets interrupt priority and registers ISR.
*
* @param hwtimer[in] Returns initialized hwtimer structure handle.
* @param pitId[in] Determines PIT module and pit channel.
* @param isrPrior[in] Interrupt priority for PIT
* @param data[in] Specific data. Not used in this timer.
*
* @return kHwtimerSuccess Success.
* @return kHwtimerInvalidInput When channel number does not exist in pit module.
* @return kHwtimerRegisterHandlerError When registration of the interrupt service routine failed.
*
* @see HWTIMER_SYS_PitDeinit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStart
* @see HWTIMER_SYS_PitStop
* @see HWTIMER_SYS_PitGetTime
* @see HWTIMER_SYS_PitIsr
* @see HWTIMER_SYS_PitIsrShared
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitInit(hwtimer_t * hwtimer, uint32_t pitId, uint32_t isrPrior, void *data)
{
uint32_t pitChannel;
uint32_t baseAddr = g_pitBaseAddr[0];
if (FSL_FEATURE_PIT_TIMER_COUNT < pitId)
{
return kHwtimerInvalidInput;
}
assert(NULL != hwtimer);
/* We need to store pitId of timer in context struct */
hwtimer->llContext[0U] = pitId;
pitChannel = hwtimer->llContext[0U];
/* Un-gate pit clock */
CLOCK_SYS_EnablePitClock(0U);
/* Enable PIT module clock */
PIT_HAL_Enable(baseAddr);
/* Allows the timers to be stopped when the device enters the Debug mode. */
PIT_HAL_SetTimerRunInDebugCmd(baseAddr, false);
/* Disable timer and interrupt */
PIT_HAL_StopTimer(baseAddr, pitChannel);
PIT_HAL_SetIntCmd(baseAddr, pitChannel, false);
/* Clear any pending interrupt */
PIT_HAL_ClearIntFlag(baseAddr, pitChannel);
/* Store hwtimer in global array */
g_hwtimersPit[pitChannel] = hwtimer;
/* Enable PIT interrupt.*/
if (kStatus_OSA_Success != OSA_InstallIntHandler(g_pitIrqId[pitChannel], HWTIMER_SYS_PitIsr))
{
return kHwtimerRegisterHandlerError;
}
PIT_HAL_SetIntCmd(baseAddr, pitChannel, true);
INT_SYS_EnableIRQ(g_pitIrqId[pitChannel]);
return kHwtimerSuccess;
}
/*!
* @brief initializes LLWU module
*/
void llwu_init(void)
{
/* Configure the interrupt vector for the interrupt handler */
INT_SYS_InstallHandler(LLW_IRQn, &llwu_isr);
/* Enable the IRQs */
INT_SYS_EnableIRQ(LLW_IRQn);
/* Configure the interrupt vector for the interrupt handler */
INT_SYS_InstallHandler(LPTimer_IRQn, &demo_lptmr_isr);
/*
* TWR_K22F120M and TWR_K64F120M: SW1,PTC6 LLWU_P10
* FRDM_K64F120M: SW2,PTC6 LLWU_P10
* FRDM_K22F120M: SW2,PTC1 LLWU_P6
*/
llwu_configure(LLWU_PIN_NUM, kLlwuExternalPinFallingEdge, kLlwuWakeupModule0);
}
void dspi_slave_setup(uint32_t instance, uint32_t baudrate)
{
dspi_data_format_config_t config;
uint32_t baseAddr = SPI0_BASE;
// Enable clock
CLOCK_SYS_EnableSpiClock(instance);
// Clear flags
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxAndRxStatus);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoDrainRequest);
// Enable HAL
DSPI_HAL_Init(baseAddr);
DSPI_HAL_SetMasterSlaveMode(baseAddr, kDspiSlave);
DSPI_HAL_Enable(baseAddr);
// Disable transfer
DSPI_HAL_StopTransfer(baseAddr);
// PCS popularity
DSPI_HAL_SetPcsPolarityMode(baseAddr, kDspiPcs0, kDspiPcs_ActiveLow);
// CTAR
DSPI_HAL_SetBaudRate(baseAddr, kDspiCtar0, baudrate, 72000000);
config.bitsPerFrame = 16;
config.clkPhase = kDspiClockPhase_FirstEdge;
config.clkPolarity = kDspiClockPolarity_ActiveHigh;
config.direction = kDspiMsbFirst;
DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &config);
// Interrupt
INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow, false);
DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest, false);
// DMA
DSPI_HAL_SetTxFifoFillDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateIntReq, true);
DSPI_HAL_SetRxFifoDrainDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateDmaReq, true);
}
/*FUNCTION**********************************************************************
*
* Function Name : GPIO_DRV_InputPinInit
* Description : Initialize one GPIO input pin used by board.
*
*END**************************************************************************/
void GPIO_DRV_InputPinInit(const gpio_input_pin_user_config_t *inputPin)
{
/* Get actual port and pin number.*/
uint32_t port = GPIO_EXTRACT_PORT(inputPin->pinName);
uint32_t pin = GPIO_EXTRACT_PIN(inputPin->pinName);
GPIO_Type * gpioBase = g_gpioBase[port];
PORT_Type * portBase = g_portBase[port];
/* Un-gate port clock*/
CLOCK_SYS_EnablePortClock(port);
/* Set current pin as gpio.*/
PORT_HAL_SetMuxMode(portBase, pin, kPortMuxAsGpio);
/* Set current pin as digital input.*/
GPIO_HAL_SetPinDir(gpioBase, pin, kGpioDigitalInput);
/* Configure GPIO input features. */
#if FSL_FEATURE_PORT_HAS_PULL_ENABLE
PORT_HAL_SetPullCmd(portBase, pin, inputPin->config.isPullEnable);
#endif
#if FSL_FEATURE_PORT_HAS_PULL_SELECTION
PORT_HAL_SetPullMode(portBase, pin, inputPin->config.pullSelect);
#endif
#if FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
PORT_HAL_SetPassiveFilterCmd(portBase, pin,
inputPin->config.isPassiveFilterEnabled);
#endif
#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
PORT_HAL_SetDigitalFilterCmd(portBase, pin,
inputPin->config.isDigitalFilterEnabled);
#endif
#if FSL_FEATURE_GPIO_HAS_INTERRUPT_VECTOR
PORT_HAL_SetPinIntMode(portBase, pin, inputPin->config.interrupt);
/* Configure NVIC */
if ((inputPin->config.interrupt) && (g_portIrqId[port]))
{
/* Enable GPIO interrupt.*/
INT_SYS_EnableIRQ(g_portIrqId[port]);
}
#endif
}
/*FUNCTION**********************************************************************
*
* Function Name : PIT_DRV_InitChannel
* Description : Initialize PIT channel.
* This function initialize PIT timers by channel. Pass in timer number and its
* config structure. Timers do not start counting by default after calling this
* function. Function PIT_DRV_StartTimer must be called to start timer counting.
* Call PIT_DRV_SetTimerPeriodByUs to re-set the period.
*
*END**************************************************************************/
void PIT_DRV_InitChannel(uint32_t instance,
uint32_t channel,
const pit_user_config_t * config)
{
assert(instance < PIT_INSTANCE_COUNT);
PIT_Type * base = g_pitBase[instance];
/* Set timer period.*/
PIT_DRV_SetTimerPeriodByUs(instance, channel, config->periodUs);
/* Enable or disable interrupt.*/
PIT_HAL_SetIntCmd(base, channel, config->isInterruptEnabled);
/* Configure NVIC*/
if (config->isInterruptEnabled)
{
/* Enable PIT interrupt.*/
INT_SYS_EnableIRQ(g_pitIrqId[channel]);
}
}
/*FUNCTION*********************************************************************
*
* Function Name : ADC16_DRV_Init
* Description : Initialize the comparator in ADC module. No mater if the
* calibration has been done for the device, this API with initial configuration
* should be called before any other operations to the ADC module. In fact,
* these initial configure are mainly for the comparator itself. For advanced
* feature, responding APIs would be called after this function.
*
*END*************************************************************************/
adc16_status_t ADC16_DRV_Init(uint32_t instance, const adc16_converter_config_t *userConfigPtr)
{
assert(instance < ADC_INSTANCE_COUNT);
ADC_Type * base = g_adcBase[instance];
if (!userConfigPtr)
{
return kStatus_ADC16_InvalidArgument;
}
/* Enable clock for ADC. */
CLOCK_SYS_EnableAdcClock(instance);
/* Reset all the register to a known state. */
ADC16_HAL_Init(base);
ADC16_HAL_ConfigConverter(base, userConfigPtr);
/* Enable ADC interrupt in NVIC level.*/
INT_SYS_EnableIRQ(g_adcIrqId[instance] );
return kStatus_ADC16_Success;
}
void RtcInit( void )
{
if ( RtcInitalized == false ) {
rtc_datetime_t datetime;
uint32_t srcClock = 0;
uint32_t seconds = 0;
uint16_t preScaler = 0;
uint64_t tmp = 0;
/* Enable clock gate to RTC module */
CLOCK_SYS_EnableRtcClock(0U);
/* Initialize the general configuration for RTC module.*/
RTC_HAL_Init (RTC_BASE_PTR);
/* Clear pending interrupts before enabling them */
NVIC_ClearPendingIRQ (RTC_IRQn);
INT_SYS_EnableIRQ(RTC_IRQn);
/* Configure RTC external clock */
CLOCK_SYS_RtcOscInit(0U, &rtcOscConfig);
// Set a start date time and start RT.
datetime.year = 2014U;
datetime.month = 12U;
datetime.day = 25U;
datetime.hour = 19U;
datetime.minute = 0;
datetime.second = 0;
RTC_HAL_ConvertDatetimeToSecs(&datetime, &seconds);
if ( (srcClock = CLOCK_SYS_GetRtcFreq(0U)) != 32768U ) {
/* As the seconds register will not increment every second, we need to adjust the value
* programmed to the seconds register */
tmp = (uint64_t) seconds * (uint64_t) srcClock;
preScaler = (uint32_t)(tmp & 0x7FFFU);
seconds = (uint32_t)(tmp >> 15U);
}
/*FUNCTION**********************************************************************
*
* Function Name : SLCD_DRV_Init
* Description : initializes the SLCD driver.
* This function will initialize the SLCD driver according to user configure
* structure including clock source, power supply, contrast, frame frequency,
* the clock divider of generating frame frequency, duty cycle, fault detection and
* frame frequency interrupt status, lower power work mode.
* Attention: Due to the register reset value depends on the reset type, so in order to avoid
* unexpected display, blank mode and SLCD pins are disabled in SLCD initialization.
*
*END**************************************************************************/
slcd_status_t SLCD_DRV_Init(uint32_t instance, const slcd_user_config_t* userConfigPtr)
{
assert(instance < LCD_INSTANCE_COUNT);
LCD_Type * base = g_slcdBase[instance];
if (!userConfigPtr)
{
return kStatus_SLCD_NullArgument;
}
CLOCK_SYS_EnableSlcdClock(instance); /*!< Enable SLCD clock */
SLCD_HAL_Init(base); /*!< Register value depends on the reset type, so initializes SLCD to reset states */
SLCD_HAL_ClockConfig(base, &userConfigPtr->clkConfig); /*!< Configures SLCD clock */
SLCD_HAL_VoltageAndPowerSupplyConfig(base, userConfigPtr->powerSupply, userConfigPtr->loadAdjust, userConfigPtr->trim); /*!< Configures SLCD voltage power supply load just and contrast */
SLCD_HAL_SetDutyCyc(base, userConfigPtr->dutyCyc); /*!< Configures SLCD duty cycles */
SLCD_HAL_SetLowPowerModeConfig(base, &userConfigPtr->workMode);
if(userConfigPtr->slcdIntEnable)
{
INT_SYS_EnableIRQ(g_slcdIrqId[instance]); /*!< Enable SLCD interrupt in NVIC */
}
return kStatus_SLCD_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : QSPI_DRV_Init
* Description : Init QSPI internal state and open clock for QSPI.
*
*END**************************************************************************/
qspi_status_t QSPI_DRV_Init(uint32_t instance, qspi_state_t * state)
{
if (state == NULL)
{
return kStatus_QSPI_Fail;
}
QuadSPI_Type * base = g_qspiBase[instance];
CLOCK_SYS_EnableQspiClock(instance);
QSPI_HAL_Init(base);
/* Configure internal state */
if (g_qspiState[instance])
{
return kStatus_QSPI_DeviceBusy;
}
else
{
g_qspiState[instance] = state;
}
/* Enable interrupt */
INT_SYS_EnableIRQ(g_qspiIrqId[instance]);
return kStatus_QSPI_Success;
}
/*!
* @brief main demo function.
*/
int main(void) {
demo_power_modes_t testVal = kDemoRun;
uint8_t mode;
power_manager_error_code_t ret = kPowerManagerSuccess;
uint32_t freq = 0;
rtc_datetime_t date =
{
.year = 2014U,
.month = 4U,
.day = 30U,
.hour = 14U,
.minute = 0U,
.second = 0U,
};
// Example of constant configuration
// It may save the space in RAM
const power_manager_user_config_t vlprConfig = {
.mode = kPowerManagerVlpr,
.sleepOnExitValue = false,
};
power_manager_user_config_t vlpwConfig = vlprConfig;
power_manager_user_config_t vlls0Config = vlprConfig;
power_manager_user_config_t vlls1Config = vlprConfig;
power_manager_user_config_t vlls2Config = vlprConfig;
power_manager_user_config_t vlls3Config = vlprConfig;
power_manager_user_config_t llsConfig = vlprConfig;
power_manager_user_config_t vlpsConfig = vlprConfig;
power_manager_user_config_t waitConfig = vlprConfig;
power_manager_user_config_t stopConfig = vlprConfig;
power_manager_user_config_t runConfig = vlprConfig;
power_manager_user_config_t hsrunConfig =
{
.mode = kPowerManagerHsrun,
};
// Initializes array of pointers to power manager configurations
power_manager_user_config_t const *powerConfigs[] =
{
&runConfig,
&waitConfig,
&stopConfig,
&vlprConfig,
&vlpwConfig,
&vlpsConfig,
&llsConfig,
&vlls0Config,
&vlls1Config,
&vlls2Config,
&vlls3Config,
&hsrunConfig
};
// User callback data
user_callback_data_t callbackData0;
// Initializes callback configuration structure for power manager
power_manager_callback_user_config_t callbackCfg0 = { callback0,
kPowerManagerCallbackBeforeAfter,
(power_manager_callback_data_t*) &callbackData0 };
// Initializes array of pointers to power manager callbacks
power_manager_callback_user_config_t * callbacks[] =
{ &callbackCfg0 };
// Initializes hardware
hardware_init();
// Make the current Clock Manager mode configuration 1 (default configuration)
/* Set clock configurations to clock manager. */
CLOCK_SYS_Init(g_defaultClockConfigurations, CLOCK_NUMBER_OF_CONFIGURATIONS,
clockCallbackTable, ARRAY_SIZE(clockCallbackTable));
CLOCK_SYS_UpdateConfiguration(CLOCK_RUN, kClockManagerPolicyForcible);
// select the 1Hz for RTC_CLKOUT
CLOCK_SYS_SetRtcOutSrc(kClockRtcoutSrc1Hz);
/* Enable clock gate to RTC module */
CLOCK_SYS_EnableRtcClock( 0U);
/* Initialize the general configuration for RTC module.*/
RTC_HAL_Init(RTC_BASE_PTR);
/* Need to check this here as the RTC_HAL_Init() may have issued a software reset on the
* module clearing all prior RTC OSC related setup */
if (!(RTC_HAL_IsOscillatorEnabled(RTC_BASE_PTR)))
{
BOARD_InitRtcOsc();
}
/* Enable the RTC Clock output */
RTC_HAL_SetClockOutCmd(RTC_BASE_PTR, true);
NVIC_ClearPendingIRQ(RTC_IRQn);
INT_SYS_EnableIRQ(RTC_IRQn);
//RTC_DRV_SetDatetime(0, &date);
RTC_HAL_SetDatetime(RTC_BASE_PTR, &date);
// Initializes GPIO driver for LEDs and buttons
GPIO_DRV_Init(switchPins, ledPins);
memset(&callbackData0, 0, sizeof(user_callback_data_t));
// initializes configuration structures
vlpwConfig.mode = kPowerManagerVlpw;
// VLLS0 mode is supported only by some SOCs.
vlls0Config.mode = kPowerManagerVlls0;
vlls1Config.mode = kPowerManagerVlls1;
vlls2Config.mode = kPowerManagerVlls2;
vlls3Config.mode = kPowerManagerVlls3;
// LLS3 mode retains all ram content so CPU wake up doesn't go through restart sequence
llsConfig.mode = kPowerManagerLls3;
vlpsConfig.mode = kPowerManagerVlps;
waitConfig.mode = kPowerManagerWait;
stopConfig.mode = kPowerManagerStop;
runConfig.mode = kPowerManagerRun;
hsrunConfig.mode = kPowerManagerHsrun;
// initialize power manager driver
POWER_SYS_Init(powerConfigs,
sizeof(powerConfigs)/sizeof(power_manager_user_config_t *),
callbacks,
sizeof(callbacks)/sizeof(power_manager_callback_user_config_t *));
// Enables LLWU interrupt
INT_SYS_EnableIRQ(LLWU_IRQn);
mode = kDemoRun - kDemoMin - 1;
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
if (ret != kPowerManagerSuccess)
{
PRINTF("POWER_SYS_SetMode(%u) returned unexpected status : %u\r\n",mode,ret);
}
while (1)
{
mode = 0;
CLOCK_SYS_GetFreq(kCoreClock, &freq);
PRINTF("\r\n#################### Power Manager Demo ####################\r\n\r\n");
PRINTF(" Core Clock = %dHz \r\n", freq);
displayPowerMode();
PRINTF("\r\nSelect the desired operation \r\n\r\n");
PRINTF("Press %c for enter: RUN - Normal RUN mode\r\n",kDemoRun);
PRINTF("Press %c for enter: Wait - Wait mode\r\n",kDemoWait);
PRINTF("Press %c for enter: Stop - Stop mode\r\n",kDemoStop);
PRINTF("Press %c for enter: VLPR - Very Low Power Run mode\r\n",kDemoVlpr);
PRINTF("Press %c for enter: VLPW - Very Low Power Wait mode\r\n",kDemoVlpw);
PRINTF("Press %c for enter: VLPS - Very Low Power Stop mode\r\n",kDemoVlps);
PRINTF("Press %c for enter: LLS3 - Low Leakage Stop mode\r\n",kDemoLls);
PRINTF("Press %c for enter: VLLS0 - Very Low Leakage Stop 0 mode\r\n",kDemoVlls0);
PRINTF("Press %c for enter: VLLS1 - Very Low Leakage Stop 1 mode\r\n",kDemoVlls1);
PRINTF("Press %c for enter: VLLS2 - Very Low Leakage Stop 2 mode\r\n",kDemoVlls2);
PRINTF("Press %c for enter: VLLS3 - Very Low Leakage Stop 3 mode\r\n",kDemoVlls3);
PRINTF("Press %c for enter: HSRUN - High Speed RUN mode\r\n",kDemoHsRun);
PRINTF("\r\nWaiting for key press..\r\n\r\n");
// Wait for user response
testVal = (demo_power_modes_t)GETCHAR();
if ((testVal >= 'a') && (testVal <= 'z'))
{
testVal -= 'a' - 'A';
}
if (testVal > kDemoMin && testVal < kDemoMax)
{
mode = testVal - kDemoMin - 1;
switch (testVal)
{
case kDemoWait:
if (POWER_SYS_GetCurrentMode() == kPowerManagerVlpr)
{
PRINTF("Can not go from VLPR to WAIT directly\r\n");
break;
}
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to WAIT directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Wait mode");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
break;
case kDemoStop:
if (POWER_SYS_GetCurrentMode() == kPowerManagerVlpr)
{
PRINTF("Can not go from VLPR to STOP directly\r\n");
break;
}
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to STOP directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Stop mode");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
// update Clock Mode
update_clock_mode(CLOCK_RUN);
break;
case kDemoVlpr:
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to VLPR directly\r\n");
break;
}
if(kPowerManagerVlpr != POWER_SYS_GetCurrentMode())
{
/*
If apps default CM config mode is not VLPR, but needs to enter VLPR, and real CM config
is not VLPR, then we need to update it to VLPR mode here. Otherwise pass through.
*/
update_clock_mode(CLOCK_VLPR);
PRINTF("Entering Very Low Power Run mode\r\n");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
}
else
{
PRINTF("Very Low Power Run mode already active\r\n");
}
break;
case kDemoVlpw:
if (POWER_SYS_GetCurrentMode() == kPowerManagerRun)
{
PRINTF("Can not go from RUN to VLPW directly\r\n");
break;
}
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to VLPW directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Very Low Wait mode");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
break;
case kDemoVlps:
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to VLPS directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Very Low Power Stop mode");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
if (POWER_SYS_GetCurrentMode() == kPowerManagerRun)
{
// update Clock Mode to Run
update_clock_mode(CLOCK_RUN);
}
CHECK_RET_VAL(ret, mode);
break;
case kDemoLls:
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to LLSx directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Low Leakage Stop mode 3");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
// Check the mode LLS was entered
if(kPowerManagerVlpr != POWER_SYS_GetCurrentMode())
{
update_clock_mode(CLOCK_RUN);
}
CHECK_RET_VAL(ret, mode);
break;
case kDemoVlls0:
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to VLLS0 directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Very Low Leakage Stop 0 mode");
PRINTF("Wake up goes through Reset sequence.\r\n");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
break;
case kDemoVlls1:
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to VLLS1 directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Very Low Leakage Stop 1 mode");
PRINTF("Wake up goes through Reset sequence.\r\n");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
break;
case kDemoVlls2:
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to VLLS2 directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Very Low Leakage Stop 2 mode");
PRINTF("Wake up goes through Reset sequence.\r\n");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
break;
case kDemoVlls3:
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
PRINTF("Can not go from HSRUN to VLLS3 directly\r\n");
break;
}
setWakeUpSource(selectWakeUpSource(testVal),"Very Low Leakage Stop 3 mode");
PRINTF("Wake up goes through Reset sequence.\r\n");
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
CHECK_RET_VAL(ret, mode);
break;
case kDemoRun:
/* Need to decrease clock frequence before back RUN mode from HSRUN */
if (POWER_SYS_GetCurrentMode() == kPowerManagerHsrun)
{
update_clock_mode(CLOCK_RUN);
}
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
if (ret != kPowerManagerSuccess)
{
PRINTF("POWER_SYS_SetMode(%u) returned unexpected status : %u\r\n",mode,ret);
}
else
{
update_clock_mode(CLOCK_RUN);
}
break;
case kDemoHsRun:
if (POWER_SYS_GetCurrentMode() == kPowerManagerVlpr)
{
PRINTF("Can not go from HSRUN to VLPR directly\r\n");
break;
}
ret = POWER_SYS_SetMode(mode, kPowerManagerPolicyAgreement);
if (ret != kPowerManagerSuccess)
{
PRINTF("POWER_SYS_SetMode(%u) returned unexpected status : %u\r\n",mode,ret);
}
else
{
update_clock_mode(CLOCK_HSRUN);
}
break;
default:
PRINTF("Wrong value");
break;
}
PRINTF("\r\nNext loop\r\n");
}
}
}
void eth_arch_enable_interrupts(void) {
enet_hal_config_interrupt(BOARD_DEBUG_ENET_INSTANCE_ADDR, (kEnetTxFrameInterrupt | kEnetRxFrameInterrupt), true);
INT_SYS_EnableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetRxfInt]]);
INT_SYS_EnableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetTxfInt]]);
}
