_mqx_int _bsp_aud_mclk_io_init(void)
{
IOMUXC_RGPIO(40) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT = IOMUXC_CCM_AUD_EXT_CLK_SELECT_INPUT_DAISY(2);
return MQX_OK;
}
/*FUNCTION*****************************************************************
*
* Function Name : lwgpio_set_attribute
* Returned Value : TRUE if successful, FALSE otherwise
* Comments :
* Sets attributes
*
*END*********************************************************************/
boolean lwgpio_set_attribute
(
/* Pin handle to get function from */
LWGPIO_STRUCT_PTR handle,
/* PORT attribute */
uint_32 attribute_id,
/* Attribute value */
uint_32 value
)
{
uint_32 temp = 0;
switch (attribute_id)
{
case(LWGPIO_ATTR_PULL_UP):
{
if (value == LWGPIO_AVAL_ENABLE)
{
/* select pull mode, enable pull mode */
temp = *handle->iomuxc_reg;
temp |= IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(1) | IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(1);
/* if pull down resistor is selected, change to 47k pull up */
if (!(temp & IOMUXC_SW_MUX_CTL_PAD_PAD_PUS_MASK))
{
temp = IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(1);
}
*handle->iomuxc_reg = temp;
}
else
{
*handle->iomuxc_reg &= ~IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK;
}
break;
}
case(LWGPIO_ATTR_PULL_DOWN):
{
if (value == LWGPIO_AVAL_ENABLE)
{
temp = *handle->iomuxc_reg;
/* select 100k pull down resistor */
temp &= ~(IOMUXC_SW_MUX_CTL_PAD_PAD_PUS_MASK);
/* select pull mode, enable pull mode */
temp |= IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(1) | IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(1);
*handle->iomuxc_reg = temp;
}
else
{
*handle->iomuxc_reg &= ~IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK;
}
break;
}
case(LWGPIO_ATTR_SLEW_RATE):
{
if (value == LWGPIO_AVAL_SLEW_RATE_SLOW)
{
*handle->iomuxc_reg |= IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(1);
}
else
{
*handle->iomuxc_reg &= ~(IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(1));
}
break;
}
case(LWGPIO_ATTR_OPEN_DRAIN):
{
if (value == LWGPIO_AVAL_ENABLE)
{
*handle->iomuxc_reg |= IOMUXC_SW_MUX_CTL_PAD_ODE(1);
}
else
{
*handle->iomuxc_reg &= ~(IOMUXC_SW_MUX_CTL_PAD_ODE(1));
}
break;
}
case(LWGPIO_ATTR_DRIVE_STRENGTH):
{
*handle->pcr_reg = \
(*handle->pcr_reg & (~IOMUXC_SW_MUX_CTL_PAD_PAD_DSE_MASK)) | \
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(value);
break;
}
default:
return FALSE;
}
return TRUE;
}
void _bsp_esai_io_init(void)
{
_bsp_esai_clocks_init();
IOMUXC_RGPIO(54) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_RGPIO(55) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_RGPIO(56) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(57) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(58) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(59) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK;
IOMUXC_RGPIO(60) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_RGPIO(61) =
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(2) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE_MASK |
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE_MASK;
IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_DAISY_MASK;
IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT =
(1 << IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_SHIFT) & IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_DAISY_MASK;
//Configure the DSPI0 to the mode of slave
IOMUXC_RGPIO(41) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
IOMUXC_RGPIO(42) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
IOMUXC_RGPIO(43) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
IOMUXC_RGPIO(44) =
IOMUXC_SW_MUX_CTL_PAD_PAD_IBE(1) |
IOMUXC_SW_MUX_CTL_PAD_PAD_OBE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PKE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_PUS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_DSE(7) |
IOMUXC_SW_MUX_CTL_PAD_PAD_HYS(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SRE(0) |
IOMUXC_SW_MUX_CTL_PAD_PAD_SPEED(3) |
IOMUXC_SW_MUX_CTL_PAD_PAD_MUX_MODE(1);
_bsp_aud_temp_codec_hw_init();
}
