static void
console_write_direct(struct console *co, const char *buf, unsigned int len)
{
int i;
unsigned long flags;
if (!port)
return;
local_irq_save(flags);
/* Send data */
for (i = 0; i < len; i++) {
/* LF -> CRLF */
if (buf[i] == '\n') {
while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*port->write = '\r';
}
/* Wait until transmitter is ready and send.*/
while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*port->write = buf[i];
}
/*
* Feed the watchdog, otherwise it will reset the chip during boot.
* The time to send an ordinary boot message line (10-90 chars)
* varies between 1-8ms at 115200. What makes up for the additional
* 90ms that allows the watchdog to bite?
*/
reset_watchdog();
local_irq_restore(flags);
}
static void
console_write_direct(struct console *co, const char *buf, unsigned int len)
{
int i;
unsigned long flags;
if (!port)
return;
local_irq_save(flags);
/* */
for (i = 0; i < len; i++) {
/* */
if (buf[i] == '\n') {
while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*port->write = '\r';
}
/* */
while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*port->write = buf[i];
}
/*
*/
reset_watchdog();
local_irq_restore(flags);
}
static void
console_write_direct(struct console *co, const char *buf, unsigned int len)
{
int i;
unsigned long flags;
local_irq_save(flags);
if (!port)
return;
/* Send data */
for (i = 0; i < len; i++) {
/* LF -> CRLF */
if (buf[i] == '\n') {
while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*port->write = '\r';
}
/* Wait until transmitter is ready and send.*/
while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*port->write = buf[i];
}
local_irq_restore(flags);
}
int
getDebugChar(void)
{
unsigned long readval;
do {
readval = *port->read;
} while (!(readval & IO_MASK(R_SERIAL0_READ, data_avail)));
return (readval & IO_MASK(R_SERIAL0_READ, data_in));
}
void
putDebugChar(int val)
{
while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*port->write = val;
}
void
putDebugChar(int val)
{
while(!(*DEBUG_READ & IO_MASK(R_SERIAL0_READ, tr_ready))) ;
;
*DEBUG_WRITE = val;
}
/* Handle multiple IRQs */
void do_multiple_IRQ(struct pt_regs* regs)
{
int bit;
unsigned masked;
unsigned mask;
unsigned ethmask = 0;
/* Get interrupts to mask and handle */
mask = masked = *R_VECT_MASK_RD;
/* Never mask timer IRQ */
mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
/*
* If either ethernet interrupt (rx or tx) is active then block
* the other one too. Unblock afterwards also.
*/
if (mask &
(IO_STATE(R_VECT_MASK_RD, dma0, active) |
IO_STATE(R_VECT_MASK_RD, dma1, active))) {
ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) |
IO_MASK(R_VECT_MASK_RD, dma1));
}
/* Block them */
*R_VECT_MASK_CLR = (mask | ethmask);
/* An extra irq_enter here to prevent softIRQs to run after
* each do_IRQ. This will decrease the interrupt latency.
*/
irq_enter();
/* Handle all IRQs */
for (bit = 2; bit < 32; bit++) {
if (masked & (1 << bit)) {
do_IRQ(bit, regs);
}
}
/* This irq_exit() will trigger the soft IRQs. */
irq_exit();
/* Unblock the IRQs again */
*R_VECT_MASK_SET = (masked | ethmask);
}
void do_multiple_IRQ(struct pt_regs* regs)
{
int bit;
unsigned masked;
unsigned mask;
unsigned ethmask = 0;
/* */
mask = masked = *R_VECT_MASK_RD;
/* */
mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
/*
*/
if (mask &
(IO_STATE(R_VECT_MASK_RD, dma0, active) |
IO_STATE(R_VECT_MASK_RD, dma1, active))) {
ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) |
IO_MASK(R_VECT_MASK_RD, dma1));
}
/* */
*R_VECT_MASK_CLR = (mask | ethmask);
/*
*/
irq_enter();
/* */
for (bit = 2; bit < 32; bit++) {
if (masked & (1 << bit)) {
do_IRQ(bit, regs);
}
}
/* */
irq_exit();
/* */
*R_VECT_MASK_SET = (masked | ethmask);
}
void
putDebugChar(int val)
{
if (!kgdb_port)
return;
while (!(*kgdb_port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
;
*kgdb_port->write = val;
}
static void
console_write_direct(struct console *co, const char *buf, unsigned int len)
{
int i;
/* Send data */
for (i = 0; i < len; i++) {
/* Wait until transmitter is ready and send.*/
while(!(*DEBUG_READ & IO_MASK(R_SERIAL0_READ, tr_ready)));
*DEBUG_WRITE = buf[i];
}
}
static void sd1303_init(void){
unsigned char i = 0;
unsigned char init_sequence[] = {
0x00, // Set Lower Column Address
0x10, // Set Higher Column Address
0x40, // Set Display Start Line
0x81, // Set Contrast Control
0x80, // 0 ~ 127
0xA1, // [A0]:column address 1 is
0xC0, // oben / unten
0xA4, // Display on
0xA6, // Normal Display
0xA8, // Set Multiplex Ratio
0x3f,
0xAD, // Set DC-DC
0x8A, // 8B=ON, 8A=Off
0xAF, // AF=ON , AE=OFF
0xD3, // Set Display Offset
0x00, // No offset
0xD5, // Set Clock Divide
0xd0,
0xD8, // Set Area Color On or Off
0x00, // Mono Mode
0xDA, // Set Pins Hardware
0x12,
0xDB, // Set VCOMH
0x00,
0xD9, // Set VP
0x22,
0xff};
genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g8_15dir);
*R_GEN_CONFIG = genconfig_shadow;
while(init_sequence[i] != 0xff){
sd1303_send(init_sequence[i], SD_CMD);
i++;
};
sd1303_cls();
}
