/*****************************************************************************
Prototype : HI_MPI_ISP_GetRegister
Description : get isp register, include extent memory.
Input : u32Addr **
pu32Value **
Output : None
Return Value :
Process :
Note :
History
1.Date : 2011/1/13
Author : x00100808
Modification : Created function
*****************************************************************************/
HI_S32 HI_MPI_ISP_GetRegister(ISP_DEV IspDev, HI_U32 u32Addr, HI_U32 *pu32Value)
{
ISP_CHECK_DEV(IspDev);
ISP_CHECK_POINTER(pu32Value);
*pu32Value = IO_READ32(u32Addr);
return HI_SUCCESS;
}
unsigned short read_pio_16(unsigned reg)
{
volatile unsigned *addr;
reg = ATABASE + (reg << 2);
addr = (unsigned *)reg;
return IO_READ32(addr);
}
HI_U8 IO_READ8(HI_U32 u32Addr)
{
HI_U32 u32Value;
if(((u32Addr>>REG_ACCESS_WIDTH_1) & 0x3) == 0)
{
u32Value = IO_READ32(u32Addr);
u32Value = (u32Value & 0x000000FF);
}
else if(((u32Addr>>REG_ACCESS_WIDTH_1) & 0x3) == 1)
static void phy_auto_negotiation_set(struct am_net_private *np)
{
unsigned int rint;
int s100,full,tmp;
switch(np->phy_Identifier)
{
case PHY_ATHEROS_8032:
rint=mdio_read(np->dev,np->phys[0],0x11);
s100=rint&(1<<14);
full=((rint)&(1<<13));
break;
case PHY_SMSC_8700:
case PHY_SMSC_8720:
default:
rint=mdio_read(np->dev,np->phys[0],31);
s100=rint&(1<<3);
full=((rint>>4)&1);
break;
}
if(full)
{
if (debug > 0)
printk("duplex\n");
//(*ETH_MAC_0_Configuration) |= 1<<11; // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp |= 1 << 11;
IO_WRITE32(tmp,np->base_addr +ETH_MAC_0_Configuration);
}
else
{
if (debug > 0)
printk("half duplex\n");
//(*ETH_MAC_0_Configuration) &= ~(1<<11) ; // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp &= ~(1 << 11);
IO_WRITE32(tmp, np->base_addr +ETH_MAC_0_Configuration);
}
mac_PLL_changed(np,s100?100:10);
return;
}
static void mdio_write(struct net_device *dev, int phyid, int reg, int val)
{
#define WR (1<<1)
#define MDCCLK (0x1) << 2 //our 130 MHz
#define BUSY 0x1
struct am_net_private *priv = netdev_priv(dev);
unsigned long busy = 0;
unsigned long reg4;
reg4 = phyid << 11 | reg << 6 | MDCCLK | WR | BUSY;
IO_WRITE32(val, priv->base_addr + ETH_MAC_5_GMII_Data);
do { //waiting the phy is ready to write ...
busy = IO_READ32(priv->base_addr + ETH_MAC_4_GMII_Addr);
} while (busy & 0x1);
IO_WRITE32(reg4, priv->base_addr + ETH_MAC_4_GMII_Addr);
do { //waiting the phy is ready to write ...
busy = IO_READ32(priv->base_addr + ETH_MAC_4_GMII_Addr);
} while (busy & 0x1);
}
void close_8193_NFI(void)
{
/*
1. Power off digital:
RG_NFI_PWR_CTRL[2] = 1 // disable clock
RG_NFI_PWR_CTRL[0] = 1 // en iso
RG_NFI_PWR_RST_B[0] = 0 // en reset
RG_NFI_PWR_CTRL[1] = 0 // turn off power
2. Power off analog
ADDR:0x134C BIT[1] =0
ADDR:0x1354 BIT[20] =0
*/
u32 value = 0;
printf("Close 8193 NFI Digital\n");
//power off digital
value = IO_READ32(0,RG_NFI_PWR_CTRL);
IO_WRITE32(0,RG_NFI_PWR_CTRL,(value | 0x4));
//IO_WRITE32(0,RG_NFI_PWR_CTRL,(value | 0x5));
value = IO_READ32(0,RG_NFI_PWR_CTRL);
IO_WRITE32(0,RG_NFI_PWR_CTRL,(value | 0x1));
value = IO_READ32(0,RG_NFI_PWR_RST_B);
IO_WRITE32(0,RG_NFI_PWR_RST_B,(value & 0xFFFFFFFE));
value = IO_READ32(0,RG_NFI_PWR_CTRL);
IO_WRITE32(0,RG_NFI_PWR_CTRL,(value & 0xFFFFFFFD));
printf("Close 8193 NFI Analog\n");
//power off analog
value = IO_READ32(0,0x134C);
IO_WRITE32(0,0x134C,(value & 0xFFFFFFFD));
//can not close power share power
//value = IO_READ32(0,0x1354);
//IO_WRITE32(0,0x1354,(value & 0xFFEFFFFF));
printf("Close 8193 NFI OK\n");
}
static int mdio_read(struct net_device *dev, int phyid, int reg)
{
#define WR (1<<1)
#define MDCCLK (0x1) << 2 //our 130 MHz
#define BUSY 0x1
struct am_net_private *priv = netdev_priv(dev);
unsigned long busy = 0;
unsigned long reg4;
unsigned long val = 0;
reg4 = phyid << 11 | reg << 6 | MDCCLK | BUSY;
/*
do{ //waiting the phy is ready to write ...
busy=IO_READ32(priv->base_addr+ETH_MAC_4_GMII_Addr);
}while(busy&0x1);
*/
IO_WRITE32(reg4, priv->base_addr + ETH_MAC_4_GMII_Addr);
do { //waiting the phy is ready to write ...
busy = IO_READ32(priv->base_addr + ETH_MAC_4_GMII_Addr);
} while (busy & 0x1);
val = IO_READ32(priv->base_addr + ETH_MAC_5_GMII_Data) & 0xffff;
return val;
}
static int mac_PLL_changed(struct am_net_private *np,int clk_mhz)
{
unsigned long tmp;
switch(clk_mhz)
{
case 0://disable clock
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, 1); //disable clk
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, (1 << 0 | 1 << 2 | 1 << 3));
break;
case 10:
if (debug > 0)
printk("10m\n");
//(*ETH_MAC_0_Configuration) &= ~(1<<14); // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp &= ~(1 << 14);
IO_WRITE32(tmp,np->base_addr +ETH_MAC_0_Configuration);
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, 1);
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, (1 << 1));
PERIPHS_SET_BITS(PREG_ETHERNET_ADDR0, 1);
break;
case 100:
default:
if (debug > 0)
printk("100m\n");
//(*ETH_MAC_0_Configuration) |= 1<<14; // program mac
tmp =
IO_READ32(np->base_addr +ETH_MAC_0_Configuration);
tmp |= 1 << 14;
IO_WRITE32(tmp,np->base_addr +ETH_MAC_0_Configuration);
PERIPHS_CLEAR_BITS(PREG_ETHERNET_ADDR0, 1);
PERIPHS_SET_BITS(PREG_ETHERNET_ADDR0, (1 << 1));
PERIPHS_SET_BITS(PREG_ETHERNET_ADDR0, 1);
}
udelay(10);
return 0;
}
/**********************
we do the basic rx tx operation irq;
FIXME:on SMP system..
************************/
void net_tasklet(unsigned long dev_instance)
{
struct net_device *dev = (struct net_device *)dev_instance;
struct am_net_private *np = netdev_priv(dev);
int len;
int result;
unsigned long flags;
#ifndef DMA_USE_SKB_BUF
struct sk_buff *skb = NULL;
#endif
spin_lock_irqsave(&np->lock, flags);
result=np->int_rx_tx;
np->int_rx_tx=0;
spin_unlock_irqrestore(&np->lock, flags);
if (!running)
goto release;
if (result & 1) {
struct _tx_desc *c_tx, *tx = NULL;
c_tx =(void *)IO_READ32(np->base_addr +ETH_DMA_18_Curr_Host_Tr_Descriptor);
c_tx=np->tx_ring+(c_tx-np->tx_ring_dma);
tx = np->start_tx;
CACHE_RSYNC(tx,sizeof(struct _tx_desc));
while (tx != NULL && tx != c_tx && !(tx->status & DescOwnByDma)) {
#ifdef DMA_USE_SKB_BUF
spin_lock_irqsave(&np->lock, flags);
if (tx->skb != NULL) {
//clear to next send;
if (np->tx_full) {
netif_wake_queue(dev);
np->tx_full = 0;
}
if(debug>2)
printk("send data ok len=%d\n",tx->skb->len);
dev_kfree_skb_any(tx->skb);
if(tx->buf_dma!=0)
dma_unmap_single(&dev->dev,tx->buf_dma,np->rx_buf_sz,DMA_TO_DEVICE);
tx->skb = NULL;
tx->buf = 0;
tx->buf_dma= 0;
tx->status = 0;
} else{
spin_unlock_irqrestore(&np->lock, flags);
break;
}
spin_unlock_irqrestore(&np->lock, flags);
#else
tx->status = 0;
CACHE_WSYNC(tx,sizeof(struct _tx_desc));
if (np->tx_full) {
netif_wake_queue(dev);
np->tx_full = 0;
}
#endif
tx = tx->next;
CACHE_RSYNC(tx,sizeof(struct _tx_desc));
}
np->start_tx = tx;
//data tx end... todo
}
if (result & 2) {
//data rx;
struct _rx_desc *c_rx, *rx = NULL;
c_rx =(void *)IO_READ32(np->base_addr +ETH_DMA_19_Curr_Host_Re_Descriptor);
c_rx=np->rx_ring+(c_rx-np->rx_ring_dma);
rx = np->last_rx->next;
while (rx != NULL) {
//if(rx->status !=IO_READ32(&rx->status))
// printk("error of D-chche!\n");
CACHE_RSYNC(rx,sizeof(struct _rx_desc));
if (!(rx->status & (DescOwnByDma))) {
int ip_summed = CHECKSUM_UNNECESSARY;
len = (rx->status & DescFrameLengthMask) >>DescFrameLengthShift;
if (unlikely(len < 18 || len > np->rx_buf_sz)) { //here is fatal error we drop it ;
np->stats.rx_dropped++;
np->stats.rx_errors++;
goto to_next;
}
if (unlikely(rx->status & (DescError))) { //here is not often occur
print_rx_error_log(rx->status);
//rx->status=DescOwnByDma;
if ((rx->status & DescRxIPChecksumErr) || (rx->status & DescRxTCPChecksumErr)) { //maybe checksum engine's problem;
//we set the NONE for ip/tcp need check it again
ip_summed = CHECKSUM_NONE;
} else {
np->stats.rx_dropped++;
np->stats.rx_errors++;
goto to_next;
}
}
len = len - 4; //clear the crc
#ifdef DMA_USE_SKB_BUF
if (rx->skb==NULL) {
printk("NET skb pointer error!!!\n");
break;
}
if (rx->skb->len>0) {
printk("skb have data before,skb=%p,len=%d\n",rx->skb,rx->skb->len);
rx->skb=NULL;
goto to_next;
}
skb_put(rx->skb, len);
rx->skb->dev = dev;
rx->skb->protocol =
eth_type_trans(rx->skb, dev);
/*we have checked in hardware;
we not need check again */
rx->skb->ip_summed = ip_summed;
if(rx->buf_dma!=0)
dma_unmap_single(&dev->dev,rx->buf_dma,np->rx_buf_sz,DMA_FROM_DEVICE);
rx->buf_dma=0;
netif_rx(rx->skb);
if(debug>3)
printk("receive skb=%p\n",rx->skb);
rx->skb=NULL;
#else
skb = dev_alloc_skb(len + 4);
if (skb == NULL) {
np->stats.rx_dropped++;
printk("error to alloc skb\n");
break;
}
skb_reserve(skb, 2);
skb_put(skb, len);
if(rx->buf_dma!=NULL)
dma_unmap_single(&dev->dev,(void *)rx->buf_dma,np->rx_buf_sz,DMA_FROM_DEVICE);
memcpy(skb->data, (void *)rx->buf, len);
skb->dev = dev;
skb->protocol = eth_type_trans(skb, dev);
skb->ip_summed = ip_summed;
netif_rx(skb);
#endif
dev->last_rx = jiffies;
np->stats.rx_packets++;
np->stats.rx_bytes += len;
//*/
if(debug>3)
printk("receive data len=%d\n",len);
//dump((unsigned char *)rx->buf,len);
//reset the rx_ring to receive
///
to_next:
#ifdef DMA_USE_SKB_BUF
if(rx->skb)
dev_kfree_skb_any(rx->skb);
rx->skb = dev_alloc_skb(np->rx_buf_sz + 4);
if (rx->skb==NULL) {
printk(KERN_ERR "error to alloc the skb\n");
rx->buf = 0;
rx->buf_dma= 0;
rx->status = 0;
rx->count = 0;
np->last_rx = rx;
CACHE_WSYNC(rx,sizeof(struct _rx_desc));
break;
}
if(debug>3)
printk("new malloc skb=%p\n",rx->skb);
skb_reserve(rx->skb, 2);
rx->buf = (unsigned long)rx->skb->data;
#endif
rx->buf_dma=dma_map_single(&dev->dev,(void *)rx->buf, (unsigned long)np->rx_buf_sz,DMA_FROM_DEVICE); //invalidate for next dma in;
rx->count =(DescChain) | (np->rx_buf_sz &DescSize1Mask);
rx->status = DescOwnByDma;
CACHE_WSYNC(rx,sizeof(struct _rx_desc));
np->last_rx = rx;
rx = rx->next;
} else {
break;
}
}
u32 mt8193_io_agent_test(void)
{
u32 u4Tmp = 0;
printk("[CKGEN] IO AGENT TEST ------------------------------------------ \n");
IO_WRITE32(0x1000, 0x500, 0x55555555);
u4Tmp = IO_READ32(0x1000, 0x500);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x1500\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1500. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x18, 0x55555555);
u4Tmp = IO_READ32(0x0, 0x18);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x18\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x18. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x0408, 0x55555555);
u4Tmp = IO_READ32(0x0, 0x408);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x408\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x408. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x0608, 0x55555555);
u4Tmp = IO_READ32(0x0, 0x608);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x608\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x608. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x0, 0x0a10, 0x55555555);
u4Tmp = IO_READ32(0x0, 0xa10);
if (u4Tmp == 0x00055555)
{
printk("[CKGEN] TEST PASS at 0xa10\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0xa10. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0x200, 0xaaaaffff);
u4Tmp = IO_READ32(0x1000, 0x200);
if (u4Tmp == 0xaaaaffff)
{
printk("[CKGEN] TEST PASS at 0x1200\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1200. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0x608, 0x05550555);
u4Tmp = IO_READ32(0x1000, 0x608);
if (u4Tmp == 0x05550555)
{
printk("[CKGEN] TEST PASS at 0x1608\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1608. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0x708, 0x55555555);
u4Tmp = IO_READ32(0x1000, 0x708);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x1708\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1708. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0xd00, 0x55555555);
u4Tmp = IO_READ32(0x1000, 0xd00);
if (u4Tmp == 0x55555555)
{
printk("[CKGEN] TEST PASS at 0x1d00\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1d00. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
IO_WRITE32(0x1000, 0xd00, 0xaaaaaaaa);
u4Tmp = IO_READ32(0x1000, 0xd00);
if (u4Tmp == 0xaaaaaaaa)
{
printk("[CKGEN] TEST PASS at 0x1d00\n");
}
else
{
printk("[CKGEN] TEST FAIL at 0x1d00. [0x%x] !!!!!!!!!!\n", u4Tmp);
}
printk("[CKGEN] IO AGENT TEST FINISH ------------------------------------------ \n");
return 0;
}
