/* Init and set seek LISR and HISR functions
* @param None.
* @return None
*/
void video_set_seek_isr(DECODE_TYPE decode_type)
{
kal_uint32 savedMask;
if((decode_type == DECODE_TYPE_MPEG4) || (decode_type == DECODE_TYPE_H263))
{
savedMask = SaveAndSetIRQMask();
#ifdef DRV_MP4_V1
IRQMask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQMask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
RestoreIRQMask(savedMask);
//savedMask = SaveAndSetIRQMask();
mpeg4_dec_init_isr_param();
g_mpeg4_dec_info_ptr->dec_state = MPEG4_DEC_STATE_SEEK;
#ifdef MP4_MOVE_LISR_TO_HISR
VISUAL_Register_HISR(VISUAL_MPEG4_SEEK_FIRST_HISR_ID, mpeg4_dec_seek_first_HISR);
#endif
VISUAL_Register_HISR(VISUAL_MP4_SEEK_HISR_ID, mpeg4_dec_seek_HISR);
#ifdef DRV_MP4_V1
IRQ_Register_LISR(IRQ_MPEG4_CODE, mpeg4_dec_seek_LISR, "MPEG4Seek");
IRQSensitivity(IRQ_MPEG4_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQ_Register_LISR(IRQ_MPEG4_DEC_CODE, mpeg4_dec_seek_LISR, "MPEG4Seek");
IRQSensitivity(IRQ_MPEG4_DEC_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
//RestoreIRQMask(savedMask);
}
}
/*************************************************************************
* FUNCTION
* EINT_Mask
*
* DESCRIPTION
* This function implements mask of dedicated external interrupt source
*
* CALLS
*
* PARAMETERS
* eintno - external interrupt vector number
*
* RETURNS
* No return
*
* GLOBALS AFFECTED
*
*************************************************************************/
void EINT_Mask(kal_uint8 eintno)
{
if (eint_is_dedicated & (1 << eintno))
{
eint_set_l1_eint_enable(eint_is_dedicated_map[eintno], EINT_DISABLE);
switch(eint_is_dedicated_map[eintno])
{
case DEDICATED_EINT0:
IRQMask(DEDICATED_EINT_IRQ0);
break;
case DEDICATED_EINT1:
IRQMask(DEDICATED_EINT_IRQ1);
break;
case DEDICATED_EINT2:
IRQMask(DEDICATED_EINT_IRQ2);
break;
case DEDICATED_EINT3:
IRQMask(DEDICATED_EINT_IRQ3);
break;
default:
return;
}
}
else
{
eint_set_irqen(eintno,EINT_DISABLE);
}
}
/* Init and set decode LISR and HISR functions
* @param None.
* @return None
*/
void video_set_dec_isr(DECODE_TYPE decode_type)
{
kal_uint32 savedMask;
if((decode_type == DECODE_TYPE_MPEG4) || (decode_type == DECODE_TYPE_H263))
{
savedMask = SaveAndSetIRQMask();
#ifdef DRV_MP4_V1
IRQMask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQMask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
RestoreIRQMask(savedMask);
//savedMask = SaveAndSetIRQMask();
mpeg4_dec_init_isr_param();
g_mpeg4_dec_info_ptr->dec_state = MPEG4_DEC_STATE_NORMAL;
#ifdef MP4_MOVE_LISR_TO_HISR
VISUAL_Register_HISR(VISUAL_MPEG4_DEC_FIRST_HISR_ID, mpeg4_dec_first_HISR);
#endif
VISUAL_Register_HISR(VISUAL_MPEG4_DEC_HISR_ID, mpeg4_dec_HISR);
//video_dec_set_enable_av_callback(mpeg4_dec_LISR);
//RestoreIRQMask(savedMask);
}
}
/*************************************************************************
* FUNCTION
* EINT_TIMER_CALLBACK
*
* DESCRIPTION
* This function implements main external interrupt LISR registered in
* global ISR jump table.
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* No return
*
* GLOBALS AFFECTED
*
*************************************************************************/
void EINT_TIMER_CALLBACK(void *data)
{
EINT_SW_DEBOUNCE_STRUCT *sw_debounce = (EINT_SW_DEBOUNCE_STRUCT *)data;
IRQMask(IRQ_EIT_CODE);
if(sw_debounce->eint_sw_debounce_handle != 0x7f)
{
DclSGPT_Control(sw_debounce->eint_sw_debounce_handle,SGPT_CMD_STOP,0);
DclSGPT_Close(&(sw_debounce->eint_sw_debounce_handle));
}
//EINT_PRINT("\tEINT_TIMER_CALLBACK, sw_debounce->eint_no = %d",sw_debounce->eint_no);
sw_debounce->eint_intr_allow = (sw_debounce->eint_intr_allow == KAL_TRUE)? KAL_FALSE: KAL_TRUE;
/*
* This timer is to avoid if interrupt status is changed but
* sw_debounce->eint_intr_allow is still in KAL_TRUE state
* because of no interrupt
*/
if (sw_debounce->eint_intr_allow)
{
SGPT_CTRL_START_T start;
start.u2Tick= eint_sw_debounce_time_delay[sw_debounce->eint_no];
start.pfCallback=EINT_TIMER_CALLBACK;
start.vPara=data;
sw_debounce->eint_sw_debounce_handle=DclSGPT_Open(DCL_GPT_CB,0);
DclSGPT_Control(sw_debounce->eint_sw_debounce_handle,SGPT_CMD_START,(DCL_CTRL_DATA_T*)&start);
}
IRQUnmask(IRQ_EIT_CODE);
EINT_UnMask(sw_debounce->eint_no);
}
void drv_idc_init_uart(void)
{
#if defined(MT6290)
DRV_WriteReg32(BASE_ADDR_MDINFRAMISC + 0x114, DRV_Reg32(BASE_ADDR_MDINFRAMISC + 0x114) | 0x6);
DRV_WriteReg32(BASE_ADDR_MDPERIMISC + 0x114, DRV_Reg32(BASE_ADDR_MDPERIMISC + 0x114) | 0x4);
#if __FPGA__
#else
// set GPIO as default output
DRV_WriteReg32_NPW(BASE_ADDR_TOPMISC + 0x1D4, DRV_Reg32(BASE_ADDR_TOPMISC + 0x1D4) | 0x200);
#endif
#endif
#if defined(MT6595)
// Enable GPIO 29, 30 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x110, DRV_Reg32(GPIO_base + 0x110) | 0x6000);
// Select GPIO 29, 30 pull-up
DRV_WriteReg32(GPIO_base + 0x210, DRV_Reg32(GPIO_base + 0x210) | 0x6000);
#endif
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_UART_INIT_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: IDC UART Init\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
// register isr, enable RX data receive interrupt
IRQMask(MD_IRQID_IDC2ARM);
// Initialize IDC UART FIFO threshold
drv_idc_set_fifo_trigger(1);
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
DRV_WriteReg32(IDC_UART_IER, IDC_UART_IER_ERBFI);
IRQ_Register_LISR(MD_IRQID_IDC2ARM, idc_uart_lisr, "IDC_UART");
DRV_Register_HISR(DRV_IDC_HISR_ID, idc_uart_hisr);
IRQSensitivity(MD_IRQID_IDC2ARM, KAL_FALSE);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_TRUE;
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_w_ptr = 3; // 2'b11
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
// Initialize baud rate
drv_idc_set_baudrate(4000000);
// initial flags/config of IDC driver
idc_port.main_state = IDC_IN_USE;
return;
}
void hif1_lisr(void)
{
#if defined (HIF1_CHANNEL_SUPPORT)
IRQMask(IRQ_HIF_1_CODE);
#endif
//(*(volatile kal_uint32*)HIF_INTSTA_REG(1)) = 0;//hif int status,write clear
HIF_INT_CLEAR(1);
hif_internal_handle[1].DMA_BUSY = KAL_FALSE;
#ifdef MTK_SLEEP_ENABLE
L1SM_SleepEnable(hif_sleepMode_handle[1]);//lock MD sleep mode
#endif
SLA_CustomLogging("HDM",0);//set for debug
if(hif_internal_handle[1].realtime_callback == KAL_TRUE)
{
if(hif_cb[1])
{
hif_cb[1]();
}
#if defined (HIF1_CHANNEL_SUPPORT)
IRQUnmask(IRQ_HIF_1_CODE);
#endif
}
else
drv_active_hisr((kal_uint8)DRV_HIF1_HISR_ID);
}
void idc_uart_lisr(kal_uint32 vector)
{
IRQMask(MD_IRQID_IDC2ARM);
drv_active_hisr((kal_uint8) DRV_IDC_HISR_ID);
return;
}
/* USB LOGGING DSP LISR */
static void USB_LOGGING_DSP1_LISR(void)
{
IRQMask(IRQ_IRDEBUG1_CODE);
drv_active_hisr(DRV_USB_LOGGING_DSP1_HISR_ID);
#if defined(DRV_USB_LOGGING_MT50)
if (SW_SEC_0 == INT_SW_SecVersion())
{
IRQ_ResetSWRegister(IRQ_IRDEBUG1_CODE);
}
#endif
}
kal_int32 cc_irq_mask(kal_uint32 index)
{
/* it is assumed that IRQ ID aligns index of CC IRQ!! */
/* Please check this during pre-sillicon. */
if (!CC_IRQ_RX_INDEX_IS_IN_RANGE(index))
{
return CC_IRQ_ERR_PARAM;
}
index = CC_IRQ_RX_INDEX_OFFSET(index);
IRQMask(CC_IRQ_INTR_ID_START + index);
return CC_IRQ_SUCCESS;
}
/* Disable decode interrupt
* @param None.
* @return None
*/
void video_dec_disable_irq(DECODE_TYPE decode_type)
{
kal_uint32 savedMask;
if((decode_type == DECODE_TYPE_MPEG4) || (decode_type == DECODE_TYPE_H263))
{
savedMask = SaveAndSetIRQMask();
#ifdef DRV_MP4_V1
IRQMask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQMask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
if(g_mpeg4_dec_isr_param.gpt_exception_protect_handle!=0)
g_mpeg4_dec_isr_param.b_gpt_active = KAL_FALSE;
RestoreIRQMask(savedMask);
if(g_mpeg4_dec_isr_param.gpt_exception_protect_handle!=0)
GPTI_StopItem(g_mpeg4_dec_isr_param.gpt_exception_protect_handle);
//video_dec_stop_av();
video_dec_set_av_callback(NULL);
}
}
/*-----------------------------------------------------------------------*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*------------------------------------------------------------------------*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_GPT_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
HGPT1_Callback();
}
if (GPT_Status & GPT_STS_2)
{
HGPT2_Callback();
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
/*
* FUNCTION
* GPT_Stop
*
* DESCRIPTION
* Stop GPT timer
*
* CALLS
* It is called to stop GPT timer
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_Stop(kal_uint8 timerNum)
{
kal_uint16 gpt_ctrl1;
kal_uint16 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
kal_uint16 gpt_ctrl3;
#endif
gpt_ctrl1 = DRV_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_Reg(GPT3_CTRL);
#endif
if (timerNum == 1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
if (timerNum == 2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
if (timerNum == 3)
{
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_WriteReg(GPT3_CTRL,gpt_ctrl3);
}
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)&& (!(gpt_ctrl3&GPT3_ENABLE)))
#else
if ( ((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0 )
#endif
{
kal_uint16 GPT_Status;
GPT_Status = DRV_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
#ifdef GPT_DRVPDN_FAST
DRVPDN_ENABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
}
}
/*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
GPTTimer.GPT_FUNC.gpt1_func();
}
if (GPT_Status & GPT_STS_2)
{
GPTTimer.GPT_FUNC.gpt2_func();
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
void drv_idc_close()
{
// stop all events before closing IDC
DRV_WriteReg32(IDC_BSI_SCH_STOP_3100, 0xFFFFFFFF);
DRV_WriteReg32(IDC_BSI_SCH_STOP_6332, 0xFFFFFFFF & ~0xFC000000);
// disable interrupt
IRQMask(MD_IRQID_IDC2ARM);
DRV_WriteReg8(IDC_UART_IER, IDC_UART_IER_ALLOFF);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_FALSE;
idc_port.rx_buf = 0;
// clear start/finish priority register
// clear start/finish priority bit enable register
// clear start/finish pattern register
// clear start/finish pattern bit enable register
DRV_WriteReg32(IDC_UART_START_PRI, 0);
DRV_WriteReg32(IDC_UART_START_PRI_BITEN, 0);
DRV_WriteReg32(IDC_UART_START_PAT, 0);
DRV_WriteReg32(IDC_UART_START_PAT_BITEN, 0);
DRV_WriteReg32(IDC_UART_FINISH_PRI, 0);
DRV_WriteReg32(IDC_UART_FINISH_PRI_BITEN, 0);
DRV_WriteReg32(IDC_UART_FINISH_PAT, 0);
DRV_WriteReg32(IDC_UART_FINISH_PAT_BITEN, 0);
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
idc_port.owner_id = 0;
idc_port.main_state = IDC_CLOSED;
return;
}
/*-----------------------------------------------------------------------*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*------------------------------------------------------------------------*/
extern void GPT_MS_Time_Out_Handler(kal_uint16 *ms_handle_sta); /*defined in dcl_gpt.c*/
extern kal_uint16 gpt_ms_lisr_handle_status; /*defined in dcl_gpt.c*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_GPT_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
HGPT1_Callback();
}
if (GPT_Status & GPT_STS_2)
{
/*--------*/
//add for 1ms GPT run in LISR context
GPT_MS_Time_Out_Handler(&gpt_ms_lisr_handle_status);
HGPT2_Callback(); /* always active hisr ,here may be some optimize */
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
void
idp_imgdma_rotdma0_LISR(void)
{
#if defined(__MTK_TARGET__) || defined(MDP_C_MODEL)
kal_uint32 reg;
#if !defined(MDP_C_MODEL)
IRQMask(IRQ_ROT_DMA_CODE);
#endif
reg = REG_IMGDMA_ROT_DMA_IRQ_FLAG & 0x00FF;
if (reg & IMGDMA_ROTDMA_IRQ_FLAG_0_BIT)
{
if (idp_imgdma_rotdma0_fend_intr_cb != NULL)
{
idp_imgdma_rotdma0_fend_intr_cb(idp_imgdma_rotdma0_fend_intr_cb_param);
}
}
#if defined(NO_SHRINK_ROTDMA_CODE)
if (reg & IMGDMA_ROTDMA_IRQ_FLAG_2_BIT)
{
if (idp_imgdma_rotdma0_q_empty_intr_cb != NULL)
{
idp_imgdma_rotdma0_q_empty_intr_cb(idp_imgdma_rotdma0_q_empty_intr_cb_param);
}
}
#endif
REG_IMGDMA_ROT_DMA_IRQ_FLAG_CLR = reg; //write clear
#if !defined(MDP_C_MODEL)
IRQUnmask(IRQ_ROT_DMA_CODE);
#endif
#endif // #if defined(__MTK_TARGET__) || defined(MDP_C_MODEL)
}
/**
* LCD interface LISR entry
*
* @param None.
*
* @return None.
*/
void lcd_LISR(void)
{
#if (!defined(MT6205B)&&!defined(MT6208))
kal_uint32 interrupt_status;
if (DRV_Reg(DRVPDN_CON1) & DRVPDN_CON1_LCD)
{
ASSERT(0);
}
IRQMask(IRQ_LCD_CODE);
interrupt_status=DRV_Reg(LCD_INT_STATUS_REG);
#ifdef IMAGE_DATA_PATH_TIMING_ANALYSIS
if (interrupt_status & LCD_INT_STATUS_COMPLETE_BIT) {
SLA_HWLogging("LCD", SA_stop);
}
#endif
#if !defined(DRV_IDP_SUPPORT)
lcd_transfer_complete = KAL_TRUE;
drv_active_hisr(DRV_LCD_HISR_ID);
#elif defined(DRV_IDP_SUPPORT)
if (interrupt_status & LCD_INT_STATUS_COMPLETE_BIT)
{
#ifdef __SYNC_LCM_SW_SUPPORT__
if ((KAL_TRUE == sync_lcm_enable_mode) &&
(LCD_HW_CMD_QUEUE_STATE == main_lcd_operation_state) &&
(KAL_FALSE == wait_lcd_restore_config_flag)) {
lcd_cmd_latch_complete = KAL_TRUE;
} else if (KAL_TRUE == wait_lcd_restore_config_flag) {
wait_lcd_restore_config_flag=KAL_FALSE;
}
/* wait one more lcd update trigger to make sure MMI's icon/menu is updated */
#endif
lcd_transfer_complete = KAL_TRUE;
#ifdef TV_OUT_SUPPORT
/*for TVout, configure TVout buffer address and LCD memory output address*/
if (TV_OUT_OWNER_LCD == tv_output_owner)
{
kal_bool update_next_buffer = KAL_TRUE;
if (0 == tv_out_current_fb)
{
if (tv_full_screen>1) /*MMI size*/
{
if (*((volatile unsigned int *) tv_output_buffer_offset_address1)!=tv_output_replace_data)
{
if (TV_OUTPUT_MODE1 == tv_output_config_data.tv_output_mode) {
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address1);
} else if (TV_OUTPUT_MODE4 == tv_output_config_data.tv_output_mode) {
tv_output_buffer_rotate=1;
}
lcd_mem_out_address_shadow1=tv_output_buffer_offset_address2;
*((volatile unsigned int *) tv_output_buffer_offset_address2)=tv_output_replace_data;
tv_full_screen--;
}
else
update_next_buffer = KAL_FALSE;
} else {
/// back to video size
if (TV_OUTPUT_MODE1 == tv_output_config_data.tv_output_mode) {
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address1);
} else if (TV_OUTPUT_MODE4 == tv_output_config_data.tv_output_mode) {
tv_output_buffer_rotate=1;
}
lcd_mem_out_address_shadow1=main_lcd_fb_update_para.tv_output_frame_buffer2_address;
}
}
else
{
if (tv_full_screen>1)/*MMI size*/
{
if (*((volatile unsigned int *) tv_output_buffer_offset_address2)!=tv_output_replace_data)
{
if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE1)
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address2);
else if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE4)
tv_output_buffer_rotate=2;
lcd_mem_out_address_shadow1=tv_output_buffer_offset_address1;
*((volatile unsigned int *) tv_output_buffer_offset_address1)=tv_output_replace_data;
tv_full_screen--;
}
else
update_next_buffer = KAL_FALSE;
}
else/*back to video size*/
{
if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE1)
tv_fb_update(TV_OUT_OWNER_LCD,tv_output_buffer_base_address2);
else if (tv_output_config_data.tv_output_mode==TV_OUTPUT_MODE4)
tv_output_buffer_rotate=2;
lcd_mem_out_address_shadow1=main_lcd_fb_update_para.tv_output_frame_buffer1_address;
}
}
if (KAL_TRUE == update_next_buffer)
{
tv_out_current_fb++;
tv_out_current_fb&=0x01;
tv_output_buffer_count++;
if (0xFF == tv_output_buffer_count)
{
tv_output_buffer_count=3;
}
/*When back to video size, we modify memory out addr in the HISR with ROI setting.
This can avoid video update issue(ROI and memory content are not sync) before
finishing ROI setting*/
if (tv_output_buffer_count!=2)
{
REG_LCD_ROI_WMEM_ADDR=lcd_mem_out_address_shadow1;
#ifdef __SYNC_LCM_SW_SUPPORT__
if (sync_lcm_enable_mode==KAL_TRUE)
{
if ((main_lcd_operation_state!=LCD_HW_CMD_QUEUE_STATE)||
(main_lcd_operation_state!=LCD_HW_UPDATE_SLEEP_STATE))
{
START_LCD_TRANSFER;
}
}
else
{
START_LCD_TRANSFER;
}
#else
START_LCD_TRANSFER;
#endif//__SYNC_LCM_SW_SUPPORT__
}
}
}
#endif
}
if (interrupt_status & LCD_INT_ENABLE_CMD_COMPLETE_BIT)
{
lcd_cmd_latch_complete=KAL_TRUE;
}
drv_active_hisr(DRV_LCD_HISR_ID);
#endif//DRV_IDP_SUPPORT
#endif//(!defined(MT6205B)&&!defined(MT6208))
} /* lcd_LISR() */
__attribute__((section ("INTSRAM_ROCODE"))) void mdci_lisr()
{
kal_uint32 arb, phy_chann, i, log_chann;
MDCI_BUFF_T *buff;
/* mask MDIF */
#if defined(MDIF_FOR_AP_SIDE)
IRQMask(IRQ_APMDIF_CODE);
#else
IRQMask(IRQ_MDIF_CODE);
#endif
/* get arbitration mode */
if (*MDIF_CON & MDIF_CON_ARB)
{
arb = 1;
}
else
{
arb = 0;
}
/* get physical channel which needs to be read */
phy_chann = *MDIF_RCHNUM;
//for (i = 0; i < MDIF_MAX_PHY; i++) {
for (i = mdci_readindx_for_MD; i < mdci_readindx_for_MD + MDIF_MAX_PHY; i++)
{
/* get logical channel one by one*/
if (phy_chann == 0) break;
i = i % MDIF_MAX_PHY;
/* get logical channel number */
if (arb == 0)
{
buff = (MDCI_BUFF_T *)MDIF_RXCHDATA + phy_chann;
log_chann = buff->channel;
i = phy_chann;
}
else if (phy_chann & (1 << i))
{
buff = (MDCI_BUFF_T *)MDIF_RXCHDATA + i;
log_chann = buff->channel;
}
else
{
continue;
}
/* validate logical channel */
if (log_chann == MDCI_FORCE_RESET_MODEM_CHANNEL)
{
#define FORCE_RESET_MODEM (0)
EXT_ASSERT(FORCE_RESET_MODEM, log_chann, phy_chann, 0);
}
else if (log_chann >= MDCI_MAX_CHANNEL)
{
EXT_ASSERT(0, log_chann, phy_chann, 0);
}
/* check state */
if (mdci_ctrl_pool[log_chann].state == MDCI_ACTIVE_READ)
{
/* use OR operation since a mdci_read() is waiting */
mdci_ctrl_pool[log_chann].state |= MDCI_ACTIVE_ISR;
}
else if (mdci_ctrl_pool[log_chann].state == MDCI_IDLE)
{
mdci_ctrl_pool[log_chann].state = MDCI_ACTIVE_ISR;
}
else if (mdci_ctrl_pool[log_chann].state == MDCI_ACTIVE_WRITE)
{
/* a mdci_write() is not finished */
EXT_ASSERT(0, phy_chann, log_chann, mdci_ctrl_pool[log_chann].state);
}
else if (mdci_ctrl_pool[log_chann].state == MDCI_ACTIVE_ISR)
{
/* a mdci_hisr() is not done yet */
if (arb == 0)
{
/* not allow in sequential mode */
EXT_ASSERT(0, phy_chann, log_chann, mdci_ctrl_pool[log_chann].state);
}
else
{
/* pend */
break; // KC: change the continue to break due to mdif phy race condition problem.
//continue;
}
}
else
{
EXT_ASSERT(0, phy_chann, log_chann, mdci_ctrl_pool[log_chann].state);
}
/* copy channel buffer */
kal_mem_cpy(&(mdci_ctrl_pool[log_chann].buff), buff, sizeof(MDCI_BUFF_T));
/* ack MDIF to release the physical channel */
*MDIF_ACK = (1 << i);
phy_chann &= ~(1<<i);
/* only one channel at one time under sequential mode */
if (arb == 0)
{
break;
}
}
mdci_readindx_for_MD = i;
#ifndef __IVP__
/* activate HISR */
if (KAL_TRUE == kal_query_systemInit())
{
#endif /* __IVP__ */
mdci_hisr();
#ifndef __IVP__
}
else
{
drv_active_hisr(DRV_MDIF_HISR_ID);
}
#endif /* __IVP__ */
}
DCL_STATUS drv_idc_set_pin_config(IDC_PIN_MODE_T pin_mode)
{
DCL_STATUS return_value = STATUS_FAIL;
#if defined(MT6752) || defined(MT6735)
// IRQMask to prevent unexpected interrupt
IRQMask(MD_IRQID_IDC2ARM);
if (pin_mode == IDC_INTERNAL_PIN)
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_INTERNAL_PIN_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Switch to internal pins\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
idc_port.pin_mode = IDC_INTERNAL_PIN;
// Switch to internal pins
#if defined(MT6752)
DRV_WriteReg32(GPIO_base + 0x500, DRV_Reg32(GPIO_base + 0x500) & ~(0x10));
#elif defined(MT6735)
DRV_WriteReg32(GPIO_base + 0x6D0, DRV_Reg32(GPIO_base + 0x6D0) & ~(0x20));
#endif
return_value = STATUS_OK;
}
else if (pin_mode == IDC_EXTERNAL_PIN)
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_EXTERNAL_PIN_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Switch to external pins\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
idc_port.pin_mode = IDC_EXTERNAL_PIN;
// Switch to external pins
#if defined(MT6752)
DRV_WriteReg32(GPIO_base + 0x500, DRV_Reg32(GPIO_base + 0x500) | 0x10);
#elif defined(MT6735)
DRV_WriteReg32(GPIO_base + 0x6D0, DRV_Reg32(GPIO_base + 0x6D0) | 0x20);
#endif
#if defined(MT6752)
// Enable GPIO37 (PTA_TX) pull-up/pull-down
DRV_WriteReg32(IOCFG_L_BASE+0xA0, DRV_Reg32(IOCFG_L_BASE+0xA0) | 0x20);
// Select GPIO37 (PTA_TX) pull-up
DRV_WriteReg32(IOCFG_L_BASE+0xD0, DRV_Reg32(IOCFG_L_BASE+0xD0) | 0x20);
// Enable GPIO130 (PTA_RX) pull-up/pull-down
DRV_WriteReg32(IOCFG_L_BASE+0x90, DRV_Reg32(IOCFG_L_BASE+0x90) | 0x40000);
// Select GPIO130 (PTA_RX) pull-up
DRV_WriteReg32(IOCFG_L_BASE+0xC0, DRV_Reg32(IOCFG_L_BASE+0xC0) | 0x40000);
#elif defined(MT6735)
// Enable GPIO1, 2 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x930, (DRV_Reg32(GPIO_base + 0x930) | (0x3 << 24)));
// Select GPIO1, 2 pull-up
DRV_WriteReg32(GPIO_base + 0x950, (DRV_Reg32(GPIO_base + 0x950) | (0x3 << 24)));
#endif
return_value = STATUS_OK;
}
// Clear TX/RX FIFO
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return return_value;
}
void drv_idc_set_dcb_config(IDC_CTRL_DCB_CONFIG_T idc_config)
{
kal_uint8 tmp_lcr, tmp_ier;
IRQMask(MD_IRQID_IDC2ARM);
tmp_ier = DRV_Reg8(IDC_UART_IER);
DRV_WriteReg8(IDC_UART_IER, IDC_UART_IER_ALLOFF);
IRQUnmask(MD_IRQID_IDC2ARM);
// set baud rate
drv_idc_set_baudrate(idc_config.u4Baud);
tmp_lcr = DRV_Reg32(IDC_UART_LCR);
tmp_lcr &= ~0x3F;
// set number of bits per character
switch(idc_config.u1DataBits)
{
case len_5:
tmp_lcr |= IDC_UART_WLS_5;
break;
case len_6:
tmp_lcr |= IDC_UART_WLS_6;
break;
case len_7:
tmp_lcr |= IDC_UART_WLS_7;
break;
case len_8:
tmp_lcr |= IDC_UART_WLS_8;
break;
default:
break;
}
switch(idc_config.u1StopBits)
{
case sb_1:
tmp_lcr |= IDC_UART_1_STOP;
break;
case sb_2:
tmp_lcr |= IDC_UART_2_STOP;
break;
case sb_1_5:
tmp_lcr |= IDC_UART_1_5_STOP;
break;
default:
break;
}
switch(idc_config.u1Parity)
{
case pa_none:
tmp_lcr |= IDC_UART_NONE_PARITY;
break;
case pa_odd:
tmp_lcr |= IDC_UART_ODD_PARITY;
break;
case pa_even:
tmp_lcr |= IDC_UART_EVEN_PARITY;
break;
default:
break;
}
DRV_WriteReg32(IDC_UART_LCR, tmp_lcr);
kal_mem_cpy((void *) &idc_port.DCB, (void *) &idc_config, sizeof(IDC_CTRL_DCB_CONFIG_T));
IRQMask(MD_IRQID_IDC2ARM);
DRV_WriteReg8(IDC_UART_IER, tmp_ier);
IRQUnmask(MD_IRQID_IDC2ARM);
}
/*
* FUNCTION
* IMGPROC_LISR_Entry
*
* DESCRIPTION
* Lisr for image processor(stands for filter mode)
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
void INTERN IMGPROC_LISR_Entry(void)
{
IRQMask(IRQ_IMGPROC_CODE);
visual_active_hisr(VISUAL_IMGPROC_HISR_ID);
}
/*-----------------------------------------------------------------------*
*
* It is called to stop GPT timer
*
*------------------------------------------------------------------------*/
static void GPT_Stop(kal_uint8 timerNum)
{
#if defined(DRV_GPT_STOP_2_STEP)
GPT_Stop_Step1(timerNum);
GPT_Stop_Step2();
#else
register kal_uint32 gpt_ctrl1;
register kal_uint32 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
register kal_uint32 gpt_ctrl3;
#endif
#if defined(DRV_GPT_GPT4)
register kal_uint32 gpt_ctrl4;
#endif
gpt_ctrl1 = DRV_GPT_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_GPT_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_GPT_Reg(GPT3_CTRL);
#endif
#if defined(DRV_GPT_GPT4)
gpt_ctrl4= DRV_GPT_Reg(GPT4_CTRL);
#endif
if (timerNum == GPT1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
else if (timerNum == GPT2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
else if (timerNum == GPT3)
{
#if !defined(GEMINI23C_EVB_BB)
kal_uint32 savedMask;
GPT3_UseCount--;
savedMask = SaveAndSetIRQMask();
if(GPT3_UseCount == 0)
{
#endif
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_GPT_WriteReg(GPT3_CTRL,gpt_ctrl3);
}
#if !defined(GEMINI23C_EVB_BB)
RestoreIRQMask(savedMask);
}
#endif
#endif /* defined(DRV_GPT_GPT3) */
#if defined(DRV_GPT_GPT4)
else if (timerNum == GPT4)
{
gpt_ctrl4 =(kal_uint16) ~GPT4_ENABLE;
DRV_GPT_WriteReg(GPT4_CTRL,gpt_ctrl4);
}
#endif
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)
#if defined(DRV_GPT_GPT3)
&& (!(gpt_ctrl3&GPT3_ENABLE))
#endif /* defined(DRV_GPT_GPT3) */
#if defined(DRV_GPT_GPT4)
&& (!(gpt_ctrl4&GPT4_ENABLE))
#endif /* defined(DRV_GPT_GPT4) */
)
if(KAL_TRUE==GPT_IsStop())
{
DRV_GPT_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
GPT_PDN_disable();
}
#endif //#if defined(DRV_GPT_STOP_2_STEP)
}
/* Note that this function should be called when first detect ms device*/
void USB_Host_Ms_State_Start(kal_uint8 ms_index)
{
kal_uint32 index;
kal_bool result;
// SGPT_CTRL_START_T start;
/* Initailize the information */
if(g_UsbHostMs[ms_index].event_id == 0)
g_UsbHostMs[ms_index].event_id = kal_create_event_group("USB_MS_EVEVT");
if(g_UsbHostMs[ms_index].mutex_id == 0)
g_UsbHostMs[ms_index].mutex_id = kal_create_mutex("USB_MS_MUTEX");
USB_GPTI_GetHandle(&(g_UsbHostMs[ms_index].gpt_handle));//DclSGPT_Open(DCL_GPT_CB, 0);//GPTI_GetHandle(&g_UsbHostMs.gpt_handle);
// if (g_UsbHostMs[ms_index].gpt_handle == 0)
// g_UsbHostMs[ms_index].gpt_handle = USB_GPTI_GetHandle();//DclSGPT_Open(DCL_GPT_CB, 0);//GPTI_GetHandle(&g_UsbHostMs.gpt_handle);
USB_GPTI_GetHandle(&(g_UsbHostMs[ms_index].sleep_timer_handle));//DclSGPT_Open(DCL_GPT_CB, 0);//GPTI_GetHandle(&g_UsbHostMs.gpt_handle);
// if (g_UsbHostMs[ms_index].sleep_timer_handle== 0)
// g_UsbHostMs[ms_index].sleep_timer_handle = USB_GPTI_GetHandle();//DclSGPT_Open(DCL_GPT_CB, 0);//GPTI_GetHandle(&g_UsbHostMs.gpt_handle);
/* Get LUN, it contains the error handling */
result = USB_Host_Ms_Comp_Get_LUN(ms_index);
if(result == KAL_TRUE)
{
/* The got LUN is total lun - 1 */
g_UsbHostMs[ms_index].total_lun++;
/* If LUN number is larger than we can support, onlt the first N can be detected */
if(g_UsbHostMs[ms_index].total_lun > USB_HOST_MS_SUPPORT_LUN)
g_UsbHostMs[ms_index].total_lun = USB_HOST_MS_SUPPORT_LUN;
}
else
{
/* when device not implement this command, it is only one LUN */
g_UsbHostMs[ms_index].dev_error_count = 0;
g_UsbHostMs[ms_index].total_lun = 1;
}
/* Reset all the LUN state to absent state */
for(index = 0; index < g_UsbHostMs[ms_index].total_lun; index++)
{
g_UsbHostMs[ms_index].media_info[index].state = USB_HOST_MS_MEDIA_STATE_ABSENT;
}
/* Get LUN is success, continue to query each LUN info */
result = USB_Host_Ms_Query_All_Media(ms_index);
/* If result is fail, ms has been detached */
if(result == KAL_TRUE)
{
/* Query each LUN is success, continue to check whether each LUN is in card slot or not */
result = USB_Host_Ms_Check_All_Media(ms_index);
/* If result is fail, ms has been detached */
}
drv_trace1(TRACE_FUNC, (kal_uint32)USB_HOST_MS_CHECK_MEDIA_STATE, g_UsbHostMs[ms_index].media_state_change);
USB_Dbg_Trace(USB_HOST_MS_REPORT_MEDIA_STATE, g_UsbHostMs[ms_index].media_state_change, (kal_uint32)g_UsbHostMs[ms_index].b_sending_change_ilm);
if(result == KAL_TRUE)
{
/* To prevent USB disconn intr coming during this moment */
IRQMask(USB_IRQ_MAP[g_UsbHostMs[ms_index].common_info.usb_ip_port]);
if((g_UsbHostMs[ms_index].media_state_change != 0)&&(g_UsbHostMs[ms_index].b_sending_change_ilm == KAL_FALSE))
{
USB_Host_Ms_Check_Media_State(ms_index);
}
/* If device is plugged out, do not send this message */
if(g_UsbHostMs[ms_index].dev_attatch == KAL_TRUE)
{
/* Start timer to query device state */
USB_GPTI_StartItem(g_UsbHostMs[ms_index].gpt_handle, USB_HOST_MS_QUERY_PERIOD,USB_Host_Ms_State_Timeout, &g_UsbHostMs);
// start.u2Tick =USB_HOST_MS_QUERY_PERIOD;
// start.pfCallback = USB_Host_Ms_State_Timeout;
// start.vPara = &g_UsbHostMs[ms_index];
// DclSGPT_Control((DCL_HANDLE)(g_UsbHostMs[ms_index].gpt_handle), SGPT_CMD_START, (DCL_CTRL_DATA_T*)&start);
}
if(USBD_Get_UnMask_Irq(g_UsbHostMs[ms_index].common_info) == KAL_TRUE)
IRQUnmask(USB_IRQ_MAP[g_UsbHostMs[ms_index].common_info.usb_ip_port]);
}
else
{
drv_trace0(TRACE_FUNC, (kal_uint32)USB_HOST_MS_STATE_START_FAIL);
}
}
void GPT_Stop_Step1(kal_uint8 timerNum)
{
register kal_uint32 gpt_ctrl1;
register kal_uint32 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
register kal_uint32 gpt_ctrl3;
#endif
#if defined(DRV_GPT_GPT4)
register kal_uint32 gpt_ctrl4;
#endif
gpt_ctrl1 = DRV_GPT_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_GPT_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_GPT_Reg(GPT3_CTRL);
#endif
#if defined(DRV_GPT_GPT4)
gpt_ctrl4 = DRV_GPT_Reg(GPT4_CTRL);
#endif
if (timerNum == 1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
else if (timerNum == 2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_GPT_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
else if (timerNum == 3)
{
#if !defined(GEMINI23C_EVB_BB)
GPT3_UseCount--;
if(GPT3_UseCount == 0)
{
#endif
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_GPT_WriteReg(GPT3_CTRL,gpt_ctrl3);
#if !defined(GEMINI23C_EVB_BB)
}
#endif
}
#endif //#if defined(DRV_GPT_GPT3)
#if defined(DRV_GPT_GPT4)
else if (timerNum == 4)
{
gpt_ctrl4 =(kal_uint16) ~GPT4_ENABLE;
DRV_GPT_WriteReg(GPT4_CTRL,gpt_ctrl4);
}
#endif //#if defined(DRV_GPT_GPT4)
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)
#if defined(DRV_GPT_GPT3)
&& (!(gpt_ctrl3&GPT3_ENABLE))
#endif /* defined(DRV_GPT_GPT3) */
#if defined(DRV_GPT_GPT4)
&& (!(gpt_ctrl4&GPT4_ENABLE))
#endif /* defined(DRV_GPT_GPT4) */
)
{
register kal_uint32 GPT_Status;
GPT_Status = DRV_GPT_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
}
}
static void USB_LOGGING_DSP2_LISR(void)
{
IRQMask(IRQ_IRDEBUG2_CODE);
drv_active_hisr(DRV_USB_LOGGING_DSP2_HISR_ID);
}
/*-----------------------------------*/
static int MountDevice(void * DriveData, int DeviceNumber, int DeviceType, DWORD Flags)
{
kal_uint8 retry = 0;
#if defined(__SIM_PLUS__)
sd_select_enum sel;
if((MSDC_HANDLE *)DriveData == &MSDC_Blk[0])
sel = SD_EXT;
else
{
sel = SD_SIM;
}
MSDC_Switch_Card(sel);
#endif
#ifdef DRV_LSD
/*notifiedFMT may be modified by FMT and MMI tasks, but it is no need to protect this, FMT can't preempt MMI*/
if(1 == notifiedFMT)/*in this state. we dont allow any access on memory card, we will return fail on any mount trial*/
{
return FS_MSDC_MOUNT_ERROR;
}
#endif
if(gMSDC_Handle->mIsInitialized)
return SECTOR_SIZE;
gMSDC_Handle->is_init_timeout = KAL_FALSE;
start:
if(!gMSDC_Handle->mIsPresent)
{
//dbg_print("not present \r\n");
#if defined(_NAND_FLASH_BOOTING_)
// add the following code for solving plug in or out the SD card during
// NFB loading process. The card detection interruptwill disapperared
// while interrupt controller is masked.
IRQMask(IRQ_MSDC_CODE);
if(*(volatile kal_uint16*)MSDC_PS & MSDC_PS_PIN0)
{
if(gMSDC_Handle->ins_level == MSDC_IOCTRL_PULL_UP)
gMSDC_Handle->mIsPresent = KAL_FALSE;
else
gMSDC_Handle->mIsPresent = KAL_TRUE;
}
else
{
if(gMSDC_Handle->ins_level == MSDC_IOCTRL_PULL_UP)
gMSDC_Handle->mIsPresent = KAL_TRUE;
else
gMSDC_Handle->mIsPresent = KAL_FALSE;
}
IRQUnmask(IRQ_MSDC_CODE);
#endif // _NAND_FLASH_BOOTING_
if(!gMSDC_Handle->mIsPresent)
{
MSDC_PDNControl(KAL_TRUE);
return FS_MSDC_MOUNT_ERROR;
}
}
MSDC_PDNControl(KAL_FALSE);
if(SD_Initialize() != NO_ERROR)
{
goto err_exit;
}
//if(SD_MountDevice(DeviceType) != FS_NO_ERROR)
//return FS_MSDC_MOUNT_ERROR;
//dbg_print("Mount success! \r\n");
#ifdef MSDC_SDMMC_NAND
/*for SDMMC NAND, some manufacturs sale NAND with all sectors zero, we should format it first*/
if(ReadSectors( DriveData, 0, 1, MSDC_Sector) != NO_ERROR)
goto err_exit;
if(0x55aa != (MSDC_Sector[128] & 0xffff0000)) { /*it doesn't have correct MBR*/
SD_SelfFormat();
}
else {
if(ReadSectors( DriveData, 1, 1, MSDC_Sector) != NO_ERROR)
goto err_exit;
if(0x55aa != (MSDC_Sector[128] & 0xffff0000)) { /*it doesn't have correct PBR*/
SD_SelfFormat();
}
}
#endif
MSDC_PDNControl(KAL_TRUE);
#ifdef DRV_LSD
if(KAL_TRUE == kal_query_systemInit()) { /*we don't let access memory card before FMT get plug in message*/
/*there is no task can access when system init*/
notifiedFMT = 1;
return FS_MSDC_MOUNT_ERROR;
}
#endif
return SECTOR_SIZE;
err_exit:
if(retry++ <= SD_MAX_RETRY && gMSDC_Handle->is_init_timeout == KAL_FALSE)
{
//dbg_print("SD MountDevice failed! retry: %d \r\n",retry);
goto start;
}
#if defined(__MSDC_NOT_SUPPORT_HOT_PLUG__)
gMSDC_Handle->mIsPresent = KAL_FALSE;
#endif
#if defined(__SIM_PLUS__)
if(INT_USBBoot() == KAL_TRUE && current_card == SD_SIM)
{
gMSDC_Handle->mIsPresent = KAL_FALSE;
}
#endif
MSDC_PDNControl(KAL_TRUE);
return FS_MSDC_MOUNT_ERROR;
}
/* get bytes from rx buffer, parameter status shows escape and break status
return value is the actually get bytes */
static kal_uint16 USB2UART_GetBytes(UART_PORT port, kal_uint8 *buffaddr, kal_uint16 length,
kal_uint8 *status, module_type ownerid)
{
kal_uint16 real_count;
// kal_uint16 index;
kal_uint16 RoomLeft;
kal_uint32 savedMask;
kal_uint32 error_count;
kal_int32 remain;
BUFFER_INFO *rx_info = &(USB2UARTPort.Rx_Buffer);
if(ownerid != USB2UARTPort.ownerid)
{
#ifdef __PRODUCTION_RELEASE__
return 0;
#else /* __PRODUCTION_RELEASE__ */
EXT_ASSERT( 0, (kal_uint32) ownerid, USB2UARTPort.ownerid, 0);
#endif
}
/* return directly if not match condition */
if ( (gUsbDevice.device_type != USB_CDC_ACM) ||
(USB2UARTPort.initialized == KAL_FALSE) || (gUsbDevice.nDevState!=DEVSTATE_CONFIG))
return 0;
/* determine real data count */
/* Note that the area to determine send_Rxilm must also contain in critical section.
Otherwise if USB HISR activated before send_Rxilm setting as true,
this message will be lost */
savedMask = SaveAndSetIRQMask();
Buf_GetBytesAvail(rx_info, real_count);
if(real_count >= length)
{
real_count = length;
}
else
{
g_UsbACM.send_Rxilm = KAL_TRUE; /*After this time get byte, buffer will be empty */
}
RestoreIRQMask(savedMask);
#ifndef __PRODUCTION_RELEASE__
if(g_UsbACM.send_Rxilm == KAL_TRUE)
{
drv_trace1(TRACE_FUNC, USBACM_GET_BYTES_BUF_EMPTY, ownerid);
// kal_prompt_trace(MOD_USB, "RDY R %d", ownerid);
}
#endif
if(real_count != 0)
{
remain = (BRead(rx_info) + real_count) - BLength(rx_info);
if(remain < 0)
{
/* dest, src, len */
kal_mem_cpy(buffaddr, BuffRead(rx_info), real_count);
BRead(rx_info) += real_count;
}
else
{
kal_mem_cpy(buffaddr, BuffRead(rx_info), real_count-remain);
kal_mem_cpy((kal_uint8 *)(buffaddr+real_count-remain), BStartAddr(rx_info), remain);
BRead(rx_info) = remain;
}
}
/* pop data from ring buffer to caller buffer */
/*
for (index = 0; index < real_count; index++)
{
Buf_Pop(rx_info, *(buffaddr+index));
}
*/
/* update status */
if (status != NULL)
{
*status = 0;
if (USB2UARTPort.EscFound)
{
*status |= UART_STAT_EscDet;
USB2UARTPort.EscFound = KAL_FALSE;
}
if (USB2UARTPort.breakDet)
{
*status |= UART_STAT_Break;
USB2UARTPort.breakDet = KAL_FALSE;
}
}
IRQMask(IRQ_USB_CODE);
Buf_GetRoomLeft(rx_info, RoomLeft);
#ifdef USB_20_ENABLE
/* only unmask IRQ if ring buffer room left >= MAX BULK PKT SIZE */
if((USB_Is_High_Speed() == KAL_TRUE)&&(RoomLeft >= USB_EP_BULK_MAXP_HS)
||(USB_Is_High_Speed() == KAL_FALSE)&&(RoomLeft >= USB_EP_BULK_MAXP_FS))
{
error_count = USB_Get_HW_Error_Count();
if(error_count <= 8)
{
USB_Set_UnMask_Irq(KAL_TRUE);
IRQUnmask(IRQ_USB_CODE);
}
else
{
drv_trace0(TRACE_FUNC, USBACM_FAIL_NOT_UNMASK);
// kal_prompt_trace(MOD_USB, "UNMASK USB FAIL");
}
}
#else
/* only unmask IRQ if ring buffer room left >= 64 */
if(RoomLeft >= USB_EP_BULK_MAXP)
{
error_count = USB_Get_HW_Error_Count();
if(error_count <= 8)
{
USB_Set_UnMask_Irq(KAL_TRUE);
IRQUnmask(IRQ_USB_CODE);
}
else
{
drv_trace0(TRACE_FUNC, USBACM_FAIL_NOT_UNMASK);
// kal_prompt_trace(MOD_USB, "UNMASK USB FAIL");
}
}
#endif
#ifndef __PRODUCTION_RELEASE__
if(ownerid != USB2UARTPort.ownerid)
{
EXT_ASSERT( 0, (kal_uint32) ownerid, (kal_uint32)USB2UARTPort.ownerid, 0);
}
drv_trace1(TRACE_FUNC, USBACM_GET_BYTES, real_count);
// kal_prompt_trace(MOD_USB, "Get %d", real_count);
#endif /* __PRODUCTION_RELEASE__ */
return real_count;
}
static int MountDevice(void * DriveData, int DeviceNumber, int DeviceType, DWORD Flags)
{
kal_uint8 retry = 0;
if(msdc2_handle->mIsInitialized)
return SECTOR_SIZE;
msdc2_handle->is_init_timeout = KAL_FALSE;
start:
if(!msdc2_handle->mIsPresent)
{
//dbg_print("not present \r\n");
#if defined(_NAND_FLASH_BOOTING_)
// add the following code for solving plug in or out the SD card during
// NFB loading process. The card detection interruptwill disapperared
// while interrupt controller is masked.
IRQMask(IRQ_MSDC2_CODE);
if(MSDC_Reg(MSDC_PS) & MSDC_PS_PIN0)
{
if(msdc2_handle->ins_level == MSDC_IOCTRL_PULL_UP)
msdc2_handle->mIsPresent = KAL_FALSE;
else
msdc2_handle->mIsPresent = KAL_TRUE;
}
else
{
if(msdc2_handle->ins_level == MSDC_IOCTRL_PULL_UP)
msdc2_handle->mIsPresent = KAL_TRUE;
else
msdc2_handle->mIsPresent = KAL_FALSE;
}
IRQUnmask(IRQ_MSDC2_CODE);
#endif // _NAND_FLASH_BOOTING_
if(!msdc2_handle->mIsPresent)
{
MSDC_PDNControl2(KAL_TRUE);
return FS_MSDC_MOUNT_ERROR;
}
}
MSDC_PDNControl2(KAL_FALSE);
if(SD_Initialize_2() != NO_ERROR)
{
goto err_exit;
}
//if(SD_MountDevice(DeviceType) != FS_NO_ERROR)
//return FS_MSDC_MOUNT_ERROR;
//dbg_print("Mount success! \r\n");
MSDC_PDNControl2(KAL_TRUE);
return SECTOR_SIZE;
err_exit:
if(retry++ <= SD_MAX_RETRY && msdc2_handle->is_init_timeout == KAL_FALSE)
{
//dbg_print("SD MountDevice failed! retry: %d \r\n",retry);
goto start;
}
#if defined(__MSDC_NOT_SUPPORT_HOT_PLUG__)
msdc2_handle->mIsPresent = KAL_FALSE;
#endif
MSDC_PDNControl2(KAL_TRUE);
return FS_MSDC_MOUNT_ERROR;
}
