/* Init and set seek LISR and HISR functions
* @param None.
* @return None
*/
void video_set_seek_isr(DECODE_TYPE decode_type)
{
kal_uint32 savedMask;
if((decode_type == DECODE_TYPE_MPEG4) || (decode_type == DECODE_TYPE_H263))
{
savedMask = SaveAndSetIRQMask();
#ifdef DRV_MP4_V1
IRQMask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQMask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
RestoreIRQMask(savedMask);
//savedMask = SaveAndSetIRQMask();
mpeg4_dec_init_isr_param();
g_mpeg4_dec_info_ptr->dec_state = MPEG4_DEC_STATE_SEEK;
#ifdef MP4_MOVE_LISR_TO_HISR
VISUAL_Register_HISR(VISUAL_MPEG4_SEEK_FIRST_HISR_ID, mpeg4_dec_seek_first_HISR);
#endif
VISUAL_Register_HISR(VISUAL_MP4_SEEK_HISR_ID, mpeg4_dec_seek_HISR);
#ifdef DRV_MP4_V1
IRQ_Register_LISR(IRQ_MPEG4_CODE, mpeg4_dec_seek_LISR, "MPEG4Seek");
IRQSensitivity(IRQ_MPEG4_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_MPEG4_CODE);
#else /*!DRV_MP4_V1*/
IRQ_Register_LISR(IRQ_MPEG4_DEC_CODE, mpeg4_dec_seek_LISR, "MPEG4Seek");
IRQSensitivity(IRQ_MPEG4_DEC_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_MPEG4_DEC_CODE);
#endif /*DRV_MP4_V1*/
//RestoreIRQMask(savedMask);
}
}
void idc_uart_hisr(void)
{
kal_uint16 IIR, LSR, RXTRIG;
IIR = DRV_Reg(IDC_UART_IIR);
LSR = DRV_Reg(IDC_UART_LSR);
RXTRIG = DRV_Reg(IDC_UART_RXTRIG);
if (IIR & IDC_UART_IIR_INT_INVALID)
{
IRQClearInt(MD_IRQID_IDC2ARM);
#if !defined(__UNIFIED_ISR_LEVEL__)
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return;
}
idc_hisr_time[idc_hisr_count] = DRV_Reg32(FRC_VAL_R);
idc_hisr_count++;
if (idc_hisr_count == 20)
{
idc_hisr_count = 0;
}
idc_send_rx_data_by_ilm();
if (KAL_FALSE == idc_read_RBR)
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_ERROR, 0, IDC_RX_HISR_MSG, IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
#else
kal_sprintf(idc_dbg_str, "drv_idc: HISR without Read Data, IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)\n\r",
IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
DT_IDC_PRINTF(idc_dbg_str);
#endif
ASSERT(0);
}
else if (((LSR & 0x9F) != 0x1) || (IIR != 0xc4))
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_ERROR, 0, IDC_RX_EXCEPTION_MSG, IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Exception occur, IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)\n\r",
IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
DT_IDC_PRINTF(idc_dbg_str);
#endif
}
else if (RXTRIG == 0);
idc_read_RBR = KAL_FALSE;
IRQClearInt(MD_IRQID_IDC2ARM);
#if !defined(__UNIFIED_ISR_LEVEL__)
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return;
}
/* activate USB LOGGING DSP interrput */
void USB_LOGGING_DSP_Drv_Activate_ISR(void)
{
IRQSensitivity(IRQ_IRDEBUG1_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_IRDEBUG1_CODE);
#if !defined(DRV_USB_LOGGING_V5_SINGLE_DSP)
IRQSensitivity(IRQ_IRDEBUG2_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_IRDEBUG2_CODE);
#endif
}
void hif1_lisr(void)
{
#if defined (HIF1_CHANNEL_SUPPORT)
IRQMask(IRQ_HIF_1_CODE);
#endif
//(*(volatile kal_uint32*)HIF_INTSTA_REG(1)) = 0;//hif int status,write clear
HIF_INT_CLEAR(1);
hif_internal_handle[1].DMA_BUSY = KAL_FALSE;
#ifdef MTK_SLEEP_ENABLE
L1SM_SleepEnable(hif_sleepMode_handle[1]);//lock MD sleep mode
#endif
SLA_CustomLogging("HDM",0);//set for debug
if(hif_internal_handle[1].realtime_callback == KAL_TRUE)
{
if(hif_cb[1])
{
hif_cb[1]();
}
#if defined (HIF1_CHANNEL_SUPPORT)
IRQUnmask(IRQ_HIF_1_CODE);
#endif
}
else
drv_active_hisr((kal_uint8)DRV_HIF1_HISR_ID);
}
/*************************************************************************
* FUNCTION
* EINT_TIMER_CALLBACK
*
* DESCRIPTION
* This function implements main external interrupt LISR registered in
* global ISR jump table.
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* No return
*
* GLOBALS AFFECTED
*
*************************************************************************/
void EINT_TIMER_CALLBACK(void *data)
{
EINT_SW_DEBOUNCE_STRUCT *sw_debounce = (EINT_SW_DEBOUNCE_STRUCT *)data;
IRQMask(IRQ_EIT_CODE);
if(sw_debounce->eint_sw_debounce_handle != 0x7f)
{
DclSGPT_Control(sw_debounce->eint_sw_debounce_handle,SGPT_CMD_STOP,0);
DclSGPT_Close(&(sw_debounce->eint_sw_debounce_handle));
}
//EINT_PRINT("\tEINT_TIMER_CALLBACK, sw_debounce->eint_no = %d",sw_debounce->eint_no);
sw_debounce->eint_intr_allow = (sw_debounce->eint_intr_allow == KAL_TRUE)? KAL_FALSE: KAL_TRUE;
/*
* This timer is to avoid if interrupt status is changed but
* sw_debounce->eint_intr_allow is still in KAL_TRUE state
* because of no interrupt
*/
if (sw_debounce->eint_intr_allow)
{
SGPT_CTRL_START_T start;
start.u2Tick= eint_sw_debounce_time_delay[sw_debounce->eint_no];
start.pfCallback=EINT_TIMER_CALLBACK;
start.vPara=data;
sw_debounce->eint_sw_debounce_handle=DclSGPT_Open(DCL_GPT_CB,0);
DclSGPT_Control(sw_debounce->eint_sw_debounce_handle,SGPT_CMD_START,(DCL_CTRL_DATA_T*)&start);
}
IRQUnmask(IRQ_EIT_CODE);
EINT_UnMask(sw_debounce->eint_no);
}
/*-----------------------------------------------------------------------*
*
* This function is to start gpt hardware.
*
*------------------------------------------------------------------------*/
static void GPT_Start(kal_uint8 timerNum)
{
GPT_PDN_enable();
if (timerNum == GPT1)
{
DRV_GPT_SetBits(GPT1_CTRL, GPT_CTRL_Enable);
}
else if (timerNum == GPT2)
{
DRV_GPT_SetBits(GPT2_CTRL, GPT_CTRL_Enable);
}
#if defined(DRV_GPT_GPT3)
else if (timerNum == GPT3)
{
#if !defined(GEMINI23C_EVB_BB)
GPT3_UseCount++;
#endif
DRV_GPT_SetBits(GPT3_CTRL, GPT3_ENABLE);
}
#endif
#if defined(DRV_GPT_GPT4)
else if (timerNum == GPT4)
{
DRV_GPT_SetBits(GPT4_CTRL, GPT4_ENABLE);
}
#endif
//GPT_PDN_enable();
IRQUnmask(IRQ_GPT_CODE);
}
void drv_idc_init_uart(void)
{
#if defined(MT6290)
DRV_WriteReg32(BASE_ADDR_MDINFRAMISC + 0x114, DRV_Reg32(BASE_ADDR_MDINFRAMISC + 0x114) | 0x6);
DRV_WriteReg32(BASE_ADDR_MDPERIMISC + 0x114, DRV_Reg32(BASE_ADDR_MDPERIMISC + 0x114) | 0x4);
#if __FPGA__
#else
// set GPIO as default output
DRV_WriteReg32_NPW(BASE_ADDR_TOPMISC + 0x1D4, DRV_Reg32(BASE_ADDR_TOPMISC + 0x1D4) | 0x200);
#endif
#endif
#if defined(MT6595)
// Enable GPIO 29, 30 pull-up/pull-down
DRV_WriteReg32(GPIO_base + 0x110, DRV_Reg32(GPIO_base + 0x110) | 0x6000);
// Select GPIO 29, 30 pull-up
DRV_WriteReg32(GPIO_base + 0x210, DRV_Reg32(GPIO_base + 0x210) | 0x6000);
#endif
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_INFO, 0, IDC_UART_INIT_MSG);
#else
kal_sprintf(idc_dbg_str, "drv_idc: IDC UART Init\n\r");
DT_IDC_PRINTF(idc_dbg_str);
#endif
// register isr, enable RX data receive interrupt
IRQMask(MD_IRQID_IDC2ARM);
// Initialize IDC UART FIFO threshold
drv_idc_set_fifo_trigger(1);
DRV_WriteReg32(IDC_UART_FCR, IDC_UART_FCR_RXTRIG | IDC_UART_FCR_FIFOINI);
DRV_WriteReg32(IDC_UART_IER, IDC_UART_IER_ERBFI);
IRQ_Register_LISR(MD_IRQID_IDC2ARM, idc_uart_lisr, "IDC_UART");
DRV_Register_HISR(DRV_IDC_HISR_ID, idc_uart_hisr);
IRQSensitivity(MD_IRQID_IDC2ARM, KAL_FALSE);
IRQClearInt(MD_IRQID_IDC2ARM);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_TRUE;
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_w_ptr = 3; // 2'b11
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
// Initialize baud rate
drv_idc_set_baudrate(4000000);
// initial flags/config of IDC driver
idc_port.main_state = IDC_IN_USE;
return;
}
/*
* FUNCTION
* IMGPROC_HISR_Entry
*
* DESCRIPTION
* Hisr for image processor(stands for filter mode)
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* imgproc_dcb.state
*/
void INTERN IMGPROC_HISR_Entry(void)
{
kal_uint32 reg = DRV_Reg32(IMGPROC_INTR);
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(imgproc_dcb.mask != FILTER_NONE);
ASSERT(imgproc_dcb.state == IMGPROC_BUSY);
if(reg & IMGPROC_INTR_INT)
{
if(imgproc_dcb.cb)
imgproc_dcb.cb();
else
kal_set_eg_events(IMGPROC_Events,IMGPROC_EVENT,KAL_OR);
}
else
ASSERT(0);
imgproc_dcb.state = IMGPROC_READY;
#elif (defined(DRV_IDP_6228_SERIES))
if(reg & IMGPROC_INTR_INT)
kal_set_eg_events(IMGPROC_Events,IMGPROC_EVENT,KAL_OR);
else
ASSERT(0);
#endif
IRQClearInt(IRQ_IMGPROC_CODE);
IRQUnmask(IRQ_IMGPROC_CODE);
}
/*-----------------------------------------------------------------------
* FUNCTION
* DclSGPT_Initialize
*
* DESCRIPTION
* This function is to initialize SW GPT module.
*
* PARAMETERS
* DCL_STATUS_OK
*
* RETURNS
* none
*
*------------------------------------------------------------------------*/
DCL_STATUS DclSGPT_Initialize(void)
{
kal_uint8 index;
DCL_GPT_BUS_CLOCK_ON();
/* GPT hardware reset */
drv_gpt_reset();
IRQ_Register_LISR(MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER), GPTCB_Lisr, "GPTCBMS");
IRQ_Register_LISR(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER), GPTCB_US_Lisr, "GPTCBUS");
IRQ_Register_LISR(MDGPT_INTR_ID(DRV_GPT_DEBUG_TIMER), GPT_DEBUG_Lisr, "GPTDEBUG");
#if defined (__MTK_TARGET__) && !defined(__GPTDEBUG_HISR_DISABLE__) && defined(__LTE_RAT__)
gpt_debug_hisr = kal_init_hisr(GPT_DEBUG_HISR);
#endif
/* set gpt CB timer */
drv_gpt_set_timer(DRV_GPT_CALLBACK_TIMER, DCL_GPT_CB_TICK2US, MDGPT_CTRL_MODE_REPEAT);
/* set gpt CBUS timer */
drv_gpt_set_timer(DRV_GPT_CBUS_TIMER, DCL_GPT_CBUS_TICK2US, MDGPT_CTRL_MODE_REPEAT);
/* set gpt Debug timer, tick unit = us */
drv_gpt_set_timer(DRV_GPT_DEBUG_TIMER, DCL_GPT_CBUS_TICK2US, MDGPT_CTRL_MODE_ONESHOT);
/* set OS timer */
drv_gpt_set_timer(DRV_GPT_SYSTEM_TIMER, KAL_MICROSECS_PER_TICK, MDGPT_CTRL_MODE_REPEAT);
/* gptCB variables are initialized in BSS reset procedure */
/* Register the GPT CB HISR */
DRV_Register_HISR(DRV_GPT1_HISR_ID, GPTCB_10MS_HISR);
DRV_Register_HISR(DRV_GPT2_HISR_ID, GPTCB_US_HISR);
for (index = 0; index < MAX_GPT_ITEMS; index++)
{
gptCB_items[index].gptimer_func = GPT_ERROR_CB;
gpt_DEBUG_items[index].gptimer_func = GPT_ERROR_CB;
}
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_CALLBACK_TIMER));
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_CBUS_TIMER));
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_DEBUG_TIMER));
IRQUnmask(MDGPT_INTR_ID(DRV_GPT_SYSTEM_TIMER));
DCL_GPT_BUS_CLOCK_OFF();
return STATUS_OK;
}
static void USB_LOGGING_DSP2_HISR(void)
{
if(log_dsp_hdlr[1] == NULL)
ASSERT(0);
log_dsp_hdlr[1]();
IRQClearInt(IRQ_IRDEBUG2_CODE);
IRQUnmask(IRQ_IRDEBUG2_CODE);
}
/*-----------------------------------------------------------------------*
* FUNCTION
* DclHGPT_Initialize
*
* DESCRIPTION
* This function is to initialize HW GPT module.
*
* PARAMETERS
* None
*
* RETURNS
* DCL_STATUS_OK
*
*------------------------------------------------------------------------*/
DCL_STATUS DclHGPT_Initialize(void)
{
pfHGPT1Callback = HGPT_Defaul_Callback;
pfHGPT2Callback = HGPT_Defaul_Callback;
IRQ_Register_LISR(IRQ_GPT_CODE, GPT_LISR,"GPT handler");
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
return STATUS_OK;
}
/*
* FUNCTION
* IMGPROC_Init
*
* DESCRIPTION
* Initialize the IMGPROC driver and it should be called only once.
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
kal_int32 API IMGPROC_Init(void)
{
#if (defined(DRV_IDP_6219_SERIES))
ASSERT(IMGPROC_Events == 0);
IMGPROC_Events = kal_create_event_group("IMGPROC Events");
VISUAL_Register_HISR(VISUAL_IMGPROC_HISR_ID,IMGPROC_HISR_Entry);
IRQ_Register_LISR(IRQ_IMGPROC_CODE, IMGPROC_LISR_Entry,"IMGPROC");
IRQSensitivity(IRQ_IMGPROC_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_IMGPROC_CODE);
kal_mem_set(&imgproc_dcb,0,sizeof(IMGPROC_DCB_STRUCT));
#elif (defined(DRV_IDP_6228_SERIES))
IMGPROC_Events = kal_create_event_group("IMGPROC Events");
VISUAL_Register_HISR(VISUAL_IMGPROC_HISR_ID,IMGPROC_HISR_Entry);
IRQ_Register_LISR(IRQ_IMGPROC_CODE, IMGPROC_LISR_Entry,"IMGPROC");
IRQSensitivity(IRQ_IMGPROC_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_IMGPROC_CODE);
#endif
return NO_ERROR;
}
void hif0_hisr(void)
{
if (hif_cb[0])
{
hif_cb[0]();
}
kal_set_eg_events(hif_events, 1, KAL_OR);
#if defined (HIF0_CHANNEL_SUPPORT)
IRQUnmask(IRQ_HIF_CODE);
#endif
}
void hif1_hisr(void)
{
if (hif_cb[1])
{
hif_cb[1]();
}
kal_set_eg_events(hif_events, 2, KAL_OR);
#if defined (HIF1_CHANNEL_SUPPORT)
IRQUnmask(IRQ_HIF_1_CODE);
#endif
}
/*-----------------------------------------------------------------------*
* FUNCTION
* DclHGPT_RegisterCallback
*
* DESCRIPTION
* This function is to set callback function for the HW GPT module.
*
* PARAMETERS
* handle - hanlde previous got from DclHGPT_Open().
* event - only support EVENT_HGPT_TIMEOUT event.
* callback - the callback function when HW GPT is timeout.
*
* RETURNS
* STATUS_OK - successfully register the callback function.
* STATUS_INVALID_DCL_HANDLE - It's a invalid handle.
* STATUS_NOT_OPENED - The module has not been opened.
* STATUS_INVALID_EVENT - The event parameter is invalid.
*
*------------------------------------------------------------------------*/
DCL_STATUS DclHGPT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback)
{
DCL_DEV eDev;
if (!DCL_HGPT_IS_HANDLE_MAGIC(handle))
{
ASSERT(0);
return STATUS_INVALID_DCL_HANDLE;
}
if (!(event & EVENT_HGPT_TIMEOUT))
{
return STATUS_INVALID_EVENT;
}
eDev = DCL_HGPT_GET_DEV(handle);
switch(eDev)
{
case GPT1:
if (KAL_FALSE == fgGPT1Open)
{
return STATUS_NOT_OPENED;
}
pfHGPT1Callback = callback;
eHGPT1Event = event;
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
return STATUS_OK;
case GPT2:
if (KAL_FALSE == fgGPT2Open)
{
return STATUS_NOT_OPENED;
}
pfHGPT2Callback = callback;
eHGPT2Event = event;
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
return STATUS_OK;
default:
ASSERT(0);
return STATUS_INVALID_DCL_HANDLE;
}
}
/*
* FUNCTION
* GPT_init
*
* DESCRIPTION
* GPT initial function
*
* CALLS
* Initialize the GPT module
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
* GPT_Callback = callback function, called when GPT intr. is coming
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_init(kal_uint8 timerNum, void (*GPT_Callback)(void))
{
IRQ_Register_LISR(IRQ_GPT_CODE, GPT_LISR,"GPT handler");
if (timerNum == 1)
{
GPTTimer.GPT_FUNC.gpt1_func = GPT_Callback;
GPT_clock(1,clk_1k);
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
}
if (timerNum == 2)
{
GPTTimer.GPT_FUNC.gpt2_func = GPT_Callback;
GPT_clock(2,clk_16k);
IRQSensitivity(IRQ_GPT_CODE,LEVEL_SENSITIVE);
IRQUnmask(IRQ_GPT_CODE);
}
}
/*************************************************************************
* FUNCTION
* EINT_UnMask
*
* DESCRIPTION
* This function implements Unmask of dedicated external interrupt source
*
* CALLS
*
* PARAMETERS
* eintno - external interrupt vector number
*
* RETURNS
* No return
*
* GLOBALS AFFECTED
*
*************************************************************************/
void EINT_UnMask(kal_uint8 eintno)
{
if (eint_is_dedicated & (1 << eintno))
{
switch(eint_is_dedicated_map[eintno])
{
case DEDICATED_EINT0:
{
eint_set_l1_eint_enable(DEDICATED_EINT0, EINT_ENABLE);
IRQUnmask(DEDICATED_EINT_IRQ0);
break;
}
case DEDICATED_EINT1:
{
eint_set_l1_eint_enable(DEDICATED_EINT1, EINT_ENABLE);
IRQUnmask(DEDICATED_EINT_IRQ1);
break;
}
case DEDICATED_EINT2:
{
eint_set_l1_eint_enable(DEDICATED_EINT2, EINT_ENABLE);
IRQUnmask(DEDICATED_EINT_IRQ2);
break;
}
case DEDICATED_EINT3:
{
eint_set_l1_eint_enable(DEDICATED_EINT3, EINT_ENABLE);
IRQUnmask(DEDICATED_EINT_IRQ3);
break;
}
default:
return;
}
}
else
{
eint_set_irqen(eintno,EINT_ENABLE);
}
}
kal_int32 cc_irq_unmask(kal_uint32 index)
{
/* it is assumed that IRQ ID aligns index of CC IRQ!! */
/* Please check this during pre-sillicon. */
if (!CC_IRQ_RX_INDEX_IS_IN_RANGE(index))
{
return CC_IRQ_ERR_PARAM;
}
index = CC_IRQ_RX_INDEX_OFFSET(index);
IRQUnmask(CC_IRQ_INTR_ID_START + index);
return CC_IRQ_SUCCESS;
}
/*************************************************************************
* FUNCTION
* mdci_init
*
* DESCRIPTION
* This function initialized MDIF.
*
* PARAMETERS
* arb - arbitration mode flag
* md_offset - modem side master offset address(in bytes).
*
* RETURNS
* none
*
*************************************************************************/
void mdci_hw_init(kal_uint32 arb, kal_uint32 md_offset)
{
/* set arbitration mode */
if (arb == 1) {
*MDIF_CON |= MDIF_CON_ARB;
}
/* initialize the MD side address offset */
mdci_md_offset = md_offset;
/* register LISR */
#if defined(MDIF_FOR_AP_SIDE)
IRQ_Register_LISR(IRQ_APMDIF_CODE, mdci_lisr, "MDIF LISR");
#else
IRQ_Register_LISR(IRQ_MDIF_CODE, mdci_lisr, "MDIF LISR");
#endif
#ifndef __IVP__
/* register HISR */
DRV_Register_HISR(DRV_MDIF_HISR_ID, mdci_hisr);
#endif /* __IVP__ */
/* set IRQ sensitivity */
#if defined(MDIF_FOR_AP_SIDE)
IRQSensitivity(IRQ_APMDIF_CODE, LEVEL_SENSITIVE);
#else
IRQSensitivity(IRQ_MDIF_CODE, LEVEL_SENSITIVE);
#endif
/* unmask MDIF */
#if defined(MDIF_FOR_AP_SIDE)
IRQUnmask(IRQ_APMDIF_CODE);
#else
IRQUnmask(IRQ_MDIF_CODE);
#endif
}
/*************************************************************************
* FUNCTION
* ccif_init
*
* DESCRIPTION
* This function initialized EMIMPU.
*
* PARAMETERS
* none
*
* RETURNS
* none
*
*************************************************************************/
void emimpu_init(kal_uint32 arb, kal_uint32 md_offset)
{
/* register LISR */
IRQ_Register_LISR(IRQ_EMI_CODE, emimpu_lisr, "EMIMPU LISR");
/* register HISR */
/* set IRQ sensitivity */
IRQSensitivity(IRQ_EMI_CODE, LEVEL_SENSITIVE);
/* unmask EMIMPU */
IRQUnmask(IRQ_EMI_CODE);
}
void
idp_imgdma_init(void)
{
#ifndef MDP_C_MODEL
#if defined(IDP_FULL_ISR_SUPPORT)
IRQ_Register_LISR(IRQ_ROT_DMA_CODE, idp_imgdma_LISR, "IMGDMA");
#endif
IRQSensitivity(IRQ_ROT_DMA_CODE, LEVEL_SENSITIVE);
IRQUnmask(IRQ_ROT_DMA_CODE);
#endif // #ifndef MDP_C_MODEL
// Initial the owner structure.
idp_imgdma_rotdma0_init();
}
/*-----------------------------------------------------------------------*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*------------------------------------------------------------------------*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_GPT_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
HGPT1_Callback();
}
if (GPT_Status & GPT_STS_2)
{
HGPT2_Callback();
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
/*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
GPTTimer.GPT_FUNC.gpt1_func();
}
if (GPT_Status & GPT_STS_2)
{
GPTTimer.GPT_FUNC.gpt2_func();
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
void drv_idc_close()
{
// stop all events before closing IDC
DRV_WriteReg32(IDC_BSI_SCH_STOP_3100, 0xFFFFFFFF);
DRV_WriteReg32(IDC_BSI_SCH_STOP_6332, 0xFFFFFFFF & ~0xFC000000);
// disable interrupt
IRQMask(MD_IRQID_IDC2ARM);
DRV_WriteReg8(IDC_UART_IER, IDC_UART_IER_ALLOFF);
IRQUnmask(MD_IRQID_IDC2ARM);
idc_port.intr_en = KAL_FALSE;
idc_port.rx_buf = 0;
// clear start/finish priority register
// clear start/finish priority bit enable register
// clear start/finish pattern register
// clear start/finish pattern bit enable register
DRV_WriteReg32(IDC_UART_START_PRI, 0);
DRV_WriteReg32(IDC_UART_START_PRI_BITEN, 0);
DRV_WriteReg32(IDC_UART_START_PAT, 0);
DRV_WriteReg32(IDC_UART_START_PAT_BITEN, 0);
DRV_WriteReg32(IDC_UART_FINISH_PRI, 0);
DRV_WriteReg32(IDC_UART_FINISH_PRI_BITEN, 0);
DRV_WriteReg32(IDC_UART_FINISH_PAT, 0);
DRV_WriteReg32(IDC_UART_FINISH_PAT_BITEN, 0);
idc_port.schedule_state[0] = IDC_PLAN;
idc_port.schedule_state[1] = IDC_PLAN;
idc_port.event_cnt[0] = 0;
idc_port.event_cnt[1] = 0;
idc_port.sram_usage_bit_map[0] = 0;
idc_port.sram_usage_bit_map[1] = 0;
idc_port.rx_buf = 0;
idc_port.owner_id = 0;
idc_port.main_state = IDC_CLOSED;
return;
}
/*-----------------------------------------------------------------------*
* FUNCTION
* GPT_LISR
*
* DESCRIPTION
* GPT interrupt handler
*
* CALLS
* It is called when GPT interrupt is coming
*
* PARAMETERS
* None
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*------------------------------------------------------------------------*/
extern void GPT_MS_Time_Out_Handler(kal_uint16 *ms_handle_sta); /*defined in dcl_gpt.c*/
extern kal_uint16 gpt_ms_lisr_handle_status; /*defined in dcl_gpt.c*/
void GPT_LISR(void)
{
kal_uint16 GPT_Status;
IRQMask(IRQ_GPT_CODE);
GPT_Status = DRV_GPT_Reg(GPT_STS);
if (GPT_Status & GPT_STS_1)
{
HGPT1_Callback();
}
if (GPT_Status & GPT_STS_2)
{
/*--------*/
//add for 1ms GPT run in LISR context
GPT_MS_Time_Out_Handler(&gpt_ms_lisr_handle_status);
HGPT2_Callback(); /* always active hisr ,here may be some optimize */
}
IRQClearInt(IRQ_GPT_CODE);
IRQUnmask(IRQ_GPT_CODE);
}
void USB_LOGGING_3G_HISR(void)
{
kal_uint32 buf_index;
kal_uint8 total_full_index = 0;
for(buf_index = USBACM_LOGGING_DSP_SOURCE_NUM; buf_index < USBACM_LOGGING_TOTAL_SOURCE_NUM; buf_index++)
{
total_full_index |= USB_LOGGING_Get_3G_Status((buf_index-USBACM_LOGGING_DSP_SOURCE_NUM));
}
if(total_full_index != 0)
{
if(log_3g_hdlr == NULL)
ASSERT(0);
log_3g_hdlr();
}
IRQClearInt(IRQ_LOG3G_CODE);
IRQUnmask(IRQ_LOG3G_CODE);
}
void
idp_imgdma_rotdma0_LISR(void)
{
#if defined(__MTK_TARGET__) || defined(MDP_C_MODEL)
kal_uint32 reg;
#if !defined(MDP_C_MODEL)
IRQMask(IRQ_ROT_DMA_CODE);
#endif
reg = REG_IMGDMA_ROT_DMA_IRQ_FLAG & 0x00FF;
if (reg & IMGDMA_ROTDMA_IRQ_FLAG_0_BIT)
{
if (idp_imgdma_rotdma0_fend_intr_cb != NULL)
{
idp_imgdma_rotdma0_fend_intr_cb(idp_imgdma_rotdma0_fend_intr_cb_param);
}
}
#if defined(NO_SHRINK_ROTDMA_CODE)
if (reg & IMGDMA_ROTDMA_IRQ_FLAG_2_BIT)
{
if (idp_imgdma_rotdma0_q_empty_intr_cb != NULL)
{
idp_imgdma_rotdma0_q_empty_intr_cb(idp_imgdma_rotdma0_q_empty_intr_cb_param);
}
}
#endif
REG_IMGDMA_ROT_DMA_IRQ_FLAG_CLR = reg; //write clear
#if !defined(MDP_C_MODEL)
IRQUnmask(IRQ_ROT_DMA_CODE);
#endif
#endif // #if defined(__MTK_TARGET__) || defined(MDP_C_MODEL)
}
void i2c_init(void)
{
//kal_uint32 savedMask;
i2c_status.state=SCCB_READY_STATE;
//savedMask = SaveAndSetIRQMask();
/* Switch GPIO to HW Mode */
//GPIO_ModeSetup(SCCB_SERIAL_CLK_PIN,SCCB_GPIO_SCL_MODE);
//GPIO_ModeSetup(SCCB_SERIAL_DATA_PIN,SCCB_GPIO_SDA_MODE);
//RestoreIRQMask(savedMask);
IRQ_Register_LISR(IRQ_I2C_CODE, i2c_lisr,"I2C ISR");
IRQUnmask(IRQ_I2C_CODE);
ENABLE_I2C_ACK_ERR_DET; //Always enable ack error detection
ENABLE_I2C_NAKERR_DET; //Always enable nack error detection
#if (defined(SCCB_DMA_ENABLED))
i2c_status.is_DMA_enabled=KAL_FALSE;
#endif
}
/*
* FUNCTION
* GPT_Start
*
* DESCRIPTION
* Start GPT timer
*
* CALLS
* It is called to start GPT timer
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_Start(kal_uint8 timerNum)
{
if (timerNum == 1)
{
DRV_Reg(GPT1_CTRL) |= GPT_CTRL_Enable;
}
if (timerNum == 2)
{
DRV_Reg(GPT2_CTRL) |= GPT_CTRL_Enable;
}
#if defined(DRV_GPT_GPT3)
if (timerNum == 3)
{
DRV_Reg(GPT3_CTRL) |= GPT3_ENABLE;
}
#endif
#ifdef GPT_DRVPDN_FAST
DRVPDN_DISABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Disable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
IRQUnmask(IRQ_GPT_CODE);
}
/* get bytes from rx buffer, parameter status shows escape and break status
return value is the actually get bytes */
static kal_uint16 USB2UART_GetBytes(UART_PORT port, kal_uint8 *buffaddr, kal_uint16 length,
kal_uint8 *status, module_type ownerid)
{
kal_uint16 real_count;
// kal_uint16 index;
kal_uint16 RoomLeft;
kal_uint32 savedMask;
kal_uint32 error_count;
kal_int32 remain;
BUFFER_INFO *rx_info = &(USB2UARTPort.Rx_Buffer);
if(ownerid != USB2UARTPort.ownerid)
{
#ifdef __PRODUCTION_RELEASE__
return 0;
#else /* __PRODUCTION_RELEASE__ */
EXT_ASSERT( 0, (kal_uint32) ownerid, USB2UARTPort.ownerid, 0);
#endif
}
/* return directly if not match condition */
if ( (gUsbDevice.device_type != USB_CDC_ACM) ||
(USB2UARTPort.initialized == KAL_FALSE) || (gUsbDevice.nDevState!=DEVSTATE_CONFIG))
return 0;
/* determine real data count */
/* Note that the area to determine send_Rxilm must also contain in critical section.
Otherwise if USB HISR activated before send_Rxilm setting as true,
this message will be lost */
savedMask = SaveAndSetIRQMask();
Buf_GetBytesAvail(rx_info, real_count);
if(real_count >= length)
{
real_count = length;
}
else
{
g_UsbACM.send_Rxilm = KAL_TRUE; /*After this time get byte, buffer will be empty */
}
RestoreIRQMask(savedMask);
#ifndef __PRODUCTION_RELEASE__
if(g_UsbACM.send_Rxilm == KAL_TRUE)
{
drv_trace1(TRACE_FUNC, USBACM_GET_BYTES_BUF_EMPTY, ownerid);
// kal_prompt_trace(MOD_USB, "RDY R %d", ownerid);
}
#endif
if(real_count != 0)
{
remain = (BRead(rx_info) + real_count) - BLength(rx_info);
if(remain < 0)
{
/* dest, src, len */
kal_mem_cpy(buffaddr, BuffRead(rx_info), real_count);
BRead(rx_info) += real_count;
}
else
{
kal_mem_cpy(buffaddr, BuffRead(rx_info), real_count-remain);
kal_mem_cpy((kal_uint8 *)(buffaddr+real_count-remain), BStartAddr(rx_info), remain);
BRead(rx_info) = remain;
}
}
/* pop data from ring buffer to caller buffer */
/*
for (index = 0; index < real_count; index++)
{
Buf_Pop(rx_info, *(buffaddr+index));
}
*/
/* update status */
if (status != NULL)
{
*status = 0;
if (USB2UARTPort.EscFound)
{
*status |= UART_STAT_EscDet;
USB2UARTPort.EscFound = KAL_FALSE;
}
if (USB2UARTPort.breakDet)
{
*status |= UART_STAT_Break;
USB2UARTPort.breakDet = KAL_FALSE;
}
}
IRQMask(IRQ_USB_CODE);
Buf_GetRoomLeft(rx_info, RoomLeft);
#ifdef USB_20_ENABLE
/* only unmask IRQ if ring buffer room left >= MAX BULK PKT SIZE */
if((USB_Is_High_Speed() == KAL_TRUE)&&(RoomLeft >= USB_EP_BULK_MAXP_HS)
||(USB_Is_High_Speed() == KAL_FALSE)&&(RoomLeft >= USB_EP_BULK_MAXP_FS))
{
error_count = USB_Get_HW_Error_Count();
if(error_count <= 8)
{
USB_Set_UnMask_Irq(KAL_TRUE);
IRQUnmask(IRQ_USB_CODE);
}
else
{
drv_trace0(TRACE_FUNC, USBACM_FAIL_NOT_UNMASK);
// kal_prompt_trace(MOD_USB, "UNMASK USB FAIL");
}
}
#else
/* only unmask IRQ if ring buffer room left >= 64 */
if(RoomLeft >= USB_EP_BULK_MAXP)
{
error_count = USB_Get_HW_Error_Count();
if(error_count <= 8)
{
USB_Set_UnMask_Irq(KAL_TRUE);
IRQUnmask(IRQ_USB_CODE);
}
else
{
drv_trace0(TRACE_FUNC, USBACM_FAIL_NOT_UNMASK);
// kal_prompt_trace(MOD_USB, "UNMASK USB FAIL");
}
}
#endif
#ifndef __PRODUCTION_RELEASE__
if(ownerid != USB2UARTPort.ownerid)
{
EXT_ASSERT( 0, (kal_uint32) ownerid, (kal_uint32)USB2UARTPort.ownerid, 0);
}
drv_trace1(TRACE_FUNC, USBACM_GET_BYTES, real_count);
// kal_prompt_trace(MOD_USB, "Get %d", real_count);
#endif /* __PRODUCTION_RELEASE__ */
return real_count;
}
