void timer_hw_init(void) { cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Reset Timer overflow flag */ REG_TIFR3 |= BV(TOV3); /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) TCCR3A |= BV(WGM31); TCCR3A &= ~BV(WGM30); TCCR3B |= BV(WGM32) | BV(CS30); TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) TCCR3A |= BV(WGM30); TCCR3A &= ~BV(WGM31); TCCR3B |= BV(WGM32) | BV(CS30); TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); #else #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS #endif /* initialization of Timer/Counter */ TCNT3 = 0x00; /* Enable timer interrupt: Timer/Counter3 Overflow */ REG_TIMSK3 |= BV(TOIE3); IRQ_RESTORE(flags); }
void kbd_addHandler(struct KbdHandler *handler) { KbdHandler *node; List *list; cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Choose between raw and coocked handlers list */ list = (handler->flags & KHF_RAWKEYS) ? &kbd_rawHandlers : &kbd_handlers; /* * Search for the first node whose priority * is lower than the timer we want to add. */ FOREACH_NODE(node,list) if (node->pri < handler->pri) break; /* Enqueue handler in the handlers chain */ INSERT_BEFORE(&handler->link, &node->link); IRQ_RESTORE(flags); }
void timer_hw_init(void) { cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Reset Timer flags */ REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2); /* Setup Timer/Counter interrupt */ REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to REG_TCCR2B = 0; // ensure correct initialization. REG_TCCR2A = BV(WGM21); #if TIMER_PRESCALER == 64 REG_TCCR2B |= TIMER2_PRESCALER_64; #else #error Unsupported value of TIMER_PRESCALER #endif /* Clear on Compare match & prescaler = 64, internal sys clock. When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */ TCNT2 = 0x00; /* initialization of Timer/Counter */ REG_OCR2A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */ /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ REG_TIMSK2 &= ~BV(TOIE2); REG_TIMSK2 |= BV(BIT_OCIE2A); IRQ_RESTORE(flags); }
void timer_hw_init(void) { cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Reset Timer overflow flag */ REG_TIFR1 |= BV(TOV1); /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) TCCR1A |= BV(WGM11); TCCR1A &= ~BV(WGM10); TCCR1B |= BV(WGM12) | BV(CS10); TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) TCCR1A |= BV(WGM10); TCCR1A &= ~BV(WGM11); TCCR1B |= BV(WGM12) | BV(CS10); TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); #else #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS #endif TCNT1 = 0x00; /* initialization of Timer/Counter */ /* Enable timer interrupt: Timer/Counter1 Overflow */ REG_TIMSK1 |= BV(TOIE1); IRQ_RESTORE(flags); }
void timer_hw_init(void) { cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Reset Timer flags */ REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0); /* Setup Timer/Counter interrupt */ REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to REG_TCCR0B = 0; REG_TCCR0A = BV(WGM01); /* Clear on Compare match */ #if TIMER_PRESCALER == 64 REG_TCCR0B |= TIMER0_PRESCALER_64; #else #error Unsupported value of TIMER_PRESCALER #endif TCNT0 = 0x00; /* Initialization of Timer/Counter */ REG_OCR0A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */ /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ REG_TIMSK0 &= ~BV(TOIE0); REG_TIMSK0 |= BV(BIT_OCIE0A); IRQ_RESTORE(flags); }
/** * Timer couter setup. * * This function apply to select timer couter all needed settings. * Every settings are stored in stepper_timers[]. */ void stepper_tc_setup(int index, stepper_isr_t callback, struct Stepper *motor) { ASSERT(index < CONFIG_TC_STEPPER_MAX_NUM); motor->timer = &stepper_timers[index]; //Disable PIO controller and enable TIO function TIO_PIO_PDR = BV(motor->timer->tio_pin); TIO_PIO_ABSR = BV(motor->timer->tio_pin); /* * Sets timer counter in waveform mode. * We set as default: * - Waveform mode 00 (see datasheet for more detail.) * - Master clock prescaler to STEPPER_MCK_PRESCALER * - Set none external event * - Clear pin output on comp_reg * - None effect on reg C compare */ *motor->timer->chl_mode_reg = BV(TC_WAVE); *motor->timer->chl_mode_reg |= motor->timer->ext_event_set; *motor->timer->chl_mode_reg &= ~TC_WAVSEL_MASK; *motor->timer->chl_mode_reg |= TC_WAVSEL_UP; *motor->timer->chl_mode_reg |= STEPPER_MCK_PRESCALER; *motor->timer->chl_mode_reg |= motor->timer->comp_effect_clear; *motor->timer->chl_mode_reg &= ~motor->timer->comp_effect_c_mask; //Reset comp_reg and C compare register *motor->timer->comp_reg = 0; *motor->timer->comp_c_reg = 0; //Register interrupt vector cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* * Warning: To guarantee a correct management of interrupt event, we must * trig the interrupt on level sensitive. This becouse, we have only a common * line for interrupt request, and if we have at the same time two interrupt * request could be that the is service normaly but the second will never * been detected and interrupt will stay active but never serviced. */ AIC_SVR(motor->timer->timer_id) = motor->timer->isr; AIC_SMR(motor->timer->timer_id) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE; AIC_IECR = BV(motor->timer->timer_id); // Disable interrupt on select timer counter stepper_tc_irq_disable(motor->timer); IRQ_RESTORE(flags); //Register callback motor->timer->callback = callback; motor->timer->motor = motor; }
/** * Send write command. * * After WR command cpu write bufferd page into flash memory. * */ INLINE void flash_sendWRcmd(uint32_t page) { cpu_flags_t flags; LOG_INFO("Writing page %ld...\n", page); IRQ_SAVE_DISABLE(flags); write_page(page); IRQ_RESTORE(flags); LOG_INFO("Done\n"); }
/** * Check if any of the signals in \a sigs has occurred and clear them. * * \return the signals that have occurred. */ sigmask_t sig_check(sigmask_t sigs) { sigmask_t result; cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); result = current_process->sig_recv & sigs; current_process->sig_recv &= ~sigs; IRQ_RESTORE(flags); return result; }
static void spi_starttx(struct SerialHardware *_hw) { struct AvrSerial *hw = (struct AvrSerial *)_hw; cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Send data only if the SPI is not already transmitting */ if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo)) { hw->sending = true; SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo); } IRQ_RESTORE(flags); }
INLINE void __sig_signal(Process *proc, sigmask_t sigs, bool wakeup) { cpu_flags_t flags; IRQ_SAVE_DISABLE(flags); /* Set the signals */ proc->sig_recv |= sigs; /* Check if process needs to be awoken */ if (proc->sig_recv & proc->sig_wait) { ASSERT(proc != current_process); proc->sig_wait = 0; if (wakeup) proc_wakeup(proc); else SCHED_ENQUEUE_HEAD(proc); } IRQ_RESTORE(flags); }
/** * Sleep until any of the signals in \a sigs or \a timeout ticks elapse. * If the timeout elapse a SIG_TIMEOUT is added to the received signal(s). * \return the signal(s) that have awoken the process. * \note Caller must check return value to check which signal awoke the process. */ sigmask_t sig_waitTimeout(sigmask_t sigs, ticks_t timeout) { Timer t; sigmask_t res; cpu_flags_t flags; ASSERT(!sig_check(SIG_TIMEOUT)); ASSERT(!(sigs & SIG_TIMEOUT)); /* IRQ are needed to run timer */ ASSERT(IRQ_ENABLED()); timer_set_event_signal(&t, proc_current(), SIG_TIMEOUT); timer_setDelay(&t, timeout); timer_add(&t); res = sig_wait(SIG_TIMEOUT | sigs); IRQ_SAVE_DISABLE(flags); /* Remove timer if sigs occur before timer signal */ if (!(res & SIG_TIMEOUT) && !sig_check(SIG_TIMEOUT)) timer_abort(&t); IRQ_RESTORE(flags); return res; }
int eth_init() { cpu_flags_t flags; emac_reset(); emac_start(); event_initGeneric(&recv_wait); event_initGeneric(&send_wait); // Register interrupt vector IRQ_SAVE_DISABLE(flags); /* Disable all emac interrupts */ EMAC_IDR = 0xFFFFFFFF; #if CPU_ARM_AT91 // TODO: define sysirq_set... /* Set the vector. */ AIC_SVR(EMAC_ID) = emac_irqHandler; /* Initialize to edge triggered with defined priority. */ AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; /* Clear pending interrupt */ AIC_ICCR = BV(EMAC_ID); /* Enable the system IRQ */ AIC_IECR = BV(EMAC_ID); #else sysirq_setHandler(INT_EMAC, emac_irqHandler); #endif /* Enable interrupts */ EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS; IRQ_RESTORE(flags); return 0; }
void timer_hw_init(void) { sysirq_init(); cpu_flags_t flags; MOD_CHECK(sysirq); IRQ_SAVE_DISABLE(flags); PIT_MR = TIMER_HW_CNT; /* Register system interrupt handler. */ sysirq_setHandler(SYSIRQ_PIT, timer_handler); /* Enable interval timer and interval timer interrupts */ PIT_MR |= BV(PITEN); sysirq_setEnable(SYSIRQ_PIT, true); /* Reset counters, this is needed to start timer and interrupt flags */ uint32_t dummy = PIVR; (void) dummy; IRQ_RESTORE(flags); }
static size_t lpc2_flash_writeDirect(struct KBlock *blk, block_idx_t idx, const void *_buf, size_t offset, size_t size) { ASSERT(offset == 0); ASSERT(FLASH_PAGE_SIZE_BYTES == size); Flash *fls = FLASH_CAST(blk); if (!(fls->blk.priv.flags & KB_WRITE_ONCE)) ASSERT(sector_size(idx) <= FLASH_PAGE_SIZE_BYTES); const uint8_t *buf = (const uint8_t *)_buf; cpu_flags_t flags; //Compute page address of current page. uint32_t addr = idx * blk->blk_size; uint32_t sector = addr_to_sector(addr); // Compute the first page index in the sector to manage the status int idx_sector = sector_addr(sector) / blk->blk_size; LOG_INFO("Writing page[%ld]sector[%ld]idx[%d]\n", idx, sector, idx_sector); IRQ_SAVE_DISABLE(flags); IapCmd cmd; IapRes res; cmd.cmd = PREPARE_SECTOR_FOR_WRITE; cmd.param[0] = cmd.param[1] = sector; iap(&cmd, &res); if (res.status != CMD_SUCCESS) goto flash_error; if ((fls->blk.priv.flags & KB_WRITE_ONCE) && bitarray_isRangeFull(&lpc2_bitx, idx_sector, erase_group[sector])) { kputs("blocchi pieni\n"); ASSERT(0); goto flash_error; } bool erase = false; if ((fls->blk.priv.flags & KB_WRITE_ONCE) && bitarray_isRangeEmpty(&lpc2_bitx, idx_sector, erase_group[sector])) erase = true; if (!(fls->blk.priv.flags & KB_WRITE_ONCE)) erase = true; if (erase) { cmd.cmd = ERASE_SECTOR; cmd.param[0] = cmd.param[1] = sector; cmd.param[2] = CPU_FREQ / 1000; iap(&cmd, &res); if (res.status != CMD_SUCCESS) goto flash_error; } LOG_INFO("Writing page [%ld], addr [%ld] in sector[%ld]\n", idx, addr, sector); cmd.cmd = PREPARE_SECTOR_FOR_WRITE; cmd.param[0] = cmd.param[1] = sector; iap(&cmd, &res); if (res.status != CMD_SUCCESS) goto flash_error; if (fls->blk.priv.flags & KB_WRITE_ONCE) { if (bitarray_test(&lpc2_bitx, idx)) { ASSERT(0); goto flash_error; } else bitarray_set(&lpc2_bitx, idx); } cmd.cmd = COPY_RAM_TO_FLASH; cmd.param[0] = addr; cmd.param[1] = (uint32_t)buf; cmd.param[2] = FLASH_PAGE_SIZE_BYTES; cmd.param[3] = CPU_FREQ / 1000; iap(&cmd, &res); if (res.status != CMD_SUCCESS) goto flash_error; IRQ_RESTORE(flags); LOG_INFO("Done\n"); return blk->blk_size; flash_error: LOG_ERR("%ld\n", res.status); fls->hw->status |= FLASH_WR_ERR; return 0; }