static void msm_ispif_intf_cmd(struct ispif_device *ispif, uint32_t cmd_bits,
struct msm_ispif_param_data *params)
{
uint8_t vc;
int i, k;
enum msm_ispif_intftype intf_type;
enum msm_ispif_cid cid;
enum msm_ispif_vfe_intf vfe_intf;
BUG_ON(!ispif);
BUG_ON(!params);
for (i = 0; i < params->num; i++) {
vfe_intf = params->entries[i].vfe_intf;
if (!msm_ispif_is_intf_valid(ispif->csid_version, vfe_intf)) {
pr_err("%s: invalid interface type\n", __func__);
return;
}
if (params->entries[i].num_cids > MAX_CID_CH) {
pr_err("%s: out of range of cid_num %d\n",
__func__, params->entries[i].num_cids);
return;
}
}
for (i = 0; i < params->num; i++) {
intf_type = params->entries[i].intftype;
vfe_intf = params->entries[i].vfe_intf;
for (k = 0; k < params->entries[i].num_cids; k++) {
cid = params->entries[i].cids[k];
vc = cid / 4;
if (intf_type == RDI2) {
/* zero out two bits */
ispif->applied_intf_cmd[vfe_intf].intf_cmd1 &=
~(0x3 << (vc * 2 + 8));
/* set cmd bits */
ispif->applied_intf_cmd[vfe_intf].intf_cmd1 |=
(cmd_bits << (vc * 2 + 8));
} else {
/* zero 2 bits */
ispif->applied_intf_cmd[vfe_intf].intf_cmd &=
~(0x3 << (vc * 2 + intf_type * 8));
/* set cmd bits */
ispif->applied_intf_cmd[vfe_intf].intf_cmd |=
(cmd_bits << (vc * 2 + intf_type * 8));
}
}
/* cmd for PIX0, PIX1, RDI0, RDI1 */
if (ispif->applied_intf_cmd[vfe_intf].intf_cmd != 0xFFFFFFFF)
msm_camera_io_w_mb(
ispif->applied_intf_cmd[vfe_intf].intf_cmd,
ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe_intf));
/* cmd for RDI2 */
if (ispif->applied_intf_cmd[vfe_intf].intf_cmd1 != 0xFFFFFFFF)
msm_camera_io_w_mb(
ispif->applied_intf_cmd[vfe_intf].intf_cmd1,
ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe_intf));
}
}
static int msm_ispif_reset(struct ispif_device *ispif)
{
int rc = 0;
int i;
BUG_ON(!ispif);
memset(ispif->sof_count, 0, sizeof(ispif->sof_count));
frame_event_manager_reset(&ispif->fem);
for (i = 0; i < ispif->vfe_info.num_vfe; i++) {
msm_camera_io_w(1 << PIX0_LINE_BUF_EN_BIT,
ispif->base + ISPIF_VFE_m_CTRL_0(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(i));
msm_camera_io_w(0xFFFFFFFF, ispif->base +
ISPIF_VFE_m_IRQ_CLEAR_0(i));
msm_camera_io_w(0xFFFFFFFF, ispif->base +
ISPIF_VFE_m_IRQ_CLEAR_1(i));
msm_camera_io_w(0xFFFFFFFF, ispif->base +
ISPIF_VFE_m_IRQ_CLEAR_2(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_INPUT_SEL(i));
msm_camera_io_w(ISPIF_STOP_INTF_IMMEDIATELY,
ispif->base + ISPIF_VFE_m_INTF_CMD_0(i));
msm_camera_io_w(ISPIF_STOP_INTF_IMMEDIATELY,
ispif->base + ISPIF_VFE_m_INTF_CMD_1(i));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 0));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 1));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 0));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 1));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 2));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CROP(i, 0));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CROP(i, 1));
}
msm_camera_io_w_mb(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
return rc;
}
static int msm_ispif_reset(struct ispif_device *ispif)
{
int rc = 0;
int i;
//
memset(ispif->sof_count, 0, sizeof(ispif->sof_count));
for (i = 0; i < ispif->vfe_info.num_vfe; i++) {
msm_camera_io_w(1 << PIX0_LINE_BUF_EN_BIT,
ispif->base + ISPIF_VFE_m_CTRL_0(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(i));
msm_camera_io_w(0xFFFFFFFF, ispif->base +
ISPIF_VFE_m_IRQ_CLEAR_0(i));
msm_camera_io_w(0xFFFFFFFF, ispif->base +
ISPIF_VFE_m_IRQ_CLEAR_1(i));
msm_camera_io_w(0xFFFFFFFF, ispif->base +
ISPIF_VFE_m_IRQ_CLEAR_2(i));
msm_camera_io_w(0, ispif->base + ISPIF_VFE_m_INPUT_SEL(i));
msm_camera_io_w(ISPIF_STOP_INTF_IMMEDIATELY,
ispif->base + ISPIF_VFE_m_INTF_CMD_0(i));
msm_camera_io_w(ISPIF_STOP_INTF_IMMEDIATELY,
ispif->base + ISPIF_VFE_m_INTF_CMD_1(i));
pr_debug("%s: base %x", __func__, (unsigned int)ispif->base);
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 0));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 1));
/* */
#if 0
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_RDI_INTF_n_CID_MASK(i, 0));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_RDI_INTF_n_CID_MASK(i, 1));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CID_MASK(i, 2));
#else
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_RDI_INTF_n_CID_MASK(i, 0));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_RDI_INTF_n_CID_MASK(i, 1));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_RDI_INTF_n_CID_MASK(i, 2));
#endif
/* */
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CROP(i, 0));
msm_camera_io_w(0, ispif->base +
ISPIF_VFE_m_PIX_INTF_n_CROP(i, 1));
}
msm_camera_io_w_mb(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
return rc;
}
static int msm_ispif_reset_hw(struct ispif_device *ispif, int release)
{
int rc = 0, i;
long timeout = 0;
struct clk *reset_clk1[ARRAY_SIZE(ispif_8626_reset_clk_info)];
ispif->clk_idx = 0;
rc = msm_ispif_get_clk_info(ispif, ispif->pdev,
ispif_ahb_clk_info, ispif_clk_info);
if (rc < 0) {
pr_err("%s: msm_isp_get_clk_info() failed", __func__);
return -EFAULT;
}
/* Turn ON regulators before enabling the clocks*/
rc = msm_ispif_set_regulator(ispif, 1);
if (rc < 0) {
pr_err("%s: ispif enable regulator failed", __func__);
return -EFAULT;
}
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_clk_info, ispif->clk,
ispif->num_clk, 1);
if (rc < 0) {
pr_err("%s: cannot enable clock, error = %d\n",
__func__, rc);
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_8626_reset_clk_info, reset_clk1,
ARRAY_SIZE(ispif_8626_reset_clk_info), 1);
if (rc < 0) {
pr_err("%s: cannot enable clock, error = %d",
__func__, rc);
} else {
/* This is set when device is 8x26 */
ispif->clk_idx = 2;
}
} else {
/* This is set when device is 8974 */
ispif->clk_idx = 1;
}
if (release) {
for (i = 0; i < ispif->vfe_info.num_vfe; i++) {
msm_camera_io_w_mb(ISPIF_STOP_INTF_IMMEDIATELY,
ispif->base + ISPIF_VFE_m_INTF_CMD_0(i));
msm_camera_io_w_mb(ISPIF_STOP_INTF_IMMEDIATELY,
ispif->base + ISPIF_VFE_m_INTF_CMD_1(i));
}
msm_camera_io_w_mb(ISPIF_IRQ_GLOBAL_CLEAR_CMD,
ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
}
init_completion(&ispif->reset_complete[VFE0]);
if (ispif->hw_num_isps > 1)
init_completion(&ispif->reset_complete[VFE1]);
/* initiate reset of ISPIF */
msm_camera_io_w(ISPIF_RST_CMD_MASK,
ispif->base + ISPIF_RST_CMD_ADDR);
timeout = wait_for_completion_timeout(
&ispif->reset_complete[VFE0], msecs_to_jiffies(500));
CDBG("%s: VFE0 done\n", __func__);
if (timeout <= 0) {
pr_err("%s: VFE0 reset wait timeout\n", __func__);
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_clk_info, ispif->clk,
ispif->num_clk, 0);
if (rc < 0) {
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_8626_reset_clk_info, reset_clk1,
ARRAY_SIZE(ispif_8626_reset_clk_info), 0);
if (rc < 0)
pr_err("%s: VFE0 reset wait timeout\n",
__func__);
}
/* Turn OFF regulators */
rc = msm_ispif_set_regulator(ispif, 0);
return -ETIMEDOUT;
}
if (ispif->hw_num_isps > 1) {
msm_camera_io_w(ISPIF_RST_CMD_1_MASK,
ispif->base + ISPIF_RST_CMD_1_ADDR);
timeout = wait_for_completion_timeout(
&ispif->reset_complete[VFE1],
msecs_to_jiffies(500));
CDBG("%s: VFE1 done\n", __func__);
if (timeout <= 0) {
pr_err("%s: VFE1 reset wait timeout\n", __func__);
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_clk_info, ispif->clk,
ispif->num_clk, 0);
/* Turn OFF regulators */
rc = msm_ispif_set_regulator(ispif, 0);
return -ETIMEDOUT;
}
}
if (ispif->clk_idx == 1) {
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_clk_info, ispif->clk,
ispif->num_clk, 0);
if (rc < 0) {
pr_err("%s: cannot disable clock, error = %d",
__func__, rc);
}
}
if (ispif->clk_idx == 2) {
rc = msm_cam_clk_enable(&ispif->pdev->dev,
ispif_8626_reset_clk_info, reset_clk1,
ARRAY_SIZE(ispif_8626_reset_clk_info), 0);
if (rc < 0) {
pr_err("%s: cannot disable clock, error = %d",
__func__, rc);
}
}
/* Turn OFF regulators after enabling the clocks*/
rc = msm_ispif_set_regulator(ispif, 0);
if (rc < 0) {
pr_err("%s: ispif disable regulator failed", __func__);
return -EFAULT;
}
return rc;
}
