Example #1
0
void ADC0_ISR ( void ) {
  ISR_ENTRY();
  uint32_t tmp = AD0GDR;
  uint16_t tmp2 = (uint16_t)(tmp >> 6) & 0x03FF;
  BatteryISRHandler(tmp2);
  /* trigger next convertion */
  T0MR1 += BOOZ2_ANALOG_BATTERY_PERIOD;
  /* lower clock         */
  T0EMR &= ~TEMR_EM1;
  VICVectAddr = 0x00000000;                 // clear this interrupt from the VIC
  ISR_EXIT();                               // recover registers and return
}
Example #2
0
void EXTINT0_ISR(void) {
  ISR_ENTRY();
  //ASSERT((max1168_status == MAX1168_SENDING_REQ),	DEBUG_MAX_1168, MAX1168_ERR_SPURIOUS_EOC);

  max1168_status = MAX1168_GOT_EOC;

  //SetBit(EXTINT, MAX1168_EOC_EINT);   /* clear extint0 */
  EXTINT = (1<<MAX1168_EOC_EINT);
  VICVectAddr = 0x00000000;             /* clear this interrupt from the VIC */

  ISR_EXIT();
}
Example #3
0
File: i2c_hw.c Project: sch17/wasp
void i2c0_ISR(void)
{
    ISR_ENTRY();

    uint32_t state = I2C_STATUS_REG;

    i2c_automaton(state);
    I2cClearIT();

    VICVectAddr = 0x00000000;             // clear this interrupt from the VIC
    ISR_EXIT();                           // recover registers and return
}
Example #4
0
void  NACKEDFUNC ATTR system_int (void) {        /* System Interrupt Handler */
    volatile AT91S_PITC * pPIT = AT91C_BASE_PITC;

    ISR_ENTRY();

    if (pPIT->PITC_PISR & AT91C_PITC_PITS) {  /* Check PIT Interrupt */
        *AT91C_AIC_EOICR = pPIT->PITC_PIVR;     /* Ack & End of Interrupt */
        timeval++;                              /* Increment Time Tick */
    } else {
        *AT91C_AIC_EOICR = 0;                   /* End of Interrupt */
    }

    ISR_EXIT();
}
void EXTINT2_ISR(void) {
  ISR_ENTRY();
  /* read dummy control byte reply */
  uint8_t foo __attribute__ ((unused)) = SSPDR;
  /* trigger 2 bytes read */
  SSPDR = 0;
  SSPDR = 0;
  /* enable timeout interrupt */
  SpiEnableRti();
  /* clear EINT2 */
  SetBit(EXTINT,MM_DRDY_EINT); /* clear EINT2 */

  VICVectAddr = 0x00000000;    /* clear this interrupt from the VIC */
  ISR_EXIT();
}
Example #6
0
void  NACKEDFUNC ATTR system_int (void) {        /* System Interrupt Handler */
  volatile AT91S_PITC * pPIT = AT91C_BASE_PITC;

  ISR_ENTRY();

  if (pPIT->PITC_PISR & AT91C_PITC_PITS) {  /* Check PIT Interrupt */
    timeval++;                              /* Increment Time Tick */
    if ((timeval % 500) == 0) {             /* 500ms Elapsed ? */
      *AT91C_PIOA_ODSR ^= LED4;             /* Toggle LED4 */
    }
    *AT91C_AIC_EOICR = pPIT->PITC_PIVR;     /* Ack & End of Interrupt */
  } else {
    *AT91C_AIC_EOICR = 0;                   /* End of Interrupt */
  }
  
  ISR_EXIT();
}
Example #7
0
static void SPI0_ISR(void) {
 ISR_ENTRY();

 static uint8_t cnt = 0;
 LED_TOGGLE(1);

 if ( bit_is_set(S0SPSR, SPIF)) { /* transfer complete  */
   uint8_t foo = S0SPDR;
   S0SPDR = cnt;
   cnt++;
 }

 /* clear_it */
 S0SPINT = 1<<SPI0IF;


 VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
 ISR_EXIT();
}
Example #8
0
static void SSP_ISR(void) {
    ISR_ENTRY();

    switch (imu_spi_selected) 
    {
        case SPI_SLAVE_MAX1168:
            max1168_got_interrupt_retrieve_values();
            imu_spi_selected = SPI_NONE;
            break;
        case SPI_SLAVE_MM:
            micromag_got_interrupt_retrieve_values();
            if (micromag_status == MM_DATA_AVAILABLE)
                imu_spi_selected = SPI_NONE;
            break;
    }

    VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
    ISR_EXIT();
}
Example #9
0
void SPI1_ISR(void) {
  ISR_ENTRY();

  static uint8_t cnt = 0;
  LED_TOGGLE(2);

  /* transfer complete  */
  if ( bit_is_set(S1SPSR, SPIF)) {
    uint8_t foo __attribute__ ((unused)) = S1SPDR;
    S1SPDR = cnt;
    cnt++;
  }

  /* clear_it */
  S1SPINT = 1<<SPI1IF;


 VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
 ISR_EXIT();
}
Example #10
0
void SPI1_ISR(void) {
 ISR_ENTRY();

 if (bit_is_set(SSPMIS, TXMIS)) {  /*  Tx half empty */
   SpiTransmit();
   SpiReceive();
   SpiEnableRti();
 }

 if ( bit_is_set(SSPMIS, RTMIS)) { /* Rx timeout      */
   SpiReceive();
   SpiClearRti();                  /* clear interrupt */
   SpiDisableRti();
   SpiDisable();
   spi_message_received = TRUE;
 }

 VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
 ISR_EXIT();
}
Example #11
0
void SPI1_ISR(void) {
  ISR_ENTRY();

  if (bit_is_set(SSPMIS, TXMIS)) {  /*  Tx fifo is half empty */
    SpiTransmit();
    SpiReceive();
    SpiEnableRti();
  }

  if (bit_is_set(SSPMIS, RTMIS)) { /* Rx fifo is not empty and no receive took place in the last 32 bits period */
    SpiUnselectCurrentSlave();
    SpiReceive();
    SpiDisableRti();
    SpiClearRti();                /* clear interrupt */
    SpiDisable();
    spi_message_received = TRUE;
  }

  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
  ISR_EXIT();
}
Example #12
0
static void SSP_ISR(void) {
	ISR_ENTRY();
	//start the device interrupt handler
	(*spi_current_package).spi_interrupt_handler();

	//unselect device, disable spi
	(*spi_current_package).slave_unselect();
	SpiClearRti();
	SpiDisableRti();
	SpiDisable();

	// check if more data to send
	if (spi_package_buffer_insert_idx != spi_package_buffer_extract_idx) {
		spi_transmit_single_package(&spi_package_buffer[spi_package_buffer_extract_idx]);
		spi_package_buffer_extract_idx++;
		spi_package_buffer_extract_idx %= SPI_PACKAGE_BUFFER_SIZE;
	} else {
		spi_transmit_running = 0; // clear running flag
	}
	VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
	ISR_EXIT();
}
Example #13
0
void SPI1_ISR(void)
{
  ISR_ENTRY();

  if (baro_scp_status == STA_INITIALISING) {
    uint8_t foo1 = SSPDR;
    uint8_t foo2 = SSPDR;
    baro_scp_status = STA_IDLE;
    foo1 = foo2;
  } else if (baro_scp_status == STA_IDLE) {

    uint8_t foo0 = SSPDR;
    baro_scp_temperature = SSPDR << 8;
    baro_scp_temperature += SSPDR;
    if (baro_scp_temperature & 0x2000) {
      baro_scp_temperature |= 0xC000;
    }
    baro_scp_temperature *= 5;

    uint8_t foo1 = SSPDR;
    uint32_t datard8 = SSPDR << 16;
    uint8_t foo2 = SSPDR;
    baro_scp_pressure = SSPDR << 8;
    baro_scp_pressure += SSPDR;
    baro_scp_pressure += datard8;
    baro_scp_pressure *= 25;
    baro_scp_available = TRUE;
    foo1 = foo2;
    foo0 = foo2;
  }

  ScpUnselect();
  SpiClearRti();
  SpiDisable();

  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
  ISR_EXIT();
}
Example #14
0
void TIMER0_ISR ( void ) {
  ISR_ENTRY();

  while (T0IR & TIMER0_IT_MASK) {
#ifdef USE_RADIO_CONTROL
    if (T0IR&TIR_CR2I) {
      ppm_isr();
      /* clear interrupt */
      T0IR = TIR_CR2I;
    }
#endif
#if USE_SERVOS_4017
    if (T0IR&TIR_MR0I) {
        servos_4017_isr();
        /* clear interrupt */
        T0IR = TIR_MR0I;
    }
#endif
  }
  VICVectAddr = 0x00000000;

  ISR_EXIT();
}
Example #15
0
void EXTINT_ISR(void) {
  ISR_ENTRY();

  if (num_irqs++ == 5)
  {
    /* switch SSEL P0.20 to be used as GPIO */
    PINSEL1 &= ~(3 << 8);
    IO0DIR |= 1 << 20;
    max11040_status = MAX11040_DATA2;
  }

  if (max11040_status == MAX11040_DATA2) {

#ifdef LOGGER
    max11040_timestamp[max11040_buf_in] = getclock();
#endif

    MaxmSelect();

    /* read data */
    SSP_Send(0xF0);
    SSP_Send(0x00);
    SSP_Send(0x00);
    SSP_Send(0x00);
    SSP_Send(0x00);
    SSP_Send(0x00);
    SSP_Send(0x00);

    max11040_count = 0;
  }

  /* clear EINT */
  SetBit(EXTINT, MAXM_DRDY_EINT);

  VICVectAddr = 0x00000000;    /* clear this interrupt from the VIC */
  ISR_EXIT();
}
Example #16
0
void SPI1_ISR(void) {
    ISR_ENTRY();

    while (bit_is_set(SSPSR, RNE)) {
        uint16_t data = SSPDR;

        if (bit_is_set(data, MAX3100_R_BIT)) { /* Data available */
            max3100_rx_buf[max3100_rx_insert_idx] = data & 0xff;
            max3100_rx_insert_idx++;  // automatic overflow because len=256
            read_bytes = true;
        }
        if (bit_is_set(data, MAX3100_T_BIT) && (max3100_status == MAX3100_STATUS_READING)) { /* transmit buffer empty */
            max3100_transmit_buffer_empty = true;
        }
    }
    SpiClearRti();                  /* clear interrupt */
    SpiDisableRti();
    SpiDisable ();
    Max3100Unselect();
    max3100_status = MAX3100_STATUS_IDLE;

    VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
    ISR_EXIT();
}
Example #17
0
void PWM_ISR ( void ) {
  ISR_ENTRY();
  if (servos_idx == 0) {
    /* lower serv0 reset */
    IO1CLR = _BV(SERV0_RESET_PIN);
    /* raise serv0 data  */
    IO1SET = _BV(SERV0_DATA_PIN);
    /* start pulsing serv0 */
    PWMMR_SERV0 = 0XFFF;
    /* stop pulsing serv1 */
    PWMMR_SERV1 = 0X0;
    PWMMR0 = servos_values[servos_idx];
    servos_delay = SERVO_REFRESH_TICS - servos_values[servos_idx];
    PWMLER = PWMLER_LATCH0 | PWMLER_LATCH_SERV0 | PWMLER_LATCH_SERV1;
    /* enable serv0 match interrupt, disable serv1 match interrupt */
    PWMMCR = PWMMCR_MR0R | PWMMCR_MRI_SERV0;
    servos_idx++;
  }
  else if (servos_idx < 4) {
    /* lower serv0 data */
    IO1CLR = _BV(SERV0_DATA_PIN);
    PWMMR0 = servos_values[servos_idx];
    servos_delay -= servos_values[servos_idx];
    PWMLER = PWMLER_LATCH0;
    servos_idx++;
  }
  else if (servos_idx == 4) {
    /* raise serv0 reset */
    IO1SET = _BV(SERV1_RESET_PIN);
    /* lower serv1 reset */
    IO1CLR = _BV(SERV1_RESET_PIN);
    /* raise serv1 data */
    IO1SET = _BV(SERV1_DATA_PIN);
    /* stop pulsing serv0 */
    PWMMR_SERV0 = 0;
    /* start pulsing serv1 */
    PWMMR_SERV1 = 0XFFF;
    /* disable serv0 interrupt, enable serv1 match interrupt */
    PWMMCR = PWMMCR_MR0R | PWMMCR_MRI_SERV1;
    /* fill next servo value */
    PWMMR0 = servos_values[servos_idx];
    servos_delay -= servos_values[servos_idx];
    /* latch PWM values */
    PWMLER = PWMLER_LATCH0 | PWMLER_LATCH_SERV0 | PWMLER_LATCH_SERV1;
    servos_idx++;
  }
  else if (servos_idx < _4015_NB_CHANNELS) {
    /* clear serv1 data */
    IO1CLR = _BV(SERV1_DATA_PIN);
    PWMMR0 = servos_values[servos_idx];
    servos_delay -= servos_values[servos_idx];
    PWMLER = PWMLER_LATCH0;
    servos_idx++;
  }
  else {
    /* raise serv1 reset */
    IO1SET = _BV(SERV1_RESET_PIN);
    /* command the delay */
    PWMMR0 = servos_delay;
    PWMLER = PWMLER_LATCH0;
    servos_idx = 0;
  }
  /* clear the interrupt */
  PWMIR = PWMIR_MRI_SERV1;
  PWMIR = PWMIR_MRI_SERV0;
  VICVectAddr = 0x00000000;
  ISR_EXIT();
}
Example #18
0
static void SSP_ISR(void) {
  int i;
  ISR_ENTRY();

  switch (max11040_status) {

    case MAX11040_RESET:
    {
      /* read dummy control byte reply */
      uint8_t foo __attribute__ ((unused));
      foo = SSPDR;
      foo = SSPDR;
      /* write configuration register */
      SSP_Send(0x60);       /* wr conf */
      SSP_Send(0x30);       /* adc0: en24bit, xtalen, no faultdis */
      for (i=1; i<MAXM_NB_ADCS; i++) {
        SSP_Send(0x20);     /* adcx: en24bit, no xtalen, no faultdis */
      }
      max11040_status = MAX11040_CONF;
      SSP_ClearRti();
    }
    break;

    case MAX11040_CONF:
    {
      /* read dummy control byte reply */
      uint8_t foo __attribute__ ((unused));
      foo = SSPDR;
      for (i=0; i<MAXM_NB_ADCS; i++) {
        foo = SSPDR;
      }
      /* write sampling instant register */
      SSP_Send(0x40);       /* wr instant */
      for (i=0; i<MAXM_NB_ADCS; i++) {
        SSP_Send(0);        /* adcx: no delay */
        SSP_Send(0);
        SSP_Send(0);
        SSP_Send(0);
      }
      max11040_status = MAX11040_INSTANT;
      SSP_ClearRti();
    }
    break;

    case MAX11040_INSTANT:
    {
      /* read dummy control byte reply */
      uint8_t foo __attribute__ ((unused));
      foo = SSPDR;
      for (i=0; i<MAXM_NB_ADCS; i++) {
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
      }
      /* write data rate control register */
      SSP_Send(0x50);    /* wr rate */
      SSP_Send(0x26);    /* adc: 250.1 sps */
      SSP_Send(0x00);
      max11040_status = MAX11040_RATE;
      SSP_ClearRti();
    }
    break;

    case MAX11040_RATE:
    {
      uint8_t foo __attribute__ ((unused));
      foo = SSPDR;
      foo = SSPDR;
      foo = SSPDR;
      /* read data register */
      SSP_Send(0xF0);       /* rd data */
      for (i=0; i<MAXM_NB_ADCS; i++) {
        SSP_Send(0x00);     /* adcx: data */
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
      }
      max11040_status = MAX11040_DATA;
      SSP_ClearRti();
    }
    break;

    case MAX11040_DATA:
    {
      uint8_t foo __attribute__ ((unused));
      foo = SSPDR;
      for (i=0; i<MAXM_NB_ADCS; i++) {
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
        foo = SSPDR;
      }

    /* read data */
      /* read data register */
      SSP_Send(0xF0);       /* rd data */
      for (i=0; i<MAXM_NB_ADCS; i++) {
        SSP_Send(0x00);     /* adc0: data */
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
      }

      SSP_ClearRti();
    }
    break;

    case MAX11040_DATA2:
    {
      uint8_t foo __attribute__ ((unused));

      SSP_ClearRti();
      SSP_ClearRxi();

      if (max11040_count <= MAXM_NB_CHAN+2)
      {
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
        SSP_Send(0x00);
      }

      if (max11040_count == 0) foo = SSPDR;

      max11040_values[max11040_buf_in][max11040_count]  = SSPDR << 16;
      max11040_values[max11040_buf_in][max11040_count] |= SSPDR << 8;
      max11040_values[max11040_buf_in][max11040_count] |= SSPDR;
      if (max11040_values[max11040_buf_in][max11040_count] & 0x800000)
        max11040_values[max11040_buf_in][max11040_count] |= 0xFF000000;

      max11040_count++;

      max11040_values[max11040_buf_in][max11040_count]  = SSPDR << 16;
      max11040_values[max11040_buf_in][max11040_count] |= SSPDR << 8;
      max11040_values[max11040_buf_in][max11040_count] |= SSPDR;
      if (max11040_values[max11040_buf_in][max11040_count] & 0x800000)
        max11040_values[max11040_buf_in][max11040_count] |= 0xFF000000;

      max11040_count++;

      if (max11040_count == MAXM_NB_CHAN)
      {
        MaxmUnselect();
        max11040_data = MAX11040_DATA_AVAILABLE;
        i = max11040_buf_in+1;
        if (i >= MAX11040_BUF_SIZE) i=0;
        if (i != max11040_buf_out) {
          max11040_buf_in = i;
        } else {
          //throw error;
        }
      }
    }
    break;

  }

  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
  ISR_EXIT();
}
Example #19
0
/* Interrupt handler for I2C0 interrupt */
static void I2C0_ISR(void)
{

	//sprintf((char*)buffer, "h ");
	//message_send_debug(COMM_1, buffer);
	//uint8_t buffer[200];	// string buffer for debug messages
	ISR_ENTRY();

	if (error_counter0 > I2C_PERMANENT_ERROR_LIMIT)
	{
		//uint8_t buffer[50];
		//sprintf(buffer, "i2c error limit %d \n", 1);
		//  sprintf((char*)buffer, package_buffer0[i2c_package_buffer0_current_idx].slave_address) ;
		//message_send_debug(COMM_1, buffer);
		//		debug_message_buffer("i2c error limit reached");
		debug_message_buffer_sprintf("i2c0 error limit reached. Dest: %i",
				package_buffer0[i2c_package_buffer0_current_idx].slave_address);

		if (i2c0_permanent_error_count++ % 256 == 0)
		{
			debug_message_buffer_sprintf(
					"i2c0 error limit reached. Total: %i errors.",
					i2c0_permanent_error_count);
		}

		package_buffer0[i2c_package_buffer0_current_idx].i2c_error_code
				= I2C_CODE_ERROR;//set error code to error
		//TODO set this to ok if everzthing was ok

		if (package_buffer0[i2c_package_buffer0_current_idx].i2c_done_handler
				!= NULL)
		{ // check if there is a package handler registered
			package_buffer0[i2c_package_buffer0_current_idx].i2c_done_handler(
					&(package_buffer0[i2c_package_buffer0_current_idx])); // call package handler
		}

		i2c_package_buffer0_insert_idx = (i2c_package_buffer0_insert_idx + 1)
				% I2C_PACKAGE_BUFFER_SIZE; // increment package insertion pointer
		error_counter0 = 0;
		if (i2c_package_buffer0_current_idx == i2c_package_buffer0_insert_idx)
		{ // no unhandled packages
			I2C0CONCLR = 1 << STAC;
			I2C0CONSET = 1 << STO; // generate I2C stop condition on the bus without restart
			I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
			i2c0_busy = 0; // release I2C resource
		}
		else
		{ // unhandled packages in package buffer
			if (!(package_buffer0[i2c_package_buffer0_current_idx].write_read
					== 1))
			{
				I2C0CONSET = 1 << STO; // generate stop condition on the bus if no repeated start is necessary
			}
			I2C0CONSET = 1 << STA; // generate "repeated start" condition on the bus -> next state: 0x10
			I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
		}
	}
	if (i2c0_busy == 1)
	{ //Return if Package error
		//message_debug_send(MAVLINK_COMM_1, 30, I2C0STAT);
		switch (I2C0STAT)
		{ // check current I2C0 state
		case 0x08: // I2C start condition has been generated on the bus -> transmit slave address and read/write bit -> next state: 0x18 or 0x40
			I2C0DAT
					= package_buffer0[i2c_package_buffer0_current_idx].slave_address
							| package_buffer0[i2c_package_buffer0_current_idx].direction;
			I2C0CONCLR = 1 << STAC; // do not restart (continue normal I2C operation)
			I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
			break;
		case 0x10: // "repeated start" condition has been generated on the bus -> transmit slave address and read/write bit -> next state: 0x18 or 0x40
			I2C0DAT
					= package_buffer0[i2c_package_buffer0_current_idx].slave_address
							| package_buffer0[i2c_package_buffer0_current_idx].direction;
			I2C0CONCLR = 1 << STAC;
			I2C0CONCLR = 1 << SIC;
			break;
		case 0x18: // slave address and write bit has been transmitted -> transmit first data byte -> next state: 0x28
			current_data_byte_i2c0 = 0;
			I2C0CONCLR = 1 << STAC;
			I2C0DAT
					= package_buffer0[i2c_package_buffer0_current_idx].data[current_data_byte_i2c0];
			current_data_byte_i2c0++;
			I2C0CONCLR = 1 << SIC;
			break;
		case 0x28: // data byte has been transmitted
			// if there's another byte to be transmitted, do it
			if (current_data_byte_i2c0
					< package_buffer0[i2c_package_buffer0_current_idx].length)
			{
				I2C0CONCLR = 1 << STAC;
				I2C0DAT
						= package_buffer0[i2c_package_buffer0_current_idx].data[current_data_byte_i2c0];
				current_data_byte_i2c0++;
				I2C0CONCLR = 1 << SIC;
			}
			// it the last byte has been transmitted, check if there are unhandled packages in the package buffer
			else
			{
				i2c_package_buffer0_current_idx
						= (i2c_package_buffer0_current_idx + 1)
								% I2C_PACKAGE_BUFFER_SIZE; // increment pointer to package in processing
				error_counter0 = 0;
				if (i2c_package_buffer0_current_idx
						== i2c_package_buffer0_insert_idx)
				{ // no unhandled packages
					I2C0CONCLR = 1 << STAC;
					I2C0CONSET = 1 << STO; // generate I2C stop condition on the bus without restart
					I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
					i2c0_busy = 0; // release I2C resource
				}
				else
				{ // unhandled packages in package buffer
					if (!(package_buffer0[i2c_package_buffer0_current_idx].write_read
							== 1))
					{
						I2C0CONSET = 1 << STO; // generate stop condition on the bus if no repeated start is necessary
					}
					I2C0CONSET = 1 << STA; // generate "repeated start" condition on the bus -> next state: 0x10
					I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
				}
			}
			break;
		case 0x20: // I2C error state detection
			I2C0CONSET = 1 << STO;
			I2C0CONSET = 1 << STA; // restart I2C state machine with current package
			error_counter0++;
			//debug_message_buffer("I2C error: slave address not acknowledged (write)\n");
			debug_message_buffer_sprintf(
					"I2C0 error: slave address not acknowledged (write). Dest: %i",
					package_buffer0[i2c_package_buffer0_current_idx].slave_address);

			//message_send_debug(COMM_1, buffer);
			I2C0CONCLR = 1 << SIC;
			break;
		case 0x30: // I2C error state detection
			I2C0CONSET = 1 << STO;
			I2C0CONSET = 1 << STA; // restart I2C state machine with current package
			error_counter0++;
			//		debug_message_buffer("I2C error: data not acknowledged\n");
			debug_message_buffer_sprintf(
					"I2C0 error: data not acknowledged. Dest: %i",
					package_buffer0[i2c_package_buffer0_current_idx].slave_address);

			//message_send_debug(COMM_1, buffer);
			I2C0CONCLR = 1 << SIC;
			break;
		case 0x38: // I2C error state detection
			I2C0CONSET = 1 << STA; // restart I2C state machine with current package
			error_counter0++;
			//		debug_message_buffer("I2C error: arbitration lost\n");
			debug_message_buffer_sprintf(
					"I2C0 error: arbitration lost. Dest: %i",
					package_buffer0[i2c_package_buffer0_current_idx].slave_address);

			//message_send_debug(COMM_1, buffer);
			I2C0CONCLR = 1 << SIC;
			break;
		case 0x40: // slave address and read bit has been transmitted -> clear interrupt and wait for first data byte -> next state: 0x50 or 0x58
			current_data_byte_i2c0 = 0;
			if (package_buffer0[i2c_package_buffer0_current_idx].length > 1)
				I2C0CONSET = 1 << AA; // if there's more than one byte to be received -> next state: 0x50
			else
				I2C0CONCLR = 1 << AAC; // if there's only one byte to be received -> next state: 0x58
			I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
			break;
		case 0x50: // data byte has been received
			package_buffer0[i2c_package_buffer0_current_idx].data[current_data_byte_i2c0]
					= I2C0DAT; // copy data byte to data array in I2C package
			current_data_byte_i2c0++; // increment data byte
			if ((current_data_byte_i2c0 + 1)
					< package_buffer0[i2c_package_buffer0_current_idx].length)
			{ // there's more than one byte left to be received
				I2C0CONSET = 1 << AA; // acknowledge next data byte -> next state: 0x50
			}
			else
			{ // there's only one byte left to be received
				I2C0CONCLR = 1 << AAC; // do not acknowledge next data byte -> next state: 0x58
			}
			I2C0CONCLR = 1 << SIC;
			break;
		case 0x58: // last data byte has been received
			package_buffer0[i2c_package_buffer0_current_idx].data[current_data_byte_i2c0]
					= I2C0DAT; // copy data byte to data array in I2C package
			I2C0CONSET = 1 << STO; // generate STOP condition on the I2C bus
			//uart0_transmit(package_buffer0[i2c_package_buffer0_current_idx].data[current_data_byte_i2c0]);
			if (package_buffer0[i2c_package_buffer0_current_idx].i2c_done_handler
					!= NULL)
			{ // check if there is a package handler registered
				package_buffer0[i2c_package_buffer0_current_idx].i2c_done_handler(
						&(package_buffer0[i2c_package_buffer0_current_idx])); // call package handler
			}
			i2c_package_buffer0_current_idx = (i2c_package_buffer0_current_idx
					+ 1) % I2C_PACKAGE_BUFFER_SIZE; // increment pointer to package in processing
			error_counter0 = 0;
			// check if there are unhandled packages in the package buffer
			if (i2c_package_buffer0_current_idx
					== i2c_package_buffer0_insert_idx)
			{ // no unhandled packages
				I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
				i2c0_busy = 0; // release I2C resource
			}
			else
			{ // unhandled packages in package buffer
				I2C0CONSET = 1 << STA; // generate "repeated start" condition on the bus -> next state: 0x10
				I2C0CONCLR = 1 << SIC; // clear I2C interrupt flag
			}
			break;
		case 0x48: // I2C error state detection
			I2C0CONSET = 1 << STO;
			I2C0CONSET = 1 << STA; // restart I2C state machine with current package
			error_counter0++;
			debug_message_buffer(
					"I2C0 error: slave address not acknowledged (read)\n");
			//message_send_debug(COMM_1, buffer);
			I2C0CONCLR = 1 << SIC;
			break;

		default: // I2C error state detection
			I2C0CONSET = 1 << STO;
			I2C0CONSET = 1 << STA; // restart I2C state machine with current package
			error_counter0++;
			debug_message_buffer_sprintf("I2C0 error: undefined I2C state: %i",I2C0STAT);
			debug_message_buffer_sprintf("I2C0 error: prior state: %X",i2c0stat_prior_state);
			//		message_send_debug(COMM_1, buffer);
			I2C0CONCLR = 1 << SIC;
		}
	}

	// Sum up errors
	global_data.i2c0_err_count += error_counter0;

	VICVectAddr = 0x00000000; // clear this interrupt from the VIC
	ISR_EXIT();
	// exit ISR
}
void TIMER0_ISR ( void ) {
  ISR_ENTRY();

  while (T0IR & TIMER0_IT_MASK) {

    if (T0IR&SYS_TICK_IT) {
      sys_tick_irq_handler();
      T0IR = SYS_TICK_IT;
    }

#if defined ACTUATORS && ( defined SERVOS_4017 || defined SERVOS_4015_MAT || defined SERVOS_PPM_MAT)
    if (T0IR&ACTUATORS_IT) {
#ifdef SERVOS_4017
      SERVOS_4017_ISR();
#endif
#ifdef SERVOS_4015_MAT
      Servos4015Mat_ISR();
#endif
#ifdef SERVOS_PPM_MAT
      ServosPPMMat_ISR();
#endif
      T0IR = ACTUATORS_IT;
    }
#endif /* ACTUATORS && (SERVOS_4017 || SERVOS_4015_MAT || SERVOS_PPM_MAT) */

#if defined RADIO_CONTROL && defined RADIO_CONTROL_TYPE_PPM
    if (T0IR&PPM_IT) {
      PPM_ISR();
      T0IR = PPM_IT;
    }
#endif
#ifdef TRIGGER_EXT
    if (T0IR&TRIGGER_IT) {
      TRIG_ISR();
      T0IR = TRIGGER_IT;
      LED_TOGGLE(3);
    }
#endif
#ifdef MB_SCALE
    if (T0IR&MB_SCALE_IT) {
      MB_SCALE_ICP_ISR();
      T0IR = MB_SCALE_IT;
    }
#endif
#ifdef MB_TACHO
    if (T0IR&MB_TACHO_IT) {
      MB_TACHO_ISR();
      T0IR = MB_TACHO_IT;
    }
#endif
#ifdef USE_PWM_INPUT1
    if (T0IR&PWM_INPUT_IT1) {
      PWM_INPUT_ISR_1();
      T0IR = PWM_INPUT_IT1;
    }
#endif
#ifdef USE_PWM_INPUT2
    if (T0IR&PWM_INPUT_IT2) {
      PWM_INPUT_ISR_2();
      T0IR = PWM_INPUT_IT2;
    }
#endif
#ifdef USE_AMI601
    if (T0IR&AMI601_IT) {
      AMI601_ISR();
      T0IR = AMI601_IT;
    }
#endif
  }
  VICVectAddr = 0x00000000;
  ISR_EXIT();
}
Example #21
0
void uart1_ISR(void)
{
  uint8_t iid;

  // perform proper ISR entry so thumb-interwork works properly
  ISR_ENTRY();

  // loop until not more interrupt sources
  while (((iid = U1IIR) & UIIR_NO_INT) == 0)
    {
    // identify & process the highest priority interrupt
    switch (iid & UIIR_ID_MASK)
      {
      case UIIR_RLS_INT:                // Receive Line Status
        U1LSR;                          // read LSR to clear
        break;

      case UIIR_CTI_INT:                // Character Timeout Indicator
      case UIIR_RDA_INT:                // Receive Data Available
        do
          {
          uint16_t temp;
          // calc next insert index & store character
          temp = (uart1_rx_insert_idx + 1) % UART1_RX_BUFFER_SIZE;
          uart1_rx_buffer[uart1_rx_insert_idx] = U1RBR;

          // check for more room in queue
          if (temp != uart1_rx_extract_idx)
            uart1_rx_insert_idx = temp; // update insert index
          }
        while (U1LSR & ULSR_RDR);

        break;

      case UIIR_THRE_INT:               // Transmit Holding Register Empty
        while (U1LSR & ULSR_THRE)
          {
          // check if more data to send
          if (uart1_tx_insert_idx != uart1_tx_extract_idx)
            {
            U1THR = uart1_tx_buffer[uart1_tx_extract_idx];
            uart1_tx_extract_idx++;
	    uart1_tx_extract_idx %= UART1_TX_BUFFER_SIZE;
            }
          else
            {
            // no
            uart1_tx_running = 0;       // clear running flag
            break;
            }
          }

        break;

      case UIIR_MS_INT:                 // MODEM Status
        U1MSR;                          // read MSR to clear
        break;

      default:                          // Unknown
        U1LSR;
        U1RBR;
        U1MSR;
        break;
      }
    }

  VICVectAddr = 0x00000000;             // clear this interrupt from the VIC
  ISR_EXIT();                           // recover registers and return
}
Example #22
0
void init_desc(void)
{
    // IDT entries
    ISR_ENTRY(0); ISR_ENTRY(1); ISR_ENTRY(2); ISR_ENTRY(3); ISR_ENTRY(4); ISR_ENTRY(5);
    ISR_ENTRY(6); ISR_ENTRY(7); ISR_ENTRY(8); ISR_ENTRY(9); ISR_ENTRY(10); ISR_ENTRY(11);
    ISR_ENTRY(12); ISR_ENTRY(13); ISR_ENTRY(14); ISR_ENTRY(15); ISR_ENTRY(16); ISR_ENTRY(17);
    ISR_ENTRY(18); ISR_ENTRY(19); ISR_ENTRY(20); ISR_ENTRY(21); ISR_ENTRY(22); ISR_ENTRY(23);
    ISR_ENTRY(24); ISR_ENTRY(25); ISR_ENTRY(26); ISR_ENTRY(27); ISR_ENTRY(28); ISR_ENTRY(29);
    ISR_ENTRY(30); ISR_ENTRY(31); 
    SYSG((u32)isr128, this_cpu.idt[0x80]);// SYStem Call goes here
    ISR_ENTRY(255);
    IRQ_ENTRY(0); IRQ_ENTRY(1); IRQ_ENTRY(2); IRQ_ENTRY(3); IRQ_ENTRY(4); IRQ_ENTRY(5);
    IRQ_ENTRY(6); IRQ_ENTRY(7); IRQ_ENTRY(8); IRQ_ENTRY(9); IRQ_ENTRY(10); IRQ_ENTRY(11);
    IRQ_ENTRY(12); IRQ_ENTRY(13); IRQ_ENTRY(14); IRQ_ENTRY(15);

    write_tss(&this_cpu.gdt[GDT_TSS_ENTRY], __KERNEL_DS, 0x0);

    this_cpu.idt_ptr.limit = IDT_ENTRY_NUM * sizeof(struct idt_desc_struct);
    this_cpu.idt_ptr.base = (u32)&(this_cpu.idt);
    gdt_flush((u32)&(this_cpu.gdt_ptr));
    init_8259A();
    irq_enable(2);
    memset((u8 *)&interrupt_handlers , 0, sizeof(interrupt_handlers));
    idt_flush((u32)&(this_cpu.idt_ptr));
    tss_flush();
}