/**
* @brief Get opmode of static memory.
* @param ChipSelect: Select Chip.
* This parameter can be one of the following values:
* SMC_CS0, SMC_CS1, SMC_CS2, SMC_CS3.
* @param OpMode: Static memory opmode returned by the function.
* This parameter is structure pointer which consists of following members:
* BusWidth, ReadBurstLen, ALE, StartAddr.
* @retval None
*/
void SMC_GetOpMode(uint8_t ChipSelect, SMC_OpModeTypeDef * OpMode)
{
OpMode_Reg get_opmode = { 0U };
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(OpMode));
assert_param(IS_SMC_CHIP_SELECT(ChipSelect));
switch (ChipSelect) {
case SMC_CS0:
get_opmode.Data = TSB_SMC->OPMODE0_0;
break;
case SMC_CS1:
get_opmode.Data = TSB_SMC->OPMODE0_1;
break;
case SMC_CS2:
get_opmode.Data = TSB_SMC->OPMODE0_2;
break;
case SMC_CS3:
get_opmode.Data = TSB_SMC->OPMODE0_3;
break;
default:
/* Do nothing */
break;
}
OpMode->BusWidth = (uint8_t) get_opmode.Bit.BusWidth;
OpMode->ReadBurstLen = (uint8_t) get_opmode.Bit.ReadBurstLen;
if (get_opmode.Bit.ALE == 1U) {
OpMode->ALE = ENABLE;
} else {
OpMode->ALE = DISABLE;
}
OpMode->StartAddr = (uint8_t) get_opmode.Bit.StartAddr;
}
/**
* @brief Initialize the specified SBI channel in I2C mode.
* @param SBIx: Select the SBI channel.
* This parameter can be one of the following values:
* TSB_SBI0, TSB_SBI1 or TSB_SBI2(TSB_SBI2 is invalid for TMPM332).
* @param InitI2CStruct: The structure containing SBI in I2C mode
* configuration.
* @retval None
*/
void SBI_InitI2C(TSB_SBI_TypeDef * SBIx, SBI_InitI2CTypeDef * InitI2CStruct)
{
uint32_t tmp = 0U;
uint32_t index = ((uint32_t) SBIx - (uint32_t) TSB_SBI0) / sizeof(TSB_SBI_TypeDef);
/* Check the parameters */
assert_param(IS_SBI_PERIPH(SBIx));
assert_param(IS_POINTER_NOT_NULL(InitI2CStruct));
assert_param(IS_SBI_I2C_ADDR(InitI2CStruct->I2CSelfAddr));
assert_param(IS_I2C_BIT_NUM(InitI2CStruct->I2CDataLen));
assert_param(IS_SBI_I2C_CLK_DIV(InitI2CStruct->I2CClkDiv));
assert_param(IS_FUNCTIONAL_STATE(InitI2CStruct->I2CACKState));
/* Set selfaddress for SBIx */
SBIx->I2CAR = InitI2CStruct->I2CSelfAddr & SBII2CAR_SA_MASK;
/* Set I2C bit length of transfer data */
tmp = SBIx->CR1 & SBICR1_BC_MASK;
tmp |= (InitI2CStruct->I2CDataLen << 5U);
/* Set I2C clock division */
tmp &= SBICR1_SCK_MASK;
tmp |= InitI2CStruct->I2CClkDiv;
SBIx_Sck[index] = InitI2CStruct->I2CClkDiv;
if (InitI2CStruct->I2CACKState) {
/* Set SBIxCR1<ACK> to enable generation of ACK clock */
tmp |= SBICR1_ACK_SET;
} else {
/* Clear SBIxCR1<ACK> to disable generation of ACK clock */
tmp &= SBICR1_ACK_CLEAR;
}
SBIx->CR1 = tmp;
/* Intilize SBI to I2C Slave-Rx mode */
SBIx->CR2 = SBICR2_PIN_SET | SBICR2_SBIM_I2C;;
}
/**
* @brief Get the access cycles of specified memory.
* @param ChipSelect: Select Chip.
* This parameter can be one of the following values:
* SMC_CS0, SMC_CS1, SMC_CS2, SMC_CS3.
* @param Cycles: Static memory access cycles returned by the function.
* This parameter is structure pointer which consists of following members:
* RC_Time, WC_Time, WP_Time, CEOE_Time, PC_Time, TR_Time.
* @retval None
*/
void SMC_GetCycles(uint8_t ChipSelect, SMC_CyclesTypeDef * Cycles)
{
Cycles_Reg get_cycles = { 0U };
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(Cycles));
assert_param(IS_SMC_CHIP_SELECT(ChipSelect));
switch (ChipSelect) {
case SMC_CS0:
get_cycles.Data = TSB_SMC->SRAM_CYCLES0_0;
break;
case SMC_CS1:
get_cycles.Data = TSB_SMC->SRAM_CYCLES0_1;
break;
case SMC_CS2:
get_cycles.Data = TSB_SMC->SRAM_CYCLES0_2;
break;
case SMC_CS3:
get_cycles.Data = TSB_SMC->SRAM_CYCLES0_3;
break;
default:
/* Do nothing */
break;
}
Cycles->RC_Time = (uint8_t) get_cycles.Bit.RC_Time;
Cycles->WC_Time = (uint8_t) get_cycles.Bit.WC_Time;
Cycles->CEOE_Time = (uint8_t) get_cycles.Bit.CEOE_Time;
Cycles->WP_Time = (uint8_t) get_cycles.Bit.WP_Time;
Cycles->PC_Time = (uint8_t) get_cycles.Bit.PC_Time;
Cycles->TR_Time = (uint8_t) get_cycles.Bit.TR_Time;
}
/**
* @brief Configure the specified ADC monitor module.
* @param ADx: Select ADC unit.
* This parameter can be one of the following values:
* TSB_ADA, TSB_ADB
* @param ADCMPx: Select which compare control register will be used.
* This parameter can be one of the following values:
* ADC_CMPCR_0 or ADC_CMPCR_1.
* @param Monitor: The structure containing ADC monitor configuration.
* @retval None.
*/
void ADC_ConfigMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, ADC_MonitorTypeDef * Monitor)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_ADC_UNIT(ADx));
assert_param(IS_ADC_CMPCRx(ADCMPx));
assert_param(IS_POINTER_NOT_NULL(Monitor));
if (ADx == TSB_ADA) {
assert_param(IS_ADCA_INPUT_CHANNEL(Monitor->CmpChannel));
} else {
assert_param(IS_ADCB_INPUT_CHANNEL(Monitor->CmpChannel));
}
assert_param(IS_ADC_CMPCNT(Monitor->CmpCnt));
assert_param(IS_ADC_CMPCONDITION(Monitor->Condition));
assert_param(IS_ADC_CMPMODE(Monitor->CntMode));
assert_param(IS_ADC_CMPVALUE_12BIT(Monitor->CmpValue));
tmp |= (uint32_t) (Monitor->CmpChannel);
tmp |= (uint32_t) (Monitor->Condition) << 4U;
tmp |= (uint32_t) (Monitor->CntMode) << 5U;
tmp |= (uint32_t) (Monitor->CmpCnt - 1U) << 8U;
if (ADCMPx == ADC_CMPCR_0) {
ADx->CMPCR0 = tmp;
ADx->CMP0 = Monitor->CmpValue;
} else {
ADx->CMPCR1 = tmp;
ADx->CMP1 = Monitor->CmpValue;
}
}
/**
* @brief Set the monitor function of the specified ADC unit and enable it.
* @param ADx: Select ADC unit
* This parameter can be one of the following values:
* For M370: TSB_ADA, TSB_ADB
* For M372/3/4: TSB_ADB
* @param Monitor: The structure containing ADC Monitor configuration
* Refer to the members of ADC_MonitorTypeDef in .h file for more detail usage.
* @retval None
*/
void ADC_SetMonitor(TSB_AD_TypeDef * ADx, ADC_MonitorTypeDef * Monitor)
{
uint32_t tmp = 0U;
uint32_t tmpComp = 0U;
/* Check the parameters */
assert_param(IS_ADC_UNIT(ADx));
assert_param(IS_POINTER_NOT_NULL(Monitor));
assert_param(IS_ADC_CMPCRx(Monitor->CMPCRx));
assert_param(IS_ADC_REGx(Monitor->ResultREGx));
assert_param(IS_ADC_CMPTIMES(Monitor->CmpTimes));
assert_param(IS_ADC_CMPCONDITION(Monitor->Condition));
assert_param(IS_ADC_CMPVALUE_12BIT(Monitor->CmpValue));
tmpComp = Monitor->CmpValue << 4U; /* 12bit mode: use bit15 to bit4 */
tmp |= (uint32_t) Monitor->ResultREGx;
tmp |= (uint32_t) Monitor->Condition << 4U;
tmp |= (uint32_t) (Monitor->CmpTimes - 1U) << 8U;
tmp |= (uint32_t) (0x01U << 7U); /* set bit 7: ADxCMPCRn<CMPnEN> to enable Monitor function */
if (Monitor->CMPCRx == ADC_CMPCR_0) {
ADx->CMPCR0 = tmp;
ADx->CMP0 = tmpComp;
} else {
ADx->CMPCR1 = tmp;
ADx->CMP1 = tmpComp;
}
}
/**
* @brief Configure the flip-flop function.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* M370: TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7.
* M372: TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB6, TSB_TB7.
* M373: TSB_TB3, TSB_TB6, TSB_TB7.
* M374: TSB_TB3, TSB_TB6.
* @param FFStruct: The structure containing TMRB flip-flop configuration
* @retval None
*/
void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct)
{
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(FFStruct));
assert_param(IS_TMRB_OUT_PERIPH(TBx));
assert_param(IS_TMRB_FLIPFLOP_CTRL(FFStruct->FlipflopCtrl));
assert_param(IS_TMRB_FLIPFLOP_TRG(FFStruct->FlipflopReverseTrg));
/* Configure the flip-flop function of TBx */
TBx->FFCR = (FFStruct->FlipflopCtrl | FFStruct->FlipflopReverseTrg);
}
/**
* @brief Fill the DMA setting data of specified channel of the specified DMAC unit to RAM.
* @param DMACx: Select DMAC unit.
* This parameter can be one of the following values:
* DMAC_UNIT_A : DMAC unit A
* DMAC_UNIT_B : DMAC unit B
* @param Channel: Select channel.
* This parameter can be one of the following values:
* DMAC_ADC0_END,
* DMAC_ADC1_END,
* DMAC_DAC0_TRG,
* DMAC_DAC1_TRG,
* DMAC_SSP0_RX,
* DMAC_SSP0_TX,
* DMAC_SSP1_RX,
* DMAC_SSP1_TX,
* DMAC_SSP2_RX,
* DMAC_SSP2_TX,
* DMAC_FUART4_RX,
* DMAC_FUART4_TX,
* DMAC_FUART5_RX,
* DMAC_FUART5_TX,
* DMAC_SIO0_RX,
* DMAC_SIO0_TX,
* DMAC_SIO1_RX,
* DMAC_SIO1_TX,
* DMAC_SIO2_RX,
* DMAC_SIO2_TX,
* DMAC_SIO3_RX,
* DMAC_SIO3_TX,
* DMAC_SBI0_RXTX,
* DMAC_SBI1_RXTX,
* DMAC_SBI2_RXTX,
* DMAC_TMRB0_CMP_MATCH,
* DMAC_TMRB1_CMP_MATCH,
* DMAC_TMRB2_CMP_MATCH,
* DMAC_TMRB3_CMP_MATCH,
* DMAC_TMRB4_CMP_MATCH,
* DMAC_PIN,
* DMAC_SW_TRG
* @param InitStruct: the structure contain the DMA setting values.
* @retval None
*/
void DMAC_FillInitData(TSB_DMA_TypeDef * DMACx, DMAC_Channel Channel, DMAC_InitTypeDef * InitStruct)
{
DMAC_PrimaryAlt PriAlt = DMAC_PRIMARY;
uint32_t Addr = 0U;
uint32_t tmpCtrl = 0U;
assert_param(IS_DMAC_UNIT(DMACx));
assert_param(IS_DMAC_CHANNEL_ALL(Channel));
assert_param(IS_POINTER_NOT_NULL(InitStruct));
assert_param(IS_DMAC_CYCLECTRL(InitStruct->Mode));
assert_param(IS_DMAC_NEXT_USEBURST(InitStruct->NextUseBurst));
assert_param(IS_DMAC_TXNUM(InitStruct->TxNum));
assert_param(IS_DMAC_ARBITRATION(InitStruct->ArbitrationMoment));
assert_param(IS_DMAC_BIT_WIDTH(InitStruct->SrcWidth));
assert_param(IS_DMAC_INCWIDTH(InitStruct->SrcInc));
assert_param(IS_DMAC_BIT_WIDTH(InitStruct->DstWidth));
assert_param(IS_DMAC_INCWIDTH(InitStruct->DstInc));
assert_param(IS_DMAC_INCWIDTH_VALID
((uint32_t) InitStruct->SrcWidth, (uint32_t) InitStruct->SrcInc));
assert_param(IS_DMAC_INCWIDTH_VALID
((uint32_t) InitStruct->DstWidth, (uint32_t) InitStruct->DstInc));
PriAlt = DMAC_GetPrimaryAlt(DMACx, Channel);
if (PriAlt == DMAC_PRIMARY) {
Addr = DMAC_GetBaseAddr(DMACx, DMAC_PRIMARY);
} else {
Addr = DMAC_GetBaseAddr(DMACx, DMAC_ALTERNATE);
}
/* add offset for channel, each channel use (4 x uint32_t) RAM */
Addr += (16U * (uint32_t) Channel);
/* make setting data for 'control data' */
tmpCtrl |= (uint32_t) InitStruct->Mode;
tmpCtrl |= (uint32_t) InitStruct->NextUseBurst << 3U;
tmpCtrl |= (uint32_t) (InitStruct->TxNum - 1U) << 4U;
tmpCtrl |= (uint32_t) InitStruct->ArbitrationMoment << 14U;
tmpCtrl |= (uint32_t) InitStruct->SrcWidth << 24U;
tmpCtrl |= (uint32_t) InitStruct->SrcInc << 26U;
tmpCtrl |= (uint32_t) InitStruct->DstWidth << 28U;
tmpCtrl |= (uint32_t) InitStruct->DstInc << 30U;
/* write setting data to right address */
*((uint32_t *) (Addr)) = InitStruct->SrcEndPointer;
*((uint32_t *) (Addr + 4U)) = InitStruct->DstEndPointer;
*((uint32_t *) (Addr + 8U)) = tmpCtrl;
*((uint32_t *) (Addr + 12U)) = (uint32_t) 0U;
}
/**
* @brief Initialize and configure the specified Full UART channel.
* @param FUARTx: Select the Full UART channel.
* This parameter can be one of the following values:
* FUART0.
* @param InitStruct: The structure containing basic Full UART configuration
* @retval None
*/
void FUART_Init(TSB_FUART_TypeDef * FUARTx, FUART_InitTypeDef * InitStruct)
{
uint32_t tmp = 0U;
uint32_t fuartclk = 0U;
uint32_t ibd = 0U; /* Interger part of baud rate divisor */
uint32_t fbd = 0U; /* Franctional part of baud rate divisor */
uint32_t br = InitStruct->BaudRate; /* BaudRate */
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(InitStruct));
assert_param(IS_FUART_PERIPH(FUARTx));
assert_param(IS_FUART_BAUDRATE(InitStruct->BaudRate));
assert_param(IS_FUART_DATA_BITS(InitStruct->DataBits));
assert_param(IS_FUART_STOPBITS(InitStruct->StopBits));
assert_param(IS_FUART_PARITY(InitStruct->Parity));
assert_param(IS_FUART_MODE(InitStruct->Mode));
assert_param(IS_FUART_FLOW_CTRL(InitStruct->FlowCtrl));
/* Get UARTCLK */
SystemCoreClockUpdate();
fuartclk = SystemCoreClock; /* UARTCLK = fsys */
ibd = fuartclk / (16U * br);
fbd = (8U * fuartclk + br - 128U * ibd * br) / (2U * br);
if (fbd == 0U) {
fbd = 1U; /* Franctional part of baud rate divisor can not be 0x00 */
} else {
/* do nothing */
}
FUARTx->IBDR = ibd; /* Set interger part of baud rate divisor */
FUARTx->FBDR = fbd; /* Set franctional part of baud rate divisor */
tmp = FUARTx->LCR_H;
tmp &= LCR_H_WLEN_MASK;
tmp |= InitStruct->DataBits;
tmp &= LCR_H_STP2_MASK;
tmp |= InitStruct->StopBits;
tmp &= LCR_H_PARITY_MASK;
tmp |= InitStruct->Parity;
FUARTx->LCR_H = tmp; /* Set DataBits, StopBits, Parity */
tmp &= CR_FLOW_CTRL_MASK;
tmp |= InitStruct->FlowCtrl;
tmp &= CR_MODE_MASK;
tmp |= InitStruct->Mode;
FUARTx->CR = tmp; /* Set Flow Control, Mode */
}
/**
* @brief Initialize the SSP through the data in structure SSP_InitTypeDef
* @param InitStruct: parameters to configure SSP mode
* @retval None
*/
void SSP_Init(SSP_InitTypeDef * InitStruct)
{
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(InitStruct));
SSP_SetFrameFormat(InitStruct->FrameFormat);
SSP_SetClkPreScale(InitStruct->PreScale, InitStruct->ClkRate);
SSP_SetClkPolarity(InitStruct->ClkPolarity);
SSP_SetClkPhase(InitStruct->ClkPhase);
SSP_SetDataSize(InitStruct->DataSize);
SSP_SetMSMode(InitStruct->Mode);
}
/**
* @brief Read SMC memory interface configuration.
* @param Config: Interface configuration returned by the function.
* This parameter is structure pointer which consists of following members:
* MemoryType, MemoryChips, MemoryWidth.
* @retval None
*/
void SMC_GetIFConfig(SMC_IFConfigTypeDef * Config)
{
IFConfig_Reg cfg = { 0U };
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(Config));
cfg.Data = TSB_SMC->MEMIF_CFG;
Config->MemoryType = (uint8_t) cfg.Bit.MemoryType;
Config->MemoryChips = (uint8_t) cfg.Bit.MemoryChips;
Config->MemoryWidth = (uint8_t) cfg.Bit.MemoryWidth;
}
/**
* @brief Initialize WDT.
* @param InitStruct: The structure containing basic WD configuration.
* @retval None
*/
void WDT_Init(WDT_InitTypeDef * InitStruct)
{
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(InitStruct));
assert_param(IS_WDT_DETECT_TIME(InitStruct->DetectTime));
assert_param(IS_WDT_OUTPUT(InitStruct->OverflowOutput));
/* Set WDT Detection time */
WDT_SetDetectTime(InitStruct->DetectTime);
/* Set WDTMOD<RESCR> to Select function of WDT when counter overflow */
WDT_SetOverflowOutput(InitStruct->OverflowOutput);
}
/**
* @brief Send direct command to static memory to update registers(opmode, cycles)
* @param Cmd: Command type and specified memory.
* This parameter is structure pointer which consists of following members:
* CmdType, ChipSelect.
* @retval None
*/
void SMC_SendDirectCMD(SMC_DirectCMDTypeDef * Cmd)
{
DirectCMD_Reg command = { 0U };
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(Cmd));
assert_param(IS_SMC_CHIP_SELECT(Cmd->ChipSelect));
assert_param(IS_SMC_CMD(Cmd->CmdType));
command.Bit.CmdType = Cmd->CmdType;
command.Bit.ChipSelect = Cmd->ChipSelect;
TSB_SMC->DIRECT_CMD = command.Data;
}
/**
* @brief RMC registers initial, the basic RMC configuration set to the specified RMC channel.
* @param RMCx: Select the RMC channel.
* This parameter can be one of the following values:
* TSB_RMC0, TSB_RMC1(Only for M360/M362/M364)
* RMC_InitStruct: The structure containing the basic RMC configuration.
* @retval None
*/
void RMC_Init(TSB_RMC_TypeDef * RMCx, RMC_InitTypeDef * RMC_InitStruct)
{
assert_param(IS_POINTER_NOT_NULL(RMC_InitStruct));
RMC_SetRxCtrl(RMCx, DISABLE);
RMC_SetLeaderDetection(RMCx, RMC_InitStruct->LeaderPara);
RMC_SetFallingEdgeINT(RMCx, RMC_InitStruct->FallingEdgeINTState);
RMC_SetSignalRxMethod(RMCx, RMC_InitStruct->SignalRxMethod);
RMC_SetRxTrg(RMCx, RMC_InitStruct->LowWidth, RMC_InitStruct->MaxDataBitCycle);
RMC_SetThreshold(RMCx, RMC_InitStruct->LargerThreshold, RMC_InitStruct->SmallerThreshold);
RMC_SetInputSignalReversed(RMCx, RMC_InitStruct->InputSignalReversedState);
RMC_SetNoiseCancellation(RMCx, RMC_InitStruct->NoiseCancellationTime);
}
/**
* @brief Configure the flip-flop function.
* @param T16Ax: Select the TMR16A channel.
* This parameter can be one of the following values:
* TSB_T16A0, TSB_T16A1, TSB_T16A2, TSB_T16A3, TSB_T16A4, TSB_T16A5, TSB_T16A6.
* @param FFStruct: The structure containing TMR16A flip-flop configuration
* @retval None
*/
void TMR16A_SetFlipFlop(TSB_T16A_TypeDef * T16Ax, TMR16A_FFOutputTypeDef * FFStruct)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(FFStruct));
assert_param(IS_TMR16A_ALL_PERIPH(T16Ax));
assert_param(IS_TMR16A_FLIPFLOP_CTRL(FFStruct->TMR16AFlipflopCtrl));
assert_param(IS_TMR16A_FLIPFLOP_TRG(FFStruct->TMR16AFlipflopReverseTrg));
/* Configure the flip-flop function of T16Ax */
tmp = T16Ax->CR;
tmp &= CR_FF_MASK;
tmp |= (FFStruct->TMR16AFlipflopCtrl | FFStruct->TMR16AFlipflopReverseTrg);
T16Ax->CR = tmp;
}
/**
* @brief Write data to the specified page.
* @param PageAddr: The page start address.
* Data: The pointer to data buffer to be written into the page.
* The data size should be 256Byte.
* @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
*
*/
FC_Result FC_WritePage(uint32_t PageAddr, uint32_t * Data)
{
uint8_t BlockNum = FC_BLOCK_4;
assert_param(IS_FC_ADDR(PageAddr)); /* Check whether it is in the flash address range */
assert_param(IS_FC_PAGE_ADDR(PageAddr)); /* Check whether it is a page start address */
assert_param(IS_POINTER_NOT_NULL(Data));
BlockNum = FC_AddrToBlockNum(PageAddr);
if (ENABLE == FC_GetBlockProtectState(BlockNum)) {
return FC_ERROR_PROTECTED;
}
return __FC_WritePage(PageAddr, Data);
}
/**
* @brief Set opmode of static memory.
* @param OpMode: Static memory opmode.
* This parameter is structure pointer which consists of following members:
* BusWidth, ReadBurstLen, ALE.
* @retval None
*/
void SMC_SetOpMode(SMC_OpModeTypeDef * OpMode)
{
OpMode_Reg set_opmode = { 0U };
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(OpMode));
assert_param(IS_SMC_DATA_BUS(OpMode->BusWidth));
assert_param(IS_SMC_READ_BURST(OpMode->ReadBurstLen));
assert_param(IS_FUNCTIONAL_STATE(OpMode->ALE));
set_opmode.Bit.BusWidth = OpMode->BusWidth;
set_opmode.Bit.ReadBurstLen = OpMode->ReadBurstLen;
if (OpMode->ALE == ENABLE) {
set_opmode.Bit.ALE = 1U;
} else {
set_opmode.Bit.ALE = 0U;
}
TSB_SMC->SET_OPMODE = set_opmode.Data;
}
/**
* @brief Initialize TMRD timing parameters.
* @param TDx: Select the TMRD channel.
* This parameter can be one of the following values:
* TSB_TD0, TSB_TD1.
* @param TimingStruct: The pointer of TMRD timing
* parameters structure.
* @retval None
*/
void TMRD_SetInitTiming(TSB_TD_TypeDef * TDx, TMRD_TimingTypeDef * TimingStruct)
{
/* Check the parameters */
assert_param(IS_TMRD_ALL_PERIPH(TDx));
assert_param(IS_POINTER_NOT_NULL(TimingStruct));
/* Set TDxRGm */
TDx->RG0 = TimingStruct->Cycle;
TDx->RG1 = TimingStruct->LeadingTiming0;
TDx->RG2 = TimingStruct->TrailingTiming0;
TDx->RG3 = TimingStruct->LeadingTiming1;
TDx->RG4 = TimingStruct->TrailingTiming1;
if (TDx == TSB_TD0) {
TSB_TD0->RG5 = TimingStruct->PhaseShiftTiming;
} else {
/* Do nothing */
}
}
/**
* @brief Select the interrupt to be generated for each of programs 0 to 5
* of the specified ADC unit.
* @param ADx: Select ADC unit
* This parameter can be one of the following values:
* For M370: TSB_ADA, TSB_ADB
* For M372/3/4: TSB_ADB
* @param TrgProgINT: The structure containing interrupt configuration for all of PMD Trigger Programs
* Refer the members of PMD_TrgProgINTTypeDef in .h file for more detail usage.
* @retval None
*/
void ADC_SetPMDTrgProgINT(TSB_AD_TypeDef * ADx, PMD_TrgProgINTTypeDef * TrgProgINT)
{
/* Check the parameters */
assert_param(IS_ADC_UNIT(ADx));
assert_param(IS_POINTER_NOT_NULL(TrgProgINT));
assert_param(IS_PMD_INT_NAME(TrgProgINT->INTProg0));
assert_param(IS_PMD_INT_NAME(TrgProgINT->INTProg1));
assert_param(IS_PMD_INT_NAME(TrgProgINT->INTProg2));
assert_param(IS_PMD_INT_NAME(TrgProgINT->INTProg3));
assert_param(IS_PMD_INT_NAME(TrgProgINT->INTProg4));
assert_param(IS_PMD_INT_NAME(TrgProgINT->INTProg5));
/* currently ADxPINTSn is defined as uint32_t */
ADx->PINTS0 = (uint32_t) TrgProgINT->INTProg0;
ADx->PINTS1 = (uint32_t) TrgProgINT->INTProg1;
ADx->PINTS2 = (uint32_t) TrgProgINT->INTProg2;
ADx->PINTS3 = (uint32_t) TrgProgINT->INTProg3;
ADx->PINTS4 = (uint32_t) TrgProgINT->INTProg4;
ADx->PINTS5 = (uint32_t) TrgProgINT->INTProg5;
}
/**
* @brief Write data to the specified page.
* @param PageAddr: The page start address.
* Data: The pointer to data buffer to be written into the page.
* The data size should be 256Byte.
* @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
*
*/
FC_Result FC_WritePage(uint32_t PageAddr, uint32_t * Data)
{
FC_Result retval = FC_SUCCESS;
volatile uint32_t *addr1 = (uint32_t *) (FLASH_START_ADDR + FC_CMD_BC1_ADDR);
volatile uint32_t *addr2 = (uint32_t *) (FLASH_START_ADDR + FC_CMD_BC2_ADDR);
volatile uint32_t *addr3 = (uint32_t *) PageAddr;
uint32_t counter = FC_WRITE_PAGE_OVER_TIME;
uint32_t i = 0U;
uint32_t *source = Data;
uint8_t BlockNum = 0U;
assert_param(IS_FC_ADDR(PageAddr)); /* Check whether it is in the flash address range */
assert_param(IS_FC_PAGE_ADDR(PageAddr)); /* Check whether it is a page start address */
assert_param(IS_POINTER_NOT_NULL(Data));
BlockNum = FC_AddrToBlockNum(PageAddr);
if (ENABLE == FC_GetBlockProtectState(BlockNum)) {
retval = FC_ERROR_PROTECTED;
} else {
*addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
*addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
*addr1 = (uint32_t) 0x000000A0; /* bus cycle 3 */
for (i = 0U; i < FC_PAGE_SIZE; i++) { /* bus cycle 4~67 */
*addr3 = *source;
source++;
}
__DSB();
while (BUSY == FC_GetBusyState()) { /* check if FLASH is busy with overtime counter */
if (!(counter--)) { /* check overtime */
retval = FC_ERROR_OVER_TIME;
break;
} else {
/* Do nothing */
}
}
}
return retval;
}
/**
* @brief Adjust the access cycle of static memory and should be set to satisfy
* the A.C. specifications of the memory to be used.
* @param Cycles: Static memory access cycles.
* This parameter is structure pointer which consists of following members:
* RC_Time, WC_Time, WP_Time, CEOE_Time, PC_Time, TR_Time.
* @retval None
*/
void SMC_SetCycles(SMC_CyclesTypeDef * Cycles)
{
Cycles_Reg set_cycles = { 0U };
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(Cycles));
assert_param(IS_SMC_READ_CYCLE_TIME(Cycles->RC_Time));
assert_param(IS_SMC_WRITE_CYCLE_TIME(Cycles->WC_Time));
assert_param(IS_SMC_CEOE_DELAY_CYCLE_TIME(Cycles->CEOE_Time));
assert_param(IS_SMC_WE_PULSE_CYCLE_TIME(Cycles->WP_Time));
assert_param(IS_SMC_PAGE_CYCLE_TIME(Cycles->PC_Time));
assert_param(IS_SMC_TURN_AROUND_CYCLE_TIME(Cycles->TR_Time));
set_cycles.Bit.RC_Time = Cycles->RC_Time;
set_cycles.Bit.WC_Time = Cycles->WC_Time;
set_cycles.Bit.CEOE_Time = Cycles->CEOE_Time;
set_cycles.Bit.WP_Time = Cycles->WP_Time;
set_cycles.Bit.PC_Time = Cycles->PC_Time;
set_cycles.Bit.TR_Time = Cycles->TR_Time;
TSB_SMC->SET_CYCLES = set_cycles.Data;
}
/**
* @brief Initialize the specified TMRB channel.
* @param TBx: Select the TMRB channel.
* This parameter can be one of the following values:
* TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7, TSB_TB8, TSB_TB9.
* @param InitStruct: The structure containing basic TMRB configuration.
* @retval None
*/
void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_POINTER_NOT_NULL(InitStruct));
assert_param(IS_TMRB_ALL_PERIPH(TBx));
assert_param(IS_TMRB_MODE(InitStruct->Mode));
if (InitStruct->Mode != 0U) {
assert_param(IS_TMRB_CLK_DIV(InitStruct->ClkDiv));
} else {
/* Do nothing */
}
assert_param(IS_TMRB_VALUE(InitStruct->Cycle));
assert_param(IS_TMRB_UC_CTRL(InitStruct->UpCntCtrl));
assert_param(IS_TMRB_VALUE(InitStruct->Duty));
assert_param(IS_VALID_DUTY(InitStruct->Duty, InitStruct->Cycle));
/* Configure source clock for TBx */
tmp = TBx->MOD;
tmp &= MOD_BIT7_CLEAR;
tmp &= MOD_CLK_CLE_CLEAR;
if (InitStruct->Mode != 0U) {
/* Use internal clock, set the prescaler */
tmp |= InitStruct->ClkDiv;
} else {
/* Use external clock */
tmp |= InitStruct->Mode;
}
/* Set up-counter running mode */
tmp |= InitStruct->UpCntCtrl;
tmp |= MOD_TBCP_SET;
TBx->MOD = tmp;
/* Write duty into RG0 */
TBx->RG0 = InitStruct->Duty;
/* Write cycle into RG1 */
TBx->RG1 = InitStruct->Cycle;
}
/**
* @brief Initialize the DAC.
* @param DACx: Select the DAC channel.
* This parameter can be one of the following values:
* TSB_DA0, TSB_DA1
* @param InitStruct: The structure containing basic DAC configuration including clear DAC request,
* set post adjustment for VOUTHOLD time, pre adjustment for VOUTHOLD time,
* offset setting of output waveform, amplitude setting of output waveform,
* output waveform selection, trigger selection and trigger function.
* @retval None
*/
void DAC_Init(TSB_DA_TypeDef * DACx, DAC_InitTypeDef * InitStruct)
{
uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DACx));
assert_param(IS_POINTER_NOT_NULL(InitStruct));
assert_param(IS_DAC_CLEAR(InitStruct->DACClear));
assert_param(IS_DAC_ADJTIME(InitStruct->PostTime));
assert_param(IS_DAC_ADJTIME(InitStruct->PreTime));
assert_param(IS_DAC_OFFSET(InitStruct->Offset));
assert_param(IS_DAC_AMPSEL(InitStruct->AmpSel));
assert_param(IS_DAC_TRGSEL(InitStruct->TrgSel));
assert_param(IS_DAC_TRGFUNC(InitStruct->TrgFunc));
assert_param(IS_DAC_DMAFUNC(InitStruct->DMAFunc));
assert_param(IS_DAC_WAVE(InitStruct->Wave));
/*Clear DAC */
tmp = DACx->TCTL;
tmp &= DAC_CLEAR_MASK;
tmp |= InitStruct->DACClear;
DACx->TCTL = tmp;
/*Set time to VOUTHOLD adjustment register */
tmp = (uint8_t) (InitStruct->PostTime << 4U);
tmp += InitStruct->PreTime;
DACx->VCTL = tmp;
/*set DACDCTLx(output control register) */
tmp = (uint8_t) (InitStruct->Offset << 18U);
tmp += (uint8_t) (InitStruct->AmpSel << 16U);
tmp += (uint8_t) (InitStruct->TrgSel << 9U);
tmp += (uint8_t) (InitStruct->TrgFunc << 8U);
tmp += (uint8_t) (InitStruct->DMAFunc << 7U);
tmp += (uint8_t) (InitStruct->Wave);
DACx->DCTL = tmp;
}
/**
* @brief Set PMD Trigger Program Register of the specified ADC unit.
* @param ADx: Select ADC unit
* This parameter can be one of the following values:
* For M370: TSB_ADA, TSB_ADB
* For M372/3/4: TSB_ADB
* @param PMDTrg: The structure containing configuration for all of PMD Trigger Program Register
* Refer to the members of PMD_TrgTypeDef in .h file for more detail usage.
* @retval None
*/
void ADC_SetPMDTrg(TSB_AD_TypeDef * ADx, PMD_TrgTypeDef * PMDTrg)
{
uint32_t tmp = 0U;
uint32_t dat = 0U;
/* Check the parameters */
assert_param(IS_ADC_UNIT(ADx));
assert_param(IS_POINTER_NOT_NULL(PMDTrg));
assert_param(IS_PMD_PROGx(PMDTrg->ProgNum));
assert_param(IS_VE_PHASE(PMDTrg->Reg0_Phase));
assert_param(IS_VE_PHASE(PMDTrg->Reg1_Phase));
assert_param(IS_VE_PHASE(PMDTrg->Reg2_Phase));
assert_param(IS_VE_PHASE(PMDTrg->Reg3_Phase));
#if defined(__TMPM370_ADC_H)
if (ADx == TSB_ADA) {
assert_param(IS_UNIT_A_AINx(PMDTrg->Reg0_AINx));
assert_param(IS_UNIT_A_AINx(PMDTrg->Reg1_AINx));
assert_param(IS_UNIT_A_AINx(PMDTrg->Reg2_AINx));
assert_param(IS_UNIT_A_AINx(PMDTrg->Reg3_AINx));
dat = (uint32_t) PMDTrg->Reg0_AINx | ((uint32_t) PMDTrg->Reg0_Phase << 5U);
tmp |= dat;
dat = (uint32_t) PMDTrg->Reg1_AINx | ((uint32_t) PMDTrg->Reg1_Phase << 5U);
tmp |= dat << 8U;
dat = (uint32_t) PMDTrg->Reg2_AINx | ((uint32_t) PMDTrg->Reg2_Phase << 5U);
tmp |= dat << 16U;
dat = (uint32_t) PMDTrg->Reg3_AINx | ((uint32_t) PMDTrg->Reg3_Phase << 5U);
tmp |= dat << 24U;
*(ADA_PSETx_Address[PMDTrg->ProgNum]) = tmp;
} else {
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg0_AINx));
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg1_AINx));
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg2_AINx));
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg3_AINx));
dat = (uint32_t) PMDTrg->Reg0_AINx | ((uint32_t) PMDTrg->Reg0_Phase << 5U);
tmp |= dat;
dat = (uint32_t) PMDTrg->Reg1_AINx | ((uint32_t) PMDTrg->Reg1_Phase << 5U);
tmp |= dat << 8U;
dat = (uint32_t) PMDTrg->Reg2_AINx | ((uint32_t) PMDTrg->Reg2_Phase << 5U);
tmp |= dat << 16U;
dat = (uint32_t) PMDTrg->Reg3_AINx | ((uint32_t) PMDTrg->Reg3_Phase << 5U);
tmp |= dat << 24U;
*(ADB_PSETx_Address[PMDTrg->ProgNum]) = tmp;
}
#else
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg0_AINx));
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg1_AINx));
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg2_AINx));
assert_param(IS_UNIT_B_AINx(PMDTrg->Reg3_AINx));
dat = (uint32_t) PMDTrg->Reg0_AINx | ((uint32_t) PMDTrg->Reg0_Phase << 5U);
tmp |= dat;
dat = (uint32_t) PMDTrg->Reg1_AINx | ((uint32_t) PMDTrg->Reg1_Phase << 5U);
tmp |= dat << 8U;
dat = (uint32_t) PMDTrg->Reg2_AINx | ((uint32_t) PMDTrg->Reg2_Phase << 5U);
tmp |= dat << 16U;
dat = (uint32_t) PMDTrg->Reg3_AINx | ((uint32_t) PMDTrg->Reg3_Phase << 5U);
tmp |= dat << 24U;
*(ADB_PSETx_Address[PMDTrg->ProgNum]) = tmp;
#endif
}
