/* Set parity error interrupt status to clear */
void
ixParityENAccPbcPEParityErrorStatusClear (void)
{
/* Update the PCI Controller PCI Config SRCR register */
IXP400_PARITYENACC_REG_WRITE(ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE);
IXP400_PARITYENACC_REG_WRITE(ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata,
ixParityENAccPbcPEConfig.pbcParityErrorStatus.pciSrcrValue);
/* Clear off Parity Error Interrupt Status by writing '1' onto PPE bit */
IXP400_PARITYENACC_REG_BIT_SET(ixParityENAccPbcPEConfig.pbcPERegisters.pciIsr,
IXP400_PARITYENACC_PBC_ISR_PPE);
} /* end of ixParityENAccPbcPEParityErrorStatusClear() function */
IX_STATUS
ixParityENAccAqmPEDetectionConfigure
(IxParityENAccAqmPEConfigOption ixAqmPDCfg)
{
UINT32 aqmPDCfgFlags = IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ENABLE;
UINT32 aqmPDCfgStatus = 0;
UINT32 aqmTmpPDCfgStatus = 0;
/* Enable parity error detection */
if (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg)
{
IXP400_PARITYENACC_VAL_BIT_SET(aqmPDCfgStatus, aqmPDCfgFlags);
}
else /* Disable parity error detection */
{
IXP400_PARITYENACC_VAL_BIT_CLEAR(aqmPDCfgStatus, aqmPDCfgFlags);
} /* end of if */
/*
* The following sequence of steps works without the following while loop on Emulator
* but doesn't work on BMP
*/
while (TRUE != IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus))
{
/* Set the new configuration */
IXP400_PARITYENACC_REG_WRITE (
ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr, aqmPDCfgStatus);
/* Verify that the configuration is successful or not */
IXP400_PARITYENACC_REG_READ(
ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr,&aqmTmpPDCfgStatus);
}
if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus))
{
return (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg) ?
ixParityENAccIcInterruptEnable(
IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT) :
ixParityENAccIcInterruptDisable(
IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT);
}
else
{
return IX_FAIL;
} /* end of if */
} /* end of ixParityENAccAqmPEDetectionConfigure() function */
/* Get parity error status into internal datastructures */
void
ixParityENAccPbcPEParityErrorStatusGet (void)
{
register IxParityENAccPbcPERegisters *pbcPERegisters =
&ixParityENAccPbcPEConfig.pbcPERegisters;
register IxParityENAccPbcPEParityErrorStatus *pbcPEErrSts =
&ixParityENAccPbcPEConfig.pbcParityErrorStatus;
/* Read PCI Controller Interrupt Enable Register contents */
IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciInten, &pbcPEErrSts->pciIntenValue);
/* Read PCI Controller Interrupt Status Register contents */
IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciIsr, &pbcPEErrSts->pciIsrValue);
/* Read PCI Controller Control and Status Register contents */
IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciCsr, &pbcPEErrSts->pciCsrValue);
/* Read the PCI Controller PCI Config SRCR register */
IXP400_PARITYENACC_REG_WRITE(pbcPERegisters->pciCrpAdCbe,
IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
IXP400_PARITYENACC_REG_READ(pbcPERegisters->pciCrpRdata, &pbcPEErrSts->pciSrcrValue);
} /* end of ixParityENAccPbcPEParityErrorStatusGet() function */
IX_STATUS
ixParityENAccEbcPEDetectionConfigure(IxParityENAccEbcPEConfigOption ixEbcPDCfg)
{
UINT32 ebcPDCfgFlags = 0;
UINT32 ebcPDCfgStatus = 0;
UINT32 ebcTmpPDCfgStatus = 0;
register IxParityENAccEbcPERegisters *ebcPERegisters =
&ixParityENAccEbcPEConfig.ebcPERegisters;
int loopIdx = 100;
if (IXP400_PARITYENACC_PE_EBC_CS == ixEbcPDCfg.ebcCsExtSource)
{
if (ixEbcPDCfg.ebcCsId >= IXP400_PARITYENACC_PE_EBC_CHIPSEL_MAX)
{
return IX_FAIL;
} /* end of if */
/* Get current parity detection configuration of Chip Select */
IXP400_PARITYENACC_REG_READ(
ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId], &ebcPDCfgStatus);
/* Enable parity error detection */
ebcPDCfgFlags = IXP400_PARITYENACC_EBC_TIMING_CSX_PAR_EN;
if (IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcCsEnabled)
{
IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus, ebcPDCfgFlags);
}
else /* Disable parity error detection */
{
IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus, ebcPDCfgFlags);
} /* end of if */
while (loopIdx-- && (ebcTmpPDCfgStatus != ebcPDCfgStatus))
{
/* Set the new configuration */
IXP400_PARITYENACC_REG_WRITE(
ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId], ebcPDCfgStatus);
/* Configuration successful? */
IXP400_PARITYENACC_REG_READ(
ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId],&ebcTmpPDCfgStatus);
}
if (ebcTmpPDCfgStatus != ebcPDCfgStatus)
{
return IX_FAIL;
} /* end of if */
/*
* This step required for Even/Odd Parity Type detection from the
* EBC Master Control Register if the chip select configuration is
* specified along with the parity type which is part of the Master
* Control Register only
*/
/* Get current parity detection configuration of External Master */
IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl,&ebcPDCfgStatus);
} /* else of if */
else /* EBC Master Control */
{
ebcPDCfgFlags = IXP400_PARITYENACC_EBC_MST_CONTROL_INPAR_EN;
/* Get current parity detection configuration */
IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl, &ebcPDCfgStatus);
/* Enable parity error detection */
if (IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcExtMstEnabled)
{
IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus,ebcPDCfgFlags);
}
else /* Disable parity error detection */
{
IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus,ebcPDCfgFlags);
} /* end of if */
} /* end of if */
/* Set Even/Odd parity type */
ebcPDCfgFlags = IXP400_PARITYENACC_EBC_MST_CONTROL_ODDPARITY;
if (IXP400_PARITYENACC_PE_ODD_PARITY == ixEbcPDCfg.parityOddEven)
{
IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus,ebcPDCfgFlags);
}
else /* Set even parity */
{
IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus,ebcPDCfgFlags);
} /* end of if */
loopIdx = 10;
while (loopIdx-- && (ebcTmpPDCfgStatus != ebcPDCfgStatus))
{
/* Set the new configuration */
IXP400_PARITYENACC_REG_WRITE(ebcPERegisters->expMstControl, ebcPDCfgStatus);
/* Configuration successful? */
IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl,&ebcTmpPDCfgStatus);
}
if (ebcTmpPDCfgStatus == ebcPDCfgStatus)
{
/* Enable/Disable the corresponding interrupt at Interrupt Controller */
return ((IXP400_PARITYENACC_PE_ENABLE ==
ixEbcPDCfg.ebcInOrOutbound.ebcCsEnabled) ||
(IXP400_PARITYENACC_PE_ENABLE ==
ixEbcPDCfg.ebcInOrOutbound.ebcExtMstEnabled)) ?
ixParityENAccIcInterruptEnable(
IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT) :
ixParityENAccIcInterruptDisable(
IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT);
}
else
{
IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
"ixParityENAccEbcPEDetectionConfigure(): returned IX_FAIL\n",
0,0,0,0,0,0);
return IX_FAIL;
} /* end of if */
} /* end of ixParityENAccEbcPEDetectionConfigure() function */
IX_STATUS
ixParityENAccMcuPEParityInterruptClear (
IxParityENAccMcuPEParityErrorSource ixMcuParityErrSrc,
IxParityENAccPEParityErrorAddress ixMcuParityErrAddress)
{
BOOL mcuParityError0 = FALSE;
BOOL mcuParityError1 = FALSE;
BOOL mcuParityErrorN = FALSE;
UINT32 mcuParitySource0 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;
UINT32 mcuParitySource1 = IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL;
register IxParityENAccMcuPERegisters *mcuPERegisters =
&ixParityENAccMcuPEConfig.mcuPERegisters;
IxParityENAccPEParityErrorAddress mcuParityErrorAddr =
IXP400_PARITYENACC_VAL_READ(ixParityENAccMcuPEConfig.\
mcuParityErrorStatus.mcuEcar0Value, IXP400_PARITYENACC_MCU_ERR_ADDRESS_MASK);
/* Identify the Multi & Single bit parity errors */
ixParityENAccMcuPEParityErrorStatusInterpret (
&mcuParityError0, &mcuParityError1, &mcuParityErrorN,
&mcuParitySource0, &mcuParitySource1);
switch (ixMcuParityErrSrc)
{
case IXP400_PARITYENACC_PE_MCU_SBIT:
{
/* Parity error number #0 is of single bit type */
if ((TRUE == mcuParityError0) &&
(IXP400_PARITYENACC_MCU_ERR_SMBIT_SGL == mcuParitySource0) &&
(mcuParityErrorAddr == ixMcuParityErrAddress))
{
/* Write '1' to clear the single bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR0_MASK);
break;
} /* end of if */
/* Parity error number #1 is of single bit type */
/* Write '1' to clear the single bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR1_MASK);
break;
} /* end of case IXP400_PARITYENACC_PE_MCU_SBIT */
case IXP400_PARITYENACC_PE_MCU_MBIT:
{
/* Parity error number #0 is of multi bit type */
if ((TRUE == mcuParityError0) &&
(IXP400_PARITYENACC_MCU_ERR_SMBIT_MLT == mcuParitySource0) &&
(mcuParityErrorAddr == ixMcuParityErrAddress))
{
/* Write '1' to clear the multi bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR0_MASK);
break;
} /* end of if */
/* Parity error number #1 is of multi bit type */
/* Write '1' to clear the multi bit parity interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERROR1_MASK);
break;
} /* end of case IXP400_PARITYENACC_PE_MCU_MBIT */
case IXP400_PARITYENACC_PE_MCU_OVERFLOW:
{
/* Write '1' to clear the Parity Overflow Interrupt */
IXP400_PARITYENACC_REG_WRITE(mcuPERegisters->mcuMcisr,
IXP400_PARITYENACC_MCU_ERRORN_MASK);
break;
} /* end of case IXP400_PARITYENACC_PE_MCU_OVERFLOW */
default:
{
/* This part of the code should never be reached */
IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
"ixParityENAccMcuPEParityInterruptClear(): "
"Invalid MCU interrupt source to clear\n", 0,0,0,0,0,0);
return IX_FAIL;
} /* end of case default */
} /* end of switch */
return IX_SUCCESS;
} /* end of ixParityENAccMcuPEParityInterruptClear() function */
IX_STATUS
ixParityENAccMcuPEDetectionConfigure (IxParityENAccMcuPEConfigOption ixMcuPDCfg)
{
UINT32 mcuPDCfgFlags = IXP400_PARITYENACC_MCU_ECC_EN_MASK; /* Always to be included */
UINT32 mcuPDCfgStatus = 0;
UINT32 mcuTmpPDCfgStatus = 0;
/*
* Enable parity error detection for given options
*
* - ECC enable
* - Single-bit ECC error report
* - Multi-bit ECC error report
* - Single-bit parity correction using ECC
*/
/* Enable Single-bit parity error detection */
if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.singlebitDetectEnabled)
{
mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_SBIT_REPORT_MASK;
} /* end of if */
/* Enable Single-bit parity error correction */
if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.singlebitCorrectionEnabled)
{
mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_SBIT_CORRECT_MASK;
} /* end of if */
/* Enable Multi-bit parity error detection */
if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.multibitDetectionEnabled)
{
mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_MBIT_REPORT_MASK;
} /* end of if */
/* Check the current ECC feature configuration */
IXP400_PARITYENACC_REG_READ(ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr,
&mcuPDCfgStatus);
/* Existing configuration is same as requested one */
if (mcuPDCfgStatus == mcuPDCfgFlags)
{
return IX_SUCCESS;
}
mcuPDCfgStatus = mcuPDCfgFlags;
IXP400_PARITYENACC_REG_WRITE((ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr),
mcuPDCfgStatus);
/* Verify that configuration has been successful or not */
IXP400_PARITYENACC_REG_READ((ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr),
&mcuTmpPDCfgStatus);
if (mcuTmpPDCfgStatus == mcuPDCfgStatus)
{
/* Enable/Disable the corresponding interrupt at Interrupt Controller */
IXP400_PARITYENACC_VAL_BIT_CLEAR(mcuPDCfgFlags,IXP400_PARITYENACC_MCU_ECC_EN_MASK);
return (0 != mcuPDCfgFlags) ?
ixParityENAccIcInterruptEnable(
IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT) :
ixParityENAccIcInterruptDisable(
IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT);
}
else
{
return IX_FAIL;
} /* end of if */
} /* end of ixParityENAccMcuPEDetectionConfigure() function */
IX_STATUS
ixParityENAccPbcPEDetectionConfigure(IxParityENAccPbcPEConfigOption ixPbcPDCfg)
{
UINT32 pbcPDCfgStatus = 0;
UINT32 pbcTmpPDCfgStatus = 0;
int loopIdx = 0;
/* Read the PCI Controller PCI Config SRCR register */
IXP400_PARITYENACC_REG_WRITE(
ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
IXP400_PARITYENACC_REG_READ(
ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata,
&pbcPDCfgStatus);
/*
* Set/Clear the PER bit of SRCR register &
* Enable/Disable Parity Error Notification
*/
if (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg)
{
/* Set the PER bit of SRCR register */
IXP400_PARITYENACC_VAL_BIT_SET(pbcPDCfgStatus,
IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER);
/* Enable the PCI Parity Error Interrupt Notification */
IXP400_PARITYENACC_REG_BIT_SET(
ixParityENAccPbcPEConfig.pbcPERegisters.pciInten,
IXP400_PARITYENACC_PBC_INTEN_PPE);
}
/* else of if */
else
{
/* Clear the PER bit of SRCR register */
IXP400_PARITYENACC_VAL_BIT_CLEAR(pbcPDCfgStatus,
IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER);
/* Disable the PCI Parity Error Interrupt Notification */
IXP400_PARITYENACC_REG_BIT_CLEAR(
ixParityENAccPbcPEConfig.pbcPERegisters.pciInten,
IXP400_PARITYENACC_PBC_INTEN_PPE);
} /* end of if */
/* Write back the PCI Controller PCI Config SRCR register */
IXP400_PARITYENACC_REG_WRITE(
ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE);
IXP400_PARITYENACC_REG_WRITE(
ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata,
pbcPDCfgStatus);
loopIdx = 10;
while (loopIdx--)
{
/* Verify that the configuration is successful or not */
IXP400_PARITYENACC_REG_WRITE(
ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
IXP400_PARITYENACC_REG_READ(
ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata,
&pbcTmpPDCfgStatus);
}
if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(pbcPDCfgStatus, pbcTmpPDCfgStatus))
{
/* Enable/Disable the corresponding interrupt at Interrupt Controller */
return (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) ?
ixParityENAccIcInterruptEnable(
IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT) :
ixParityENAccIcInterruptDisable(
IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT);
}
else
{
return IX_FAIL;
} /* end of if */
} /* end of ixParityENAccPbcPEDetectionConfigure() function */
