/******************************************************************************* ** Function definitions ** *******************************************************************************/ IFX_INLINE IfxCpu_Trap IfxCpu_Trap_extractTrapInfo(uint8 trapClass, uint32 tin) { IfxCpu_Trap trapInfo; trapInfo.tAddr = (unsigned int)__getA11(); trapInfo.tClass = trapClass; trapInfo.tId = tin; trapInfo.tCpu = IfxCpu_getCoreId(); return trapInfo; }
IfxCpu_CoreMode IfxCpu_getCoreMode(Ifx_CPU *cpu) { IfxCpu_CoreMode cpuMode; Ifx_CPU_DBGSR dbgsr; IfxCpu_ResourceCpu index = IfxCpu_getIndex(cpu); cpuMode = IfxCpu_CoreMode_unknown; /*get the DBGSR.HALT status */ /*Check if the request is done for same cpu as the host for this call */ if (IfxCpu_getCoreId() != index) { /*status request is for other cpu than the host */ dbgsr = cpu->DBGSR; } else { /*status request is for same cpu as the host */ dbgsr.U = __mfcr(CPU_DBGSR); } /*Check if the requested CPU is in DBG HALT mode */ if (dbgsr.B.HALT == (uint32)IfxCpu_DBGST_HALT_halt) { /*CPU is in DBG HALT mode */ cpuMode = IfxCpu_CoreMode_halt; } else { if (dbgsr.B.HALT == (uint32)IfxCpu_DBGST_HALT_run) { /*CPU is in DBG RUNNING mode now check PMCSR status */ Ifx_SCU_PMCSR *pmcsr_val; pmcsr_val = (Ifx_SCU_PMCSR *)&MODULE_SCU.PMCSR[index]; if (pmcsr_val->B.PMST == (uint32)IfxCpu_PMCSR_PMST_normalMode) { /*Cpu is in normal run mode */ cpuMode = IfxCpu_CoreMode_run; } else { /*Cpu is not in run mode */ if (pmcsr_val->B.PMST == (uint32)IfxCpu_PMCSR_PMST_idleMode) { /*Cpu is in idle mode */ cpuMode = IfxCpu_CoreMode_idle; } } } else { cpuMode = IfxCpu_CoreMode_unknown; } } return cpuMode; }
boolean IfxCpu_setProgramCounter(Ifx_CPU *cpu, uint32 programCounter) { boolean retVal = TRUE; if (cpu == IfxCpu_getAddress(IfxCpu_getCoreId())) { retVal = FALSE; } else { cpu->PC.B.PC = programCounter >> 1; } return retVal; }
boolean IfxCpu_setCoreMode(Ifx_CPU *cpu, IfxCpu_CoreMode mode) { // this switch is only temporary required // once the IfxCan driver is generated via lldgen, we will vary the code without #ifdef #ifdef IFX_TC27x /* FIXME Copied from old TC27xA code, check that this is up to date code */ IfxCpu_CoreMode cpuMode; boolean RetVal; IfxScu_PMCSR_REQSLP modeSet; RetVal = TRUE; modeSet = IfxScu_PMCSR_REQSLP_Idle; /* Check the mode the CPU is in */ cpuMode = IfxCpu_getCoreMode(cpu); /* if requested mode is same as current mode nothing to do */ if (cpuMode != mode) { /* transition from halt to Run */ if (IfxCpu_CoreMode_halt == cpuMode) { if (IfxCpu_CoreMode_run == mode) { Ifx_CPU_DBGSR dbgsr; if (IfxCpu_getCoreId() != IfxCpu_getIndex(cpu)) { cpu->DBGSR.B.HALT = 0x2; } else { dbgsr.U = __mfcr(CPU_DBGSR); dbgsr.B.HALT = 0x2; __mtcr(CPU_DBGSR, dbgsr.U); } } else /* cannot go to any other mode e.g. IfxCpu_CoreMode_idle */ { RetVal = FALSE; } } /* From Run to Idle or vice versa */ else { if (IfxCpu_CoreMode_run == cpuMode) { if (IfxCpu_CoreMode_idle == mode) { modeSet = IfxScu_PMCSR_REQSLP_Idle; } else { RetVal = FALSE; } } /* idle to Run */ else if (IfxCpu_CoreMode_idle == cpuMode) { if (IfxCpu_CoreMode_run == mode) { modeSet = IfxScu_PMCSR_REQSLP_Run; } else { RetVal = FALSE; } } else { RetVal = FALSE; } if (TRUE == RetVal) { /* To take care of the Work Around in A step * In A Step the PMCSR is Cpu Endinit protected * in B step it is by safety endinit*/ uint16 password; uint32 wdtCon0_Val; Ifx_SCU_WDTCPU *watchdog; watchdog = &MODULE_SCU.WDTCPU[IfxCpu_getCoreId()]; /* FIXME access to the watchdog of an other CPU, this might not work! */ password = IfxScuWdt_getCpuWatchdogPassword(); IfxScuWdt_clearCpuEndinit(password); /* password access */ watchdog->CON0.U = (password << 2U) | 0x1U; /* modify access, E=0 */ watchdog->CON0.U = (password << 2U) | 0x2U; /* password access in advance */ watchdog->CON0.U = (password << 2U) | 0x1U; /* prepare write value */ wdtCon0_Val = ((0x0000U) << 16U) | (password << 2U) | (0x3U); MODULE_SCU.PMCSR[(uint32)IfxCpu_getIndex(cpu)].B.REQSLP = modeSet; /* modify access, E=1, reload WDT */ watchdog->CON0.U = wdtCon0_Val; IfxScuWdt_setCpuEndinit(password); } } } return RetVal; #else uint8 reqslp; boolean retValue; IfxCpu_ResourceCpu index = IfxCpu_getIndex(cpu); /*Modes such as HALT, SLEEP and STBY are not handled at CPU level */ retValue = ((mode == IfxCpu_CoreMode_halt) || (mode == IfxCpu_CoreMode_sleep) || (mode == IfxCpu_CoreMode_stby)) ? FALSE : TRUE; reqslp = (mode == IfxCpu_CoreMode_idle) ? IfxScu_PMCSR_REQSLP_Idle : IfxScu_PMCSR_REQSLP_Run; if (retValue == TRUE) { /*Check if the same core is requesting to change the core run mode */ if (IfxCpu_getCoreId() != index) { /*Request is for the other core */ /*To access PMCSR of other CPUs handle the safety EndInit protection */ uint16 safetyWdtPw = IfxScuWdt_getSafetyWatchdogPassword(); IfxScuWdt_clearSafetyEndinit(safetyWdtPw); MODULE_SCU.PMCSR[(uint32)IfxCpu_getIndex(cpu)].B.REQSLP = reqslp; IfxScuWdt_setSafetyEndinit(safetyWdtPw); cpu->DBGSR.B.HALT = 2; /*reset the HALT bit, if it is already done it is no harm in writing again */ } else { /*Request is for self, this request normally only for halt, otherwise the core is already running anyway! */ /*To access PMCSR of self handle the cpu EndInit protection */ uint16 cpuWdtPw = IfxScuWdt_getCpuWatchdogPassword(); IfxScuWdt_clearCpuEndinit(cpuWdtPw); MODULE_SCU.PMCSR[(uint32)index].B.REQSLP = reqslp; IfxScuWdt_setCpuEndinit(cpuWdtPw); } } return retValue; #endif }
int core0_main(void) { udp_pcb_t * udp; ip_addr_t addr; pbuf_t *p = (void*)0;//(pbuf_t *)pbuf_alloc_special(MEMP_PBUF); uint16 idx; uint16 total; /* * !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!! * Enable the watchdog in the demo if it is required and also service the watchdog periodically * */ IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword()); /* Initialise the application state */ g_AppCpu0.info.pllFreq = IfxScuCcu_getPllFrequency(); g_AppCpu0.info.cpuFreq = IfxScuCcu_getCpuFrequency(IfxCpu_getCoreId()); g_AppCpu0.info.sysFreq = IfxScuCcu_getSpbFrequency(); g_AppCpu0.info.stmFreq = IfxStm_getFrequency(&MODULE_STM0); report.position = 0; IfxPort_Io_initModule(&conf); for (idx = 0; idx < conf.size; idx++) { IfxPort_Io_ConfigPin *tbl = &conf.pinTable[idx]; IfxPort_setPinHigh(tbl->pin->port, tbl->pin->pinIndex); // P33.0 = 0 } initStm0(); /* Enable the global interrupts of this CPU */ IfxCpu_enableInterrupts(); /* Demo init */ wMultican_init(); Ifx_Lwip_Config config; IP4_ADDR(&config.ipAddr, 192, 168, 7, 123); IP4_ADDR(&config.netMask, 255, 255, 255, 0); IP4_ADDR(&config.gateway, 192, 168, 7, 6); MAC_ADDR(&config.ethAddr, 0x00, 0x20, 0x30, 0x40, 0x50, 0x60); Ifx_Lwip_init(&config); addr.addr8[3] = 6; addr.addr8[2] = 7; addr.addr8[1] = 168; addr.addr8[0] = 192; /* background endless loop */ IfxPort_setPinHigh(&MODULE_P33, 6); // P33.0 = 0 total = Ifx_g_Eth.config.phyLink(); if (total == 1) { report.phy_link = 1; } else { report.phy_link = 0; } ethRam = NULL_PTR; udp = udp_new(); while (TRUE) { Ifx_Lwip_pollTimerFlags(); Ifx_Lwip_pollReceiveFlags(); if (total != Ifx_g_Eth.config.phyLink()) { total = Ifx_g_Eth.config.phyLink(); if (total == 1) { IfxPort_setPinLow(&MODULE_P33, 6); netif_set_up(&Ifx_g_Lwip.netif); IfxEth_startTransmitter(Ifx_g_Lwip.netif.state); } else { netif_set_down(&Ifx_g_Lwip.netif); IfxPort_setPinHigh(&MODULE_P33, 6); } } report.phy_link = total; report.mdio_stat = IfxEth_Phy_Pef7071_MIIState(); report.ethRam = ethRam!=NULL?1:0; wMultiCanNode0Demo_run(report, 0); if ((stat & 0x0003) != 0x01) { IfxPort_setPinLow(&MODULE_P33, 7); } else { IfxPort_setPinHigh(&MODULE_P33, 7); } if (Ifx_g_Eth.config.phyLink() && (ethRam = IfxEth_getTransmitBuffer(&Ifx_g_Eth))) { p = (pbuf_t *)memp_malloc(MEMP_PBUF); if (p != NULL) { p->payload = LWIP_MEM_ALIGN((void *)((u8_t *)ethRam)); p->len = 100; p->tot_len = p->len; p->next = NULL; p->ref = 1; p->type = PBUF_REF; udp_sendto_if(udp, p, &addr, 5001, &Ifx_g_Lwip.netif); pbuf_free(p); IfxPort_setPinLow(&MODULE_P33, 8); // P33.0 = 0 } } else { IfxPort_setPinHigh(&MODULE_P33, 8); // P33.0 = 0 } REGRESSION_RUN_STOP_PASS; } udp_remove(udp); return 0; }