void InitProx(void)
{
InitAd(); // init AD converter module
InitTMR1(); // init timer 1 for ir processing
}
int main(void)
{
DDRA=0;
PORTA=0;
DDRB=0xbc;
PORTB |= 0xff;
DDRC=0x1c;
// PORTC |=0xff;
DDRD=0xba;
PORTD=0xff;
//INIT TWI;
TWBR=0x7f;//F TWI
CtStart=65000;
while(CtStart--) _WDR();
//Init capture1
TCCR1B=0x82;//0.5mkc,falling edge
TIMSK=TIMSK | 0x4;//enable Int overlowT1
// INIT SPI
SPCR=0x72;//f/64
SPSR=0;//f/64
InitAd();
MCUCR=0;
TCCR0=5;// /1024
ASSR=0;
TCCR2=2;// T=0,5 mkc
ASSR=0;
NumberLink=1;
CtUsart=NumberBlok;
ResetError();
URef=ReadEepromWord(8);
if(URef>275)
URef=256;
if(URef<230)
URef=256;
_SEI();
while(1)
{
_WDR();
ChangeRegimTest();
ControlOut();
CalcTM();
LoadIndicator();
SetRegimErrorLuk();
SetErrorLuk();
if(RomReceiveRS[5][3] & 4)
ResetError();
else if(RomReceiveRS[5][6] & 4)
ResetError();
else
{
RegTransmit[3][1] &=0xdf;
RegTransmit[3][2] &=0xfe;
}
SetError();
if(RomReceiveRS[6][3] & 0x80)
{
RegTransmit[1][2]=0;
RegTransmit[2][2] &=0xfe;
}
else
ControlLuk();
if(!CtErrorLink[0])
{
//INIT TWI;
TWBR=0;//F TWI
TWAR=0;
TWCR =0;
TWSR=0xf8;
TWBR=0x7f;//F TWI
CtStart=65000;
while(CtStart--) _WDR();
CtErrorLink[0]=CtErrorLink0;
CtErrorLink[1]=CtErrorLink0;
CtErrorLink[2]=CtErrorLink0;
}
if(!CtErrorLink[1])
{
//INIT TWI;
TWBR=0;//F TWI
TWAR=0;
TWCR =0;
TWSR=0xf8;
TWBR=0x7f;//F TWI
CtStart=65000;
while(CtStart--) _WDR();
CtErrorLink[0]=CtErrorLink0;
CtErrorLink[1]=CtErrorLink0;
CtErrorLink[2]=CtErrorLink0;
}
if(!CtErrorLink[2])
{
//INIT TWI;
TWBR=0;//F TWI
TWAR=0;
TWCR =0;
TWSR=0xf8;
TWBR=0x7f;//F TWI
CtStart=65000;
while(CtStart--) _WDR();
CtErrorLink[0]=CtErrorLink0;
CtErrorLink[1]=CtErrorLink0;
CtErrorLink[2]=CtErrorLink0;
}
ReadKn();
if(NumberLink)
--NumberLink;
else
NumberLink=2;
LoadRegTransmit();
ReceiveTransmitMaster();
}
}
int main(void)
{
unsigned int R0;
unsigned int R2;
DDRA=0;
PORTA=0;
DDRB=0xa0;
PORTB |= 0xff;
DDRC=0xfc;
PORTC |=0xff;
DDRD=0x2a;
PORTD=0xf7;
//INIT TWI;
TWBR=0x7f;//F TWI
CtStart=65000;
while(CtStart--) _WDR();
//Init capture1
TCCR1B=0x82;//0.5mkc,falling edge
TIMSK=TIMSK | 0x4;//enable Int overlowT1
// TIMSK=TIMSK | 0x20;//enable Int capture1 prov
//INIT USART
InitUsart();
// INIT SPI
SPCR=0x70;//f/64
SPSR=0;//f/64
InitIndStart();
InitAd();
TCCR1B=0xc2;//0.5mkc
TIMSK=TIMSK | 0x4;//enable Int overlowT1
ResetAvaria();
LoadFromEeprom();
RomReceive[3]=1;
RomReceive[4]=0;
RomReceive[6]=0;
RegSPCH2=0;
RegSPCH2Old=0;
CtKn=5;
RegimWork=0;
U50=0;
I50=200;
UKvadro=0;
U400Out=0;
IA=0;
IB=0;
IC=0;
CtUsart=NumberBlok;
RegTransmitRS[1]=0;
CtLuk=200;
_SEI();
CtBegin=50;
RomReceiveRS[3][1]=0;//denablePusk
RomReceiveRS[3][4]=0;//denablePusk
RegTransmitRS[3]=0;
RegTransmitRS[1]=0;
ClearErrorFar();
CtIMax=80;
CtUError=160;
AvariaI=0;
RegStop=0;
while(1)
{
_WDR();
if(CtBegin)
{
if(RomReceive[3] & 2)
NumberBlok=4;
else
NumberBlok=1;
}
// UMin=220;
// UMax=600;
if(RegimWork>=6)
{
if((UKvadro>=UMin) && (UKvadro<=UMax))
CtUError=160;
}
else
CtUError=80;
if(RomReceiveRS[5][3] & 4)
{
ResetAvaria();
ClearErrorFar();
}
if((RomReceiveRS[5][6] & 4)||(RomReceive[4] & 0x80))
{
ResetAvaria();
ClearErrorFar();
}
if((Avaria)||(AvariaI))
RegTransmitRS[1] |=1;
else
RegTransmitRS[1] &=0xfe;
if(!(RegS & 0x60))
RegTransmitRS[1] |=2;
else
RegTransmitRS[1] &=0xfd;
if(RegS & 0x10)
RegTransmitRS[1] |=4;
else
RegTransmitRS[1] &=0xfb;
if((RegimWork)&&(!CtLuk))
RegTransmitRS[1] |=8;//Open Luk
else
RegTransmitRS[1] &=0xf7;//Close Luk
if((RomReceive[5] & 1)&&(RegS & 0x10))
RegTransmitRS[1] |=0x10;
else
RegTransmitRS[1] &=0xef;
if(RegS & 0x10)//nagr=on
RegTransmitRS[1] |=0x20;
else
RegTransmitRS[1] &=0xdf;
RegTransmitRS[2]=RomReceiveRS[3][0];//Avaria;//RegS;//RegimError;//NumberBlok;//45;//U50;
RegTransmitRS[4]=U400In>>2;//RomReceive[2];//UNom
RegTransmitRS[5]=Avaria;//46;//AdResult[1];
RegTransmitRS[6]=TestTimeAd;//16;
RegSPCH2=RomReceive[3]<<8;
RegSPCH2 |=RomReceive[4];
AccountU50();
AccountI50();
CalcI50();
AccountUKvadro();
AccountU400Out();
AccountIA();
AccountIB();
AccountIC();
AccountIMax();
if(IMax<IMaxDop)
CtIMax=80;
ControlRegimError();
if(RomReceive[3] & 1)
{
ControlRegimWork();
ControlK();
}
else
{
ControlRegimWorkDU();
ControlKDU();
}
SetAvaria();
if(!CtErrorLink)
{
//INIT TWI;
TWBR=0;//F TWI
TWAR=0;
TWCR =0;
TWSR=0xf8;
TWBR=0x7f;//F TWI
CtErrorLink=CtErrorLink0;
}
if(CtLinkTWI)
--CtLinkTWI;
else
{
CtLinkTWI=30;
_WDR();
LoadRegTransmit();//++RegTransmit
ReceiveTransmitMaster();
}
ReadKn();
DecSegm(U400In);
SetCursor(0,0);
IndPar();
R0=400;
while(R0--) _WDR();
SPDR=0x20;
R2=900;
while(R2--) _WDR();
DecSegm(UKvadro);
SetCursor(40,0);
IndPar();
R0=400;
while(R0--) _WDR();
SPDR=0x20;
R2=900;
while(R2--) _WDR();
DecSegm(IMax);
SetCursor(80,0);
IndPar();
R0=400;
while(R0--) _WDR();
SPDR=0x20;
R2=900;
while(R2--) _WDR();
DecSegm(RegSPCH2);
SetCursor(0,1);
IndPar();
R0=400;
while(R0--) _WDR();
SPDR=0x20;
R2=900;
while(R2--) _WDR();
DecSegm(RegStop);
SetCursor(40,1);
IndPar();
R0=400;
while(R0--) _WDR();
SPDR=0x20;
R2=900;
while(R2--) _WDR();
DecSegm(Avaria);
SetCursor(80,1);
IndPar();
R0=400;
while(R0--) _WDR();
SPDR=0x20;
R2=900;
while(R2--) _WDR();
Reg0=600;
while(Reg0)
--Reg0;
}
}
int main(void)
{
DDRA=0;
PORTA=0;
DDRB=0xb2;
PORTB |= 0xf3;// Control UAB
DDRC=0x2a;
PORTC |=0x2a;
DDRD=0xc7;
PORTD=0xff;/*Reset=on*/
// INIT SPI
SPSR=0;//f/64
SPCR=0x72;
SPCR |=0x80;//enable Int SPI
InitAd();
TCCR1A=0;//0x82;
TCCR1B=0x2;//0.5mks
// TIMSK=TIMSK | 0x20;//enable Int capture1
TIMSK=TIMSK | 0x4;//enable Int overlowT1
/*Interrupt1*/
// MCUCR=0x8;// Log1>0 Int1
// GICR |=(1<<INT1);/*Enable INT1*/
/*Timer0*/
TCCR0=0x61;//0x61;//1;//1;
OCR0=0xe0;
// TIMSK |=1;/*Enable Int Overlow Timer0*/
/*Timer2*/
TCCR2=0x4;
TIMSK |=(1<<TOIE2);/*Enable Int Overlow Timer2*/
CtSetka=0;
_SEI();
RegimWork=0;
ResetError();
CtStart=50;
RevunOff=0;
// ClearRomReceive();
/*Work program*/
while(1)
{
_WDR();
if(!CtIndAd)
{
// IndicatorAd(2);
CtIndAd=30;
}
ReadKn();
if(RegS & 0x10)
ResetError();
ChangeRegim();
ControlRevun();
ControlMPP();
ControlPogar();
ControlNorma();
Indicator();
IndicatorAll();
SetRegimError();
SetError();
// DecSegm(RegS);
// IndicatorSegment();
if(Error)
PORTD |=0x40;//Error
else
PORTD &=0xbf;//Norma
}
}
