void main(void)
{
InitSysCtrl();
InitXintf();
InitXintf16Gpio();
ADInit();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &ISRTimer0;
EDIS; // This is needed to disable write to EALLOW protected registers
InitCpuTimers(); // For this example, only initialize the Cpu Timers
ConfigCpuTimer(&CpuTimer0, 100, 987); //在定时器内进行采样,采样率1.5KHz
IER |= M_INT1;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
EINT;
ERTM;
/*EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // GPIO0 = GPIO0
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
EDIS;
GpioDataRegs.GPADAT.bit.GPIO0 = 0;*/
SET_ADRST;
DELAY_US(100000);
CLEAR_ADRST;
StartCpuTimer0();
while(1);
}
//---------------------------------------------------------------------------
// InitGpio:
//---------------------------------------------------------------------------
// This function initializes the Gpio to a known (default) state.
//
// For more details on configuring GPIO's as peripheral functions,
// refer to the individual peripheral examples and/or GPIO setup example.
void InitGpio(void)
{
// Step 1: Init the Gpio use for 16 bit mode XINTF
EALLOW;
InitXintf16Gpio();
EDIS;
}
void InitXintf32Gpio()
{
// To configure the GPIOs for XINTF, set the GPIO MUX setting equal to:
// - 2 for C2834x/C2824x devices
// Always refer to the device data manual and XINTF User's Guide for
// correct GPIO MUX settings
EALLOW;
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 2; // XD31
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 2; // XD30
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 2; // XD29
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 2; // XD28
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 2; // XD27
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 2; // XD26
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 2; // XD25
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 2; // XD24
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 2; // XD23
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 2; // XD22
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 2; // XD21
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 2; // XD20
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 2; // XD19
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 2; // XD18
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 2; // XD17
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 2; // XD16
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 2; // XD31 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 2; // XD30 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 2; // XD29 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 2; // XD28 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 2; // XD27 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 2; // XD26 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 2; // XD25 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 2; // XD24 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 2; // XD23 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 2; // XD22 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 2; // XD21 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 2; // XD20 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 2; // XD19 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 2; // XD18 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 2; // XD17 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 2; // XD16 asynchronous input
InitXintf16Gpio();
}
void InitXintf32Gpio()
{
EALLOW;
// Configure the GPIO for the use for high-16 XINTF Data Bus
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
// Configure the GPIO for the use for low 16 bit XINTF: data bus, addr bus, contrl signals etc.
InitXintf16Gpio();
EDIS;
}
void InitXintf32Gpio()
{
EALLOW;
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
InitXintf16Gpio();
}
void InitXintf(void)
{
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
// For an example of an XINTF configuration used with the
// F28335 eZdsp, refer to the examples/run_from_xintf project.
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 1;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
InitXintf16Gpio();
// InitXintf32Gpio();
asm(" RPT #7 || NOP");
}
