void UCS_FLL_settle(u16 fsystem, u16 ratio) {
volatile u16 x = ratio * 32;
Init_FLL(fsystem, ratio);
while(x--) {
__delay_cycles(30);
}
}
//----------------------------------------------------------------------------
VOID Init_Clock(VOID)
{
#if defined (__MSP430F563x_F663x)
while(BAKCTL & LOCKIO) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKIO); // enable XT1 pins
// Workaround for USB7
UCSCTL6 &= ~XT1OFF;
#endif
if (USB_PLL_XT == 2)
{
#if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x0C; // enable XT2 pins for F5529
#elif defined (__MSP430F563x_F663x)
P7SEL |= 0x0C;
#endif
// Use the REFO oscillator to source the FLL and ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
// MCLK will be driven by the FLL (not by XT2), referenced to the REFO
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // Start the FLL, at the freq indicated by the config constant USB_MCLK_FREQ
//XT2_Start(XT2DRIVE_3); // Start the "USB crystal"
}
else
{
#if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x10; // enable XT1 pins
#endif
// Use the REFO oscillator to source the FLL and ACLK
// UCSCTL3 = SELREF__REFOCLK;
// UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
P5SEL |= 0x30; // enable XT1 pins for F5509
LFXT_Start(XT1DRIVE_3);
// Use the LFXT1 oscillator to source the FLL and ACLK
UCSCTL3 = SELA__XT1CLK;
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__XT1CLK);
// MCLK will be driven by the FLL (not by XT2), referenced to the REFO
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK)
//XT1_Start(XT1DRIVE_3); // Start the "USB crystal"
}
}
void Init_FLL_Settle(uint16_t fsystem, uint16_t ratio)
{
volatile uint16_t x = ratio * 32;
Init_FLL(fsystem, ratio);
while (x--) {
__delay_cycles(30);
}
}
void Init_FLL_Settle(unsigned int fsystem, unsigned int ratio)
{
volatile unsigned int x = ratio * 32;
Init_FLL(fsystem, ratio);
while (x--) {
__delay_cycles(30);
}
}
// Initializes the clocks. Starts the DCO at USB_MCLK_FREQ (the CPU freq set with the Desc
// Tool), using the REFO as the FLL reference. Configures the high-freq crystal, but
// doesn't start it yet. Takes some special actions for F563x/663x.
VOID Init_Clock(VOID)
{
#if defined (__MSP430F563x_F663x)
while(BAKCTL & LOCKIO) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKIO); // Enable XT1 pins
// Workaround for USB7 chip errata
UCSCTL6 &= ~XT1OFF;
#endif
if (USB_PLL_XT == 2)
{
// Enable XT2 pins
#if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x0C;
#elif defined (__MSP430F563x_F663x)
P7SEL |= 0x0C;
#endif
// Use the REFO oscillator as the FLL reference, and also for ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
// Start the FLL, which will drive MCLK (not the crystal)
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768);
}
else
{
// Enable XT1 pins
#if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x10;
#endif
// Use the REFO oscillator as the FLL reference, and also for ACLK
UCSCTL3 = SELREF__REFOCLK;
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
// Start the FLL, which will drive MCLK (not the crystal)
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK)
}
}
VOID Init_Clock(VOID)
{
# if defined (__MSP430F563x_F663x)
while(BAKCTL & LOCKIO) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKIO); // enable XT1 pins
// Workaround for USB7
UCSCTL6 &= ~XT1OFF;
# endif
//Initialization of clock module
if (USB_PLL_XT == 2)
{
# if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x0C; // enable XT2 pins for F5529
# elif defined (__MSP430F563x_F663x)
P7SEL |= 0x0C;
# endif
// use REFO for FLL and ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK)
XT2_Start(XT2DRIVE_3);
}
else
{
# if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x10; // enable XT1 pins
# endif
UCSCTL3 = SELREF__REFOCLK; // run FLL mit REF_O clock
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK); // set ACLK = REFO
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK)
XT1_Start(XT1DRIVE_3);
}
// SFRIE1 |= OFIFG; // Enable OscFault ISR
}
/**
* Initializes FLL of the UCS and wait till settled
*
* \param fsystem required system frequency (MCLK) in kHz
* \param ratio ratio between MCLK and FLLREFCLK
*/
void Init_FLL_Settle(uint16_t fsystem, uint16_t ratio)
{
volatile uint16_t x = ratio * 32;
// save actual state of FLL loop control
uint16_t globalInterruptState = __get_SR_register() & SCG0;
__bic_SR_register(SCG0); // Enable FLL loop control
Init_FLL(fsystem, ratio);
while(x--)
{
__delay_cycles(30);
}
__bis_SR_register(globalInterruptState); // restore previous state
}
