/*
** This function configures the AINTC to receive EDMA3 interrupts.
*/
static void EDMA3AINTCConfigure(void)
{
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Registering EDMA3 Channel Controller transfer completion interrupt. */
IntRegister(EDMA_COMPLTN_INT_NUM, Edma3CompletionIsr);
/* Setting the priority for EDMA3CC completion interrupt in AINTC. */
IntPrioritySet(EDMA_COMPLTN_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Registering EDMA3 Channel Controller Error Interrupt. */
IntRegister(EDMA_ERROR_INT_NUM, Edma3CCErrorIsr);
/* Setting the priority for EDMA3CC Error interrupt in AINTC. */
IntPrioritySet(EDMA_ERROR_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the EDMA3CC completion interrupt in AINTC. */
IntSystemEnable(EDMA_COMPLTN_INT_NUM);
/* Enabling the EDMA3CC Error interrupt in AINTC. */
IntSystemEnable(EDMA_ERROR_INT_NUM);
/* Registering HSMMC Interrupt handler */
IntRegister(MMCSD_INT_NUM, HSMMCSDIsr);
/* Setting the priority for EDMA3CC completion interrupt in AINTC. */
IntPrioritySet(MMCSD_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the HSMMC interrupt in AINTC. */
IntSystemEnable(MMCSD_INT_NUM);
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
}
/*
** configures arm interrupt controller to generate raster interrupt
*/
void SetupIntc(void)
{
#ifdef _TMS320C6X
IntDSPINTCInit();
IntRegister(C674X_MASK_INT4, LCDIsr);
IntEventMap(C674X_MASK_INT4, SYS_INT_LCDC_INT);
IntEnable(C674X_MASK_INT4);
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt.
*/
IntChannelSet(SYS_INT_LCDINT, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
IntSystemEnable(SYS_INT_I2CINT0);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/*
** Main Function.
*/
int main(void)
{
unsigned char choice = 0;
/* Enable the clocks for McSPI0 module.*/
McSPI0ModuleClkConfig();
/* Perform Pin-Muxing for SPI0 Instance.*/
McSPIPinMuxSetup(0);
/* Perform Pin-Muxing for CS0 of SPI0 Instance.*/
McSPI0CSPinMuxSetup(MCSPI_CH_NUM);
/* Initialize the UART utility functions.*/
UARTStdioInit();
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
UARTPuts("Here the McSPI controller on the SOC communicates with ",-1);
UARTPuts("the McSPI Flash.\r\n\r\n",-1);
/* Initialize the EDMA3 instance.*/
EDMA3Initialize();
/* Request EDMA3CC for Tx and Rx channels for SPI0. */
RequestEDMA3Channels();
/* Set up the McSPI instance.*/
McSPISetUp();
/* Enable the SPI Flash for writing to it. */
WriteEnable();
UARTPuts("Do you want to erase a sector of the flash before writing to it ?.", -1);
UARTPuts("\r\nInput y(Y)/n(N) to proceed.\r\n", -1);
choice = UARTGetc();
UARTPutc(choice);
if(('y' == choice) || ('Y' == choice))
{
/* Erasing the specified sector of SPI Flash. */
FlashSectorErase();
}
/* Enable the SPI Flash for writing to it. */
WriteEnable();
/* Write data of 1 page size into a page of Flash.*/
FlashPageProgram();
/* Read data of 1 page size from a page of flash.*/
ReadFromFlash();
/* Verify the data written to and read from Flash are same or not.*/
VerifyData();
while(1);
}
void _EDMAAppRegisterEdma3Interrupts()
{
/* Enable IRQ in CPSR. */
IntMasterIRQEnable();
/* Intialize ARM interrupt controller */
IntAINTCInit();
/* Register Interrupts Here */
/******************** Completion Interrupt ********************************/
/* Registers Edma3ComplHandler0 Isr in Interrupt Vector Table of AINTC. */
IntRegister(SYS_INT_EDMACOMPINT , _EDMAAppEdma3ccComplIsr);
/* Set priority for system interrupt in AINTC */
IntPrioritySet(SYS_INT_EDMACOMPINT, 0u, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the EDMA CC0 system interrupt in AINTC.*/
IntSystemEnable(SYS_INT_EDMACOMPINT);
/********************** CC Error Interrupt ********************************/
/*
** Registers the EDMA3_0 Channel Controller 0 Error Interrupt Isr in the
** Interrupt Vector Table of AINTC.
*/
IntRegister(SYS_INT_EDMAERRINT , _EDMAAppEdma3ccErrIsr);
/* Set priority for system interrupt in AINTC */
IntPrioritySet(SYS_INT_EDMAERRINT, 0u, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the EDMA CCERR system interrupt AINTC.*/
IntSystemEnable(SYS_INT_EDMAERRINT);
}
int main(void)
{
/* Setup the MMU and do necessary MMU configurations. */
MMUConfigAndEnable();
/* Enable all levels of CACHE. */
CacheEnable(CACHE_ALL);
/* Initialize the UART console */
ConsoleUtilsInit();
/* Select the console type based on compile time check */
ConsoleUtilsSetType(CONSOLE_UART);
ConsoleUtilsPrintf("McASP Example Application. ");
ConsoleUtilsPrintf("Please connect headphone/speaker to the LINE OUT");
ConsoleUtilsPrintf(" of the EVM to listen to the audio tone.");
/* Enable the module clock for I2C0 Instance. */
I2C0ModuleClkConfig();
/* Set up the pin mux for I2C0 instance. */
I2CPinMuxSetup(0);
/* Enable the module clock for McASP1 Instance. */
McASP1ModuleClkConfig();
/* Enable pin-mux for McASP1 instance. */
McASP1PinMuxSetup();
/* Enable the EDMA module clocks. */
EDMAModuleClkConfig();
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Enable EDMA Interrupt. */
EDMA3IntSetup();
/* Enable McASP Interrupt. */
McASPIntSetup();
/* Initialize the I2C interface for the codec AIC31 */
I2CCodecIfInit(I2C_INST_BASE, I2C_SLAVE_CODEC_AIC31);
/* Enable the interrupts generation at global level */
IntMasterIRQEnable();
/* Configure the Codec for I2S mode */
AudioCodecInit();
/* Initialize the looping of tone. */
ToneLoopInit();
/* Start playing tone. */
AudioTxActivate();
while(1);
}
/*
** Configures arm/dsp interrupt controller to generate frame interrupt
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
/* Initialize the DSP interrupt controller */
IntDSPINTCInit();
/* Register VPIF ISR to vector table */
IntRegister(C674X_MASK_INT5, VPIFIsr);
/* Map system interrupt to DSP maskable interrupt for VPIF */
IntEventMap(C674X_MASK_INT5, SYS_INT_VPIF_INT);
/* Enable DSP maskable interrupt for VPIF */
IntEnable(C674X_MASK_INT5);
/* Register LCD ISR to vector table */
IntRegister(C674X_MASK_INT6, LCDIsr);
/* Map system interrupt to DSP maskable interrupt for LCD */
IntEventMap(C674X_MASK_INT6, SYS_INT_LCDC_INT);
/* Enable DSP maskable interrupt for LCD */
IntEnable(C674X_MASK_INT6);
/* Enable DSP interrupts */
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_VPIF, VPIFIsr);
/* Set the channel number 2 of AINTC for LCD system interrupt. */
IntChannelSet(SYS_INT_VPIF, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_VPIF);
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt. */
IntChannelSet(SYS_INT_LCDINT, 3);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
void IntEnable(unsigned char status)
{
if((status & 0x80) == 0)
{
IntMasterIRQEnable();
}
}
/**
* This function is used to unlock access to critical sections when lwipopt.h
* defines SYS_LIGHTWEIGHT_PROT. It enables interrupts if the value of the lev
* parameter indicates that they were enabled when the matching call to
* sys_arch_protect() was made.
*
* @param lev is the interrupt level when the matching protect function was
* called
*/
void
sys_arch_unprotect(sys_prot_t lev)
{
/* Only turn interrupts back on if they were originally on when the matching
sys_arch_protect() call was made. */
if((lev & 0x80) == 0) {
IntMasterIRQEnable();
}
}
static void USBInterruptEnable(void)
{
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
/* Configuring AINTC to receive USB interrupts. */
USB0AINTCConfigure();
CPDMAAINTCConfigure();
}
static void UartInterruptEnable(void)
{
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
/* Configuring AINTC to receive UART0 interrupts. */
UART0AINTCConfigure();
/* Enabling the specified UART interrupts. */
UARTIntEnable(SOC_UART_0_REGS, (UART_INT_LINE_STAT | UART_INT_THR |UART_INT_RHR_CTI));
}
int main(void)
{
MMUConfigAndEnable();
CacheEnable(CACHE_ALL);
IntMasterIRQEnable();
IntAINTCInit();
/* Initialize console for communication with the Host Machine */
ConsoleUtilsInit();
//
//Delay timer setup
//
DelayTimerSetup();
/* Select the console type based on compile time check */
ConsoleUtilsSetType(CONSOLE_UART);
ConsoleUtilsPrintf("LCDC Controller\r\n");
LCDAINTCConfigure();
LCDBackLightEnable();
SetUpLCD();
/* Configuring the base ceiling */
RasterDMAFBConfig(LCDC_INSTANCE,
(unsigned int)curr_image,
(unsigned int)curr_image + sizeof(image1) - 2,
0);
RasterDMAFBConfig(LCDC_INSTANCE,
(unsigned int)curr_image,
(unsigned int)curr_image + sizeof(image1) - 2,
1);
/* Enable End of frame0/frame1 interrupt */
RasterIntEnable(LCDC_INSTANCE, RASTER_END_OF_FRAME0_INT |
RASTER_END_OF_FRAME1_INT);
/* Enable raster */
RasterEnable(LCDC_INSTANCE);
while(1) {
if (curr_image == image1) {
curr_image = image2;
} else {
curr_image = image1;
}
delay(5000);
}
}
static void USBInterruptEnable(int usbInstance)
{
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Configuring AINTC to receive UART0 interrupts. */
USBAINTCConfigure(usbInstance);
LCDAINTCConfigure();
}
static void SetupIntc(void)
{
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
IntRegister(SYS_INT_ADC_TSC_GENINT, ADCIsr);
IntPrioritySet(SYS_INT_ADC_TSC_GENINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_ADC_TSC_GENINT);
}
static void SetupAINTCInt(void)
{
/*Initialize the ARM Interrupt Controller(AINTC). */
IntAINTCInit();
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
}
static void USBInterruptEnable(void)
{
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Configuring AINTC to receive USB0 interrupts. */
USB0AINTCConfigure();
/*Configuring AINTC to receive LCD interrupts. */
LCDAINTCConfigure();
}
/**
* \brief Initialize the AINTC by enabling normal interrupts (IRQ) and fast interrupts (FIQ) on all required levels
*
* \return none
**/
void interrupt_init(void) {
/* Initialize AINTC - this should only be done once per application */
IntAINTCInit();
/* Enable IRQ for ARM (in CPSR)*/
IntMasterIRQEnable();
/* Enable AINTC interrupts in GER */
IntGlobalEnable();
/* Enable IRQ in AINTC */
IntIRQEnable();
IntMasterFIQEnable();
IntFIQEnable();
}
/*
** configures arm interrupt controller to generate PWM interrupts
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
// Initialize the DSP interrupt controller
IntDSPINTCInit();
// Register the ISRs to the vector table
IntRegister(C674X_MASK_INT4, PWMEventIsr);
IntRegister(C674X_MASK_INT5, PWMTZIsr);
// Map system events to the DSP maskable interrupts
IntEventMap(C674X_MASK_INT4, SYS_INT_EHRPWM1);
IntEventMap(C674X_MASK_INT5, SYS_INT_EHRPWM1TZ);
// Enable the DSP maskable interrupts
IntEnable(C674X_MASK_INT4);
IntEnable(C674X_MASK_INT5);
// Enable DSP interrupts globally
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
IntSystemStatusClear(SYS_INT_EHRPWM1);
EHRPWMETIntClear(SOC_EHRPWM_1_REGS);
/************************PWM1****************************************/
IntRegister(SYS_INT_EHRPWM1, PWMEventIsr);
IntChannelSet(SYS_INT_EHRPWM1, 2);
IntSystemEnable(SYS_INT_EHRPWM1);
/********************************************************************/
IntRegister(SYS_INT_EHRPWM1TZ, PWMTZIsr);
IntChannelSet(SYS_INT_EHRPWM1TZ, 2);
IntSystemEnable(SYS_INT_EHRPWM1TZ);
/********************************************************************/
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/******************************************************************************
** FUNCTION DEFINITIONS
*******************************************************************************/
int main(void)
{
/* This function will enable clocks for the DMTimer2 instance */
DMTimer2ModuleClkConfig();
/* Initialize the UART console */
ConsoleUtilsInit();
/* Select the console type based on compile time check */
ConsoleUtilsSetType(CONSOLE_UART);
/* Enable IRQ in CPSR */
IntMasterIRQEnable();
/* Register DMTimer2 interrupts on to AINTC */
DMTimerAintcConfigure();
/* Perform the necessary configurations for DMTimer */
DMTimerSetUp();
/* Enable the DMTimer interrupts */
DMTimerIntEnable(SOC_DMTIMER_2_REGS, DMTIMER_INT_OVF_EN_FLAG);
ConsoleUtilsPrintf("Tencounter: ");
/* Start the DMTimer */
DMTimerEnable(SOC_DMTIMER_2_REGS);
while(cntValue)
{
if(flagIsr == 1)
{
ConsoleUtilsPrintf("\b%d",(cntValue - 1));
cntValue--;
flagIsr = 0;
}
}
/* Stop the DMTimer */
DMTimerDisable(SOC_DMTIMER_2_REGS);
PRINT_STATUS(S_PASS);
/* Halt the program */
while(1);
}
/*
** Set up the ARM Interrupt Controller for generating timer interrupt
*/
static void TimerIntrSetUp(void)
{
#ifdef _TMS320C6X
/* Initialize the DSPINTC */
IntDSPINTCInit();
/* Register the Timer ISR */
IntRegister(C674X_MASK_INT4, TimerIsr);
/* Map Timer interrupts to DSP maskable interrupt */
IntEventMap(C674X_MASK_INT4, SYS_INT_T64P2_TINTALL);
/* Enable DSP interrupt in DSPINTC */
IntEnable(C674X_MASK_INT4);
/* Enable DSP interrupts */
IntGlobalEnable();
#else
/* Initialize AINTC and register timer interrupt */
IntAINTCInit();
/* Register the Timer ISR */
IntRegister(SYS_INT_TIMR2_ALL, TimerIsr);
/* Set the channel number for Timer interrupt, it will map to IRQ */
IntChannelSet(SYS_INT_TIMR2_ALL, 2);
/* Enable IRQ for ARM (in CPSR)*/
IntMasterIRQEnable();
/* Enable AINTC interrupts in GER */
IntGlobalEnable();
/* Enable IRQ in AINTC */
IntIRQEnable();
/* Enable timer interrupts in AINTC */
IntSystemEnable(SYS_INT_TIMR2_ALL);
#endif
}
static void SetupInt(void)
{
#ifdef _TMS320C6X
// Initialize the DSP INTC
IntDSPINTCInit();
// Enable DSP interrupts globally
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller(AINTC). */
IntAINTCInit();
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/*
** configures arm interrupt controller to generate raster interrupt
*/
static void SetupIntc(void)
{
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt.
*/
IntChannelSet(SYS_INT_LCDINT, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
}
/*#####################################################*/
bool board_init()
{
//MMUConfigAndEnable();
CacheEnable(CACHE_ICACHE);
CacheEnable(CACHE_ALL);
L3L4_init();
/* Enable IRQ for ARM (in CPSR)*/
IntMasterIRQEnable();
IntAINTCInit();
timer_init();
/*-----------------------------------------------------*/
/* Set up the Uart 0 like debug interface with RxBuff = 256, TxBuff = 256, 115200b/s*/
DebugCom = new_(new_uart);
DebugCom->TxPin = Uart0_Tx_PinMux_E16;
DebugCom->RxPin = Uart0_Rx_PinMux_E15;
DebugCom->BaudRate = 115200;
DebugCom->RxBuffSize = 256;
DebugCom->TxBuffSize = 256;
DebugCom->rxFifoTrigLevel = 1;
DebugCom->txFifoTrigLevel = 1;
DebugCom->UartNr = 0;
uart_open(DebugCom);
/*-----------------------------------------------------*/
/* LED[0] = gpio_assign(1, 21, GPIO_DIR_OUTPUT, false);
LED[1] = gpio_assign(1, 22, GPIO_DIR_OUTPUT, false);
LED[2] = gpio_assign(1, 23, GPIO_DIR_OUTPUT, false);
LED[3] = gpio_assign(1, 24, GPIO_DIR_OUTPUT, false);*/
/*-----------------------------------------------------*/
/* Display board message*/
#if defined(BOARD_MESSAGE)
UARTprintf(DebugCom, "Use %s Board.\n\r", BOARD_MESSAGE);
#endif
/*-----------------------------------------------------*/
/* Set up the Twi 0 to communicate with PMIC and the Onboard serial EEprom memory */
//UARTPuts(DebugCom, "Setup TWI 0 with RxBuff = 258, TxBuff = 258....." , -1);
TWI = new_(new_twi);
TWI->SdaPin = Twi0_Sda_PinMux_C17;
TWI->SclPin = Twi0_Scl_PinMux_C16;
TWI->BaudRate = 100000;
TWI->TwiNr = 0;
TWI->Priority = 0;
TWI->WithInterrupt = TRUE;
TWI->RxBuffSize = 258;
TWI->TxBuffSize = 258;
twi_open(TWI);
//UARTPuts(DebugCom, "OK.\n\r" , -1);
/*-----------------------------------------------------*/
//if(!detect_if_is_beaglebone()) return false;
/*-----------------------------------------------------*/
//beaglebone_detect_extension_boards();
/*-----------------------------------------------------*/
//UARTPuts(DebugCom, "Init MMCSD0 Host.......", -1);
mmcsd_init(&sdCtrl, 0, 6, NULL /*LED[0]*/);
//UARTPuts(DebugCom, "OK.\n\r", -1);
/*-----------------------------------------------------*/
//UARTPuts(DebugCom, "Init USBMSC1 Host.......", -1);
//usb_host_init(1, LED2);
//UARTPuts(DebugCom, "OK.\n\r", -1);
/*-----------------------------------------------------*/
return true;
}
/*
** Enter the desired power save mode
*/
void PowerSaveModeEnter(deepSleepData dsData, unsigned int slpMode)
{
unsigned int i = 0;
unsigned int index = 0;
unsigned int noOfElements = sizeof(pmModuleList)/sizeof(pmModuleList[0]);
PeripheralsContextSave(slpMode, wakeSource);
PeripheralsHalt();
dsData.dsDataBits.wakeSources = wakeSource;
/* Configure CMD_ID and other parameters which are to be
** communicated with CM3 */
configIPCRegs(dsData);
syncCm3();
if(SLEEP_STAND_BY_MODE == slpMode)
{
/* Enable wake source interupt */
enableStandbyWakeSrc(dsData.dsDataBits.wakeSources);
}
else
{
/* Enable wake source */
enableWakeSource(dsData.dsDataBits.wakeSources);
}
/* Include MPU Clock in the disable list */
for(index = 0; index < noOfElements; index++)
{
if(CLK_MPU_CLK == pmModuleList[index].module)
{
pmModuleList[index].select = TRUE;
}
}
/* Disable clock */
while(true != disableSelModuleClock(pmModuleList,
(sizeof(pmModuleList)/sizeof(pmModuleList[0]))));
/* Configure for minimum OPP supported by SoC */
ConfigMinimumOPP();
disableModuleClock(CLK_I2C0, TRUE);
/* Disable IRQ */
IntMasterIRQDisable();
if(SLEEP_MODE_DS0 == slpMode)
{
PowerDownConfig();
}
/*
** Save A8 context
** WFI
** Restore A8 context
*/
saveRestoreContext(slpMode, deviceVersion);
/* Enable Timer3 for DS2 */
enableModuleClock(CLK_TIMER3);
/* Enable IRQ */
IntMasterIRQEnable();
enableModuleClock(CLK_I2C0);
/* Restore OPP configuration */
DemoOppChange(mpuOpp);
/* Exclude MPU Clock from the disable list */
for(index = 0; index < noOfElements; index++)
{
if(CLK_MPU_CLK == pmModuleList[index].module)
{
pmModuleList[index].select = FALSE;
}
}
/* Device clock enable */
enableSelModuleClock(pmModuleList,
(sizeof(pmModuleList)/sizeof(pmModuleList[0])));
EDMAModuleClkConfig();
/* disable wake source */
if(SLEEP_STAND_BY_MODE == slpMode)
{
disableStandbyWakeSrc(dsData.dsDataBits.wakeSources);
}
else
{
disableWakeSource(dsData.dsDataBits.wakeSources);
}
PeripheralsContextRestore(slpMode, dsData.dsDataBits.wakeSources);
PeripheralsResume();
/*
** Print string name of the sleep mode.
*/
ConsoleUtilsPrintf("\n\r%s", sleepModeStrMap[slpMode].str);
/* Check the DS status */
if(PM_CMD_FAIL == (readCmdStatus() & (PM_CMD_FAIL)))
{
ConsoleUtilsPrintf(" attempt failed");
}
else
{
ConsoleUtilsPrintf(" attempt passed");
}
/* Reset CM3 State Machine */
configIPCRegs(dsDataM3reset);
syncCm3();
if(slpMode & SLEEP_MODE_DS1)
{
/* delay to reduce the frequency of sleep/wake cycle for DS1 */
delay(500);
}
for(i = 0; i < 2; i++)
{
x_data[i] = 0;
y_data[i] = 0;
}
/* Reset sleep trigger flag */
IsTSPress = 0;
}
/*
** Main function. The application starts here.
*/
int main(void)
{
unsigned char rxByte;
unsigned int value = (unsigned int)E_FAIL;
#ifdef __TMS470__
/* Relocate the required section to internal RAM */
memcpy((void *)(&relocstart), (const void *)(&iram_start),
(unsigned int)(&iram_size));
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma section = "CodeRelocOverlay"
#pragma section = "DataRelocOverlay"
#pragma section = "DataOverlayBlk"
#pragma section = "CodeOverlayBlk"
char* srcAddr = (__section_begin("CodeRelocOverlay"));
char* endAddr = (__section_end("DataRelocOverlay"));
memcpy((void *)(__section_begin("CodeRelocOverlay")),
(const void *)(__section_begin("CodeOverlayBlk")),
endAddr - srcAddr);
#else
memcpy((void *)&(relocstart), (const void *)&(iram_start),
(unsigned int)(((&(relocend)) -
(&(relocstart))) * (sizeof(unsigned int))));
#endif
MMUConfigAndEnable();
/* Enable Instruction Cache */
CacheEnable(CACHE_ALL);
PeripheralsSetUp();
/* Initialize the ARM Interrupt Controller */
IntAINTCInit();
/* Register the ISRs */
Timer2IntRegister();
Timer4IntRegister();
EnetIntRegister();
RtcIntRegister();
CM3IntRegister();
HSMMCSDIntRegister();
IntRegister(127, dummyIsr);
IntMasterIRQEnable();
pageIndex = 0;
prevAction = 0;
/* Enable system interrupts */
IntSystemEnable(SYS_INT_RTCINT);
IntPrioritySet(SYS_INT_RTCINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_3PGSWTXINT0);
IntPrioritySet(SYS_INT_3PGSWTXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_3PGSWRXINT0);
IntPrioritySet(SYS_INT_3PGSWRXINT0, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_TINT2);
IntPrioritySet(SYS_INT_TINT2, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_TINT4);
IntPrioritySet(SYS_INT_TINT4, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_MMCSD0INT);
IntPrioritySet(SYS_INT_MMCSD0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_EDMACOMPINT);
IntPrioritySet(SYS_INT_EDMACOMPINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntPrioritySet(SYS_INT_M3_TXEV, 0, AINTC_HOSTINT_ROUTE_IRQ );
IntSystemEnable(SYS_INT_M3_TXEV);
IntSystemEnable(127);
IntPrioritySet(127, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_UART0INT);
IntPrioritySet(SYS_INT_UART0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_UART0INT, uartIsr);
/* GPIO interrupts */
IntSystemEnable(SYS_INT_GPIOINT0A);
IntPrioritySet(SYS_INT_GPIOINT0A, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_GPIOINT0A, gpioIsr);
IntSystemEnable(SYS_INT_GPIOINT0B);
IntPrioritySet(SYS_INT_GPIOINT0B, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_GPIOINT0B, gpioIsr);
BoardInfoInit();
deviceVersion = DeviceVersionGet();
CM3EventsClear();
CM3LoadAndRun();
waitForM3Txevent();
/* Initialize console for communication with the Host Machine */
ConsoleUtilsInit();
/*
** Select the console type based on compile time check
** Note: This example is not fully complaint to semihosting. It is
** recommended to use Uart console interface only.
*/
ConsoleUtilsSetType(CONSOLE_UART);
/* Print Board and SoC information on console */
ConsoleUtilsPrintf("\n\r Board Name : %s", BoardNameGet());
ConsoleUtilsPrintf("\n\r Board Version : %s", BoardVersionGet());
ConsoleUtilsPrintf("\n\r SoC Version : %d", deviceVersion);
/* On CM3 init firmware version is loaded onto the IPC Message Reg */
ConsoleUtilsPrintf("\n CM3 Firmware Version: %d", readCM3FWVersion());
I2CIntRegister(I2C_0);
IntPrioritySet(SYS_INT_I2C0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_I2C0INT);
I2CInit(I2C_0);
IntSystemEnable(SYS_INT_TINT1_1MS);
IntPrioritySet(SYS_INT_TINT1_1MS, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntRegister(SYS_INT_TINT1_1MS,clearTimerInt);
configVddOpVoltage();
RtcInit();
HSMMCSDContolInit();
DelayTimerSetup();
initializeTimer1();
ConsoleUtilsPrintf("\r\n After intializing timer");
Timer2Config();
Timer4Config();
LedIfConfig();
MailBoxInit();
Timer2IntEnable();
Timer4IntEnable();
RtcSecIntEnable();
Timer4Start();
while(FALSE == tmr4Flag);
tmr4Flag = FALSE;
Timer4Stop();
ConsoleUtilsPrintf("\n\r Configuring for maximum OPP");
mpuOpp = ConfigMaximumOPP();
mpuFreq = FrequencyGet(mpuOpp);
mpuVdd1 = VddVoltageGet(mpuOpp);
PrintConfigDVFS();
/* Create menu page */
pageIndex = MENU_IDX_MAIN;
ActionEnetInit();
/*
** Loop for ever. Necessary actions shall be taken
** after detecting the click.
*/
while(1)
{
/*
** Check for any any activity on Uart Console and process it.
*/
if (true == UARTCharsAvail(SOC_UART_0_REGS))
{
/* Receiving bytes from the host machine through serial console. */
rxByte = UARTGetc();
/*
** Checking if the entered character is a carriage return.
** Pressing the 'Enter' key on the keyboard executes a
** carriage return on the serial console.
*/
if('\r' == rxByte)
{
ConsoleUtilsPrintf("\n");
UartAction(value);
value = (unsigned int)E_FAIL;
rxByte = 0;
}
/*
** Checking if the character entered is one among the decimal
** number set 0,1,2,3,....9
*/
if(('0' <= rxByte) && (rxByte <= '9'))
{
ConsoleUtilsPrintf("%c", rxByte);
if((unsigned int)E_FAIL == value)
{
value = 0;
}
value = value*10 + (rxByte - 0x30);
}
}
/*
** Check if click is detected
*/
if(clickIdx != 0)
{
/*
** Take the Action for click
*/
ClickAction();
clickIdx = 0;
}
/*
** Check if the Timer Expired
*/
if(TRUE == tmrFlag)
{
/* Toggle the LED state */
LedToggle();
tmrFlag = FALSE;
}
/*
** Check if RTC Time is set
*/
if(TRUE == rtcSetFlag)
{
if(TRUE == rtcSecUpdate)
{
rtcSecUpdate = FALSE;
RtcTimeCalDisplay();
ConsoleUtilsPrintf(" --- Selected: ");
}
}
if(TRUE == tmr4Flag)
{
tmr4Flag = FALSE;
/* Make sure that interrupts are disabled and no lwIP functions
are executed while calling an lwIP exported API */
IntMasterIRQDisable();
etharp_tmr();
IntMasterIRQEnable();
}
}
}
int
func_rmpi(unsigned int rmpi_dof)
{
if (g_flags.perf == 1)
{
bbmc_perf_init();
}
bbmc_cisr_init(&g_isr_state);
sysconfig_contrl_stop_init();
sysconfig_qei_data_init(TIMER_RMPI, rmpi_dof);
UARTPuts("\r\n\r\nEXECUTING..\r\n", -1);
sysconfig_poslim_enable(rmpi_dof);
sysconfig_killswitch_enable();
sysconfig_pwm_enable(rmpi_dof);
sysconfig_timer_enable(TIMER_RMPI);
IntMasterIRQEnable();
while(!g_isr_state.termination_flag)
{
;
}
sysconfig_timer_disable(TIMER_RMPI);
sysconfig_pwm_disable(rmpi_dof);
sysconfig_killswitch_disable();
sysconfig_poslim_disable(rmpi_dof);
UARTPuts("\r\nEOR\r\n", -1);
if (g_flags.perf == 1)
{
bbmc_perf_print();
}
if (g_flags.datalog == 1)
{
char buff[8];
int test = util_checkpoint_yn("\r\nPrint datalog? [Y/n]: ", buff);
if (test == 1)
{
int range[4];
range[0] = 0;
range[1] = g_isr_state.iteration_counter;
range[2] = 0;
range[3] = DATALOG_STATIC_DATASIZE;
datalog_s_print(rmpi_log, range);
}
}
return (RETURN_RMPI + g_flags.isr_return);
}
/*
** Main function.
*/
int main(void)
{
unsigned int numByteChunks = 0;
unsigned char *pBuffer = NULL;
unsigned int remainBytes = 0;
/* Configure and enable the MMU. */
MMUConfigAndEnable();
/* Enable all levels of Cache. */
CacheEnable(CACHE_ALL);
/* Configuring the system clocks for EDMA. */
EDMAModuleClkConfig();
/* Configuring the system clocks for UART0 instance. */
UART0ModuleClkConfig();
/* Performing Pin Multiplexing for UART0 instance. */
UARTPinMuxSetup(0);
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Initializing the EDMA. */
EDMA3Initialize();
/* Initializing the UART0 instance for use. */
UARTInitialize();
/* Select the console type based on compile time check */
ConsoleUtilsSetType(CONSOLE_UART);
/*
** Configuring the EDMA.
*/
/* Request DMA Channel and TCC for UART Transmit*/
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_TX_CHA_NUM, EDMA3_UART_TX_CHA_NUM,
EVT_QUEUE_NUM);
/* Registering Callback Function for TX*/
cb_Fxn[EDMA3_UART_TX_CHA_NUM] = &callback;
/* Request DMA Channel and TCC for UART Receive */
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_RX_CHA_NUM, EDMA3_UART_RX_CHA_NUM,
EVT_QUEUE_NUM);
/* Registering Callback Function for RX*/
cb_Fxn[EDMA3_UART_RX_CHA_NUM] = &callback;
/******************** Transmission of a string **************************/
numByteChunks = (sizeof(welcome) - 1) / txBytesPerEvent;
remainBytes = (sizeof(welcome) - 1) % txBytesPerEvent;
/* Configuring EDMA PaRAM sets to transmit data. */
UARTTxEDMAPaRAMSetConfig(welcome,
numByteChunks * txBytesPerEvent,
EDMA3_UART_TX_CHA_NUM,
EDMA3CC_OPT(DUMMY_CH_NUM),
EDMA3_UART_TX_CHA_NUM);
/* Configuring the PaRAM set for Dummy Transfer. */
TxDummyPaRAMConfEnable();
/* Enable EDMA Transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM,
EDMA3_TRIG_MODE_EVENT);
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/* Remaining bytes are transferred through polling method. */
if(0 != remainBytes)
{
pBuffer = welcome + (sizeof(welcome) - 1) - remainBytes;
UARTPuts((char*)pBuffer, remainBytes);
}
/******************** Transmission of a string **************************/
numByteChunks = (sizeof(intent) - 1) / txBytesPerEvent;
remainBytes = (sizeof(intent) - 1) % txBytesPerEvent;
/* Enabling DMA Mode 1. */
UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE);
/* Configuring EDMA PaRAM sets to transmit data. */
UARTTxEDMAPaRAMSetConfig(intent,
numByteChunks * txBytesPerEvent,
EDMA3_UART_TX_CHA_NUM,
EDMA3CC_OPT(DUMMY_CH_NUM),
EDMA3_UART_TX_CHA_NUM);
/* Configuring the PaRAM set for Dummy Transfer. */
TxDummyPaRAMConfEnable();
/* Enable EDMA Transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM,
EDMA3_TRIG_MODE_EVENT);
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/* Remaining bytes are transferred through polling method. */
if(0 != remainBytes)
{
pBuffer = intent + (sizeof(intent) - 1) - remainBytes;
UARTPuts((char*)pBuffer, remainBytes);
}
/******************** Transmission of a string **************************/
numByteChunks = (sizeof(enter) - 1) / txBytesPerEvent;
remainBytes = (sizeof(enter) - 1) % txBytesPerEvent;
/* Enabling DMA Mode 1. */
UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE);
/* Configuring EDMA PaRAM sets to transmit data. */
UARTTxEDMAPaRAMSetConfig(enter,
numByteChunks * txBytesPerEvent,
EDMA3_UART_TX_CHA_NUM,
EDMA3CC_OPT(DUMMY_CH_NUM),
EDMA3_UART_TX_CHA_NUM);
/* Configuring the PaRAM set for Dummy Transfer. */
TxDummyPaRAMConfEnable();
/* Enable EDMA Transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM,
EDMA3_TRIG_MODE_EVENT);
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/* Remaining bytes are transferred through polling method. */
if(0 != remainBytes)
{
pBuffer = enter + (sizeof(enter) - 1) - remainBytes;
UARTPuts((char*)pBuffer, remainBytes);
}
/********************* Receiving Data from User *************************/
/* Enabling DMA Mode 1. */
UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE);
/* Configuring the PaRAM set for reception. */
UARTRxEDMAPaRAMSetConfig(rxBuffer,
NUM_RX_BYTES,
EDMA3_UART_RX_CHA_NUM,
0xFFFF,
EDMA3_UART_RX_CHA_NUM);
/* Enable EDMA Transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_RX_CHA_NUM,
EDMA3_TRIG_MODE_EVENT);
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/******************* Echoing received bytes *****************************/
numByteChunks = (NUM_RX_BYTES) / txBytesPerEvent;
remainBytes = (NUM_RX_BYTES) % txBytesPerEvent;
/* Enabling DMA Mode 1. */
UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE);
/* Configuring EDMA PaRAM sets to transmit data. */
UARTTxEDMAPaRAMSetConfig(rxBuffer,
numByteChunks * txBytesPerEvent,
EDMA3_UART_TX_CHA_NUM,
EDMA3CC_OPT(DUMMY_CH_NUM),
EDMA3_UART_TX_CHA_NUM);
/* Configuring the PaRAM set for Dummy Transfer. */
TxDummyPaRAMConfEnable();
/* Enable EDMA Transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_UART_TX_CHA_NUM,
EDMA3_TRIG_MODE_EVENT);
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/* Remaining bytes are transferred through polling method. */
if(0 != remainBytes)
{
pBuffer = rxBuffer + NUM_RX_BYTES - remainBytes;
UARTPuts((char*)pBuffer, remainBytes);
}
/******************* Freeing of allocated channels **********************/
/* Free EDMA3 Channels for TX and RX */
EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT,
EDMA3_UART_TX_CHA_NUM, EVT_QUEUE_NUM);
EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_RX_CHA_NUM, EDMA3_TRIG_MODE_EVENT,
EDMA3_UART_RX_CHA_NUM, EVT_QUEUE_NUM);
/* Support for Automation Testing. */
PRINT_STATUS(S_PASS);
while(1);
}
int main(void)
{
/* Configuring the system clocks for EDMA. */
EDMAModuleClkConfig();
/* Configuring the system clocks for UART0 instance. */
UART0ModuleClkConfig();
/* Performing Pin Multiplexing for UART0 instance. */
UARTPinMuxSetup(0);
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Initializing the EDMA. */
EDMA3Initialize();
/* Initializing the UART0 instance for use. */
UARTInitialize();
/*
** Configuring the EDMA.
*/
/* Request DMA Channel and TCC for UART Transmit*/
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_TX_CHA_NUM, EDMA3_UART_TX_CHA_NUM,
EVT_QUEUE_NUM);
/* Registering Callback Function for TX*/
cb_Fxn[EDMA3_UART_TX_CHA_NUM] = &callback;
/* Request DMA Channel and TCC for UART Receive */
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_RX_CHA_NUM, EDMA3_UART_RX_CHA_NUM,
EVT_QUEUE_NUM);
/* Registering Callback Function for RX*/
cb_Fxn[EDMA3_UART_RX_CHA_NUM] = &callback;
/******************** Transmission of a string **************************/
/* Configuring EDMA PaRAM sets to transmit 'welcome' message. */
UartEDMATxConfTransfer(EDMA3_UART_TX_CHA_NUM,
EDMA3_UART_TX_CHA_NUM,
welcome,
sizeof(welcome) - 1);
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/******************** Transmission of a string **************************/
/* Enabling DMA Mode 1. */
UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE);
/* Configuring EDMA PaRAM sets to transmit 'enter' message. */
UartEDMATxConfTransfer(EDMA3_UART_TX_CHA_NUM,
EDMA3_UART_TX_CHA_NUM,
enter,
sizeof(enter) - 1);
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/********************* Receiving Data from User *************************/
/* Enabling DMA Mode 1. */
UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE);
/* Configuring the PaRAM set for reception. */
UartEDMARxConfTransfer(EDMA3_UART_RX_CHA_NUM,
EDMA3_UART_RX_CHA_NUM,
rxBuffer,
sizeof(rxBuffer));
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/******************* Echoing received bytes *****************************/
/* Enabling DMA Mode 1. */
UARTDMAEnable(UART_INSTANCE_BASE_ADD, UART_DMA_MODE_1_ENABLE);
/* Configuring the PaRAM set to transmit the bytes that were received. */
UartEDMATxConfTransfer(EDMA3_UART_TX_CHA_NUM,
EDMA3_UART_TX_CHA_NUM,
rxBuffer,
sizeof(rxBuffer));
/* Wait for return from callback */
while(0 == clBackFlag);
clBackFlag = 0;
/******************* Freeing of allocated channels **********************/
/* Free EDMA3 Channels for TX and RX */
EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_TX_CHA_NUM, EDMA3_TRIG_MODE_EVENT,
EDMA3_UART_TX_CHA_NUM, EVT_QUEUE_NUM);
EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_UART_RX_CHA_NUM, EDMA3_TRIG_MODE_EVENT,
EDMA3_UART_RX_CHA_NUM, EVT_QUEUE_NUM);
while(1);
}
/*
** The main function. Application starts here.
*/
int main(void)
{
unsigned short parToSend;
unsigned short parToLink;
/* Set up pin mux for I2C module 0 */
I2CPinMuxSetup(0);
McASPPinMuxSetup();
/* Power up the McASP module */
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_MCASP0, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
/* Power up EDMA3CC_0 and EDMA3TC_0 */
PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);
#ifdef _TMS320C6X
// Initialize the DSP interrupt controller
IntDSPINTCInit();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
#endif
/* Initialize the I2C 0 interface for the codec AIC31 */
I2CCodecIfInit(SOC_I2C_0_REGS, INT_CHANNEL_I2C, I2C_SLAVE_CODEC_AIC31);
EDMA3Init(SOC_EDMA30CC_0_REGS, 0);
EDMA3IntSetup();
McASPErrorIntSetup();
#ifdef _TMS320C6X
IntGlobalEnable();
#else
/* Enable the interrupts generation at global level */
IntMasterIRQEnable();
IntGlobalEnable();
IntIRQEnable();
#endif
/*
** Request EDMA channels. Channel 0 is used for reception and
** Channel 1 is used for transmission
*/
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_CHA_MCASP0_TX, EDMA3_CHA_MCASP0_TX, 0);
EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
EDMA3_CHA_MCASP0_RX, EDMA3_CHA_MCASP0_RX, 0);
/* Initialize the DMA parameters */
I2SDMAParamInit();
/* Configure the Codec for I2S mode */
AIC31I2SConfigure();
/* Configure the McASP for I2S */
McASPI2SConfigure();
/* Activate the audio transmission and reception */
I2SDataTxRxActivate();
/*
** Looop forever. if a new buffer is received, the lastFullRxBuf will be
** updated in the rx completion ISR. if it is not the lastSentTxBuf,
** buffer is to be sent. This has to be mapped to proper paRAM set.
*/
while(1)
{
if(lastFullRxBuf != lastSentTxBuf)
{
/*
** Start the transmission from the link paramset. The param set
** 1 will be linked to param set at PAR_TX_START. So do not
** update paRAM set1.
*/
parToSend = PAR_TX_START + (parOffTxToSend % NUM_PAR);
parOffTxToSend = (parOffTxToSend + 1) % NUM_PAR;
parToLink = PAR_TX_START + parOffTxToSend;
lastSentTxBuf = (lastSentTxBuf + 1) % NUM_BUF;
ByteBuftoFloatBuf(rxBufPtr[lastFullRxBuf]);
/* Copy the buffer */
memcpy((void *)txBufPtr[lastSentTxBuf],
(void *)rxBufPtr[lastFullRxBuf],
AUDIO_BUF_SIZE);
/*
** Send the buffer by setting the DMA params accordingly.
** Here the buffer to send and number of samples are passed as
** parameters. This is important, if only transmit section
** is to be used.
*/
BufferTxDMAActivate(lastSentTxBuf, NUM_SAMPLES_PER_AUDIO_BUF,
(unsigned short)parToSend,
(unsigned short)parToLink);
}
}
}
/******************************************************************************
** INTERNAL FUNCTION DEFINITIONS
******************************************************************************/
int main(void)
{
volatile unsigned int count = 0x0FFFu;
unsigned int retVal = FALSE;
unsigned char choice = 0;
/* Enable the clocks for McSPI0 module.*/
McSPI0ModuleClkConfig();
/* Perform Pin-Muxing for SPI0 Instance */
McSPIPinMuxSetup(0);
/* Perform Pin-Muxing for CS0 of SPI0 Instance */
McSPI0CSPinMuxSetup(chNum);
/* Initialize the UART utility functions */
UARTStdioInit();
UARTPuts("Here the McSPI controller on the SoC communicates with", -1);
UARTPuts(" the SPI Flash.\r\n\r\n", -1);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Map McSPI Interrupts to AINTC */
McSPI0AintcConfigure();
/* Do the necessary set up configurations for McSPI.*/
McSPISetUp();
/* Pass the write enable command to flash.*/
WriteEnable();
/* Wait until write enable command is successfully written to flash.*/
while(FALSE == retVal)
{
retVal = IsWriteSuccess();
}
retVal = FALSE;
UARTPuts("Do you want to erase a sector of the flash before ", -1);
UARTPuts("writing to it ?.", -1);
UARTPuts("\r\nInput y(Y)/n(N) to proceed.\r\n", -1);
choice = UARTGetc();
UARTPutc(choice);
if(('Y' == choice) || ('y' == choice))
{
/* Erase a sector of flash.*/
SectorErase();
}
/* Pass the write enable command to flash.*/
WriteEnable();
/* Wait until write enable command is successfully written to flash.*/
while(FALSE == retVal)
{
retVal = IsWriteSuccess();
}
/* Write data of 1 page size to flash.*/
WriteToFlash();
while(count--);
count = 0x0FFFu;
/* Read data of 1 page size from flash.*/
ReadFromFlash();
while(count--);
/* Verify the data written to and read from flash are same or not.*/
VerifyData();
while(1);
}
void configEMIFOPP100(void)
{
/* Disable interrupts */
IntMasterIRQDisable();
IntMasterFIQDisable();
/* DDR2 in SR */
HWREG(SOC_EMIF_0_REGS + EMIF_PWR_MGMT_CTRL) |=
((EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SELFREFRESH <<
EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SHIFT) & EMIF_PWR_MGMT_CTRL_REG_LP_MODE);
/* Give a delay */
//for(loopIdx = 0;(loopIdx < PM_DELAY_COUNT);loopIdx++) {}
/* PLL Configuration */
/* MN bypass */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) &
(~CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN)) |
CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN_DPLL_MN_BYP_MODE;
while(((HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_IDLEST_DPLL_DDR)) &
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_MN_BYPASS )!=
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_MN_BYPASS);
/* M & N */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKSEL_DPLL_DDR) =
(PM_OPP100_DDR_M << CM_WKUP_CM_CLKSEL_DPLL_DDR_DPLL_MULT_SHIFT) |
(PM_OPP100_DDR_N);
/* M2 */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_DIV_M2_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_DIV_M2_DPLL_DDR) &
(~CM_WKUP_CM_DIV_M2_DPLL_DDR_DPLL_CLKOUT_DIV)) | (PM_OPP100_DDR_M2);
/* PLL Relock */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) =
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_CLKMODE_DPLL_DDR) &
(~CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN)) |
CM_WKUP_CM_CLKMODE_DPLL_DDR_DPLL_EN_DPLL_LOCK_MODE;
while(((HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_IDLEST_DPLL_DDR)) &
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_DPLL_CLK )!=
CM_WKUP_CM_IDLEST_DPLL_DDR_ST_DPLL_CLK_DPLL_LOCKED);
/* EMIF PRCM */
/* Enable EMIF4DC Firewall clocks*/
HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_FW_CLKCTRL) =
(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_FW_CLKCTRL) &
CM_PER_EMIF_FW_CLKCTRL_MODULEMODE) | CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_ENABLE;
/* Enable EMIF4DC clocks*/
HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) =
(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) & (~CM_PER_EMIF_CLKCTRL_MODULEMODE)) |
CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE;
/* Poll for module is functional */
while(HWREG(SOC_CM_PER_REGS + CM_PER_EMIF_CLKCTRL) !=
CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE);
/*CMD REG PHY*/
HWREG(CMD0_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD0_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD0_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD0_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD0_REG_PHY_INVERT_CLKOUT_0) = 0;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD1_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD1_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD1_REG_PHY_INVERT_CLKOUT_0) = 0;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_RATIO_0) = DDR2_REG_PHY_CTRL_SLAVE_RATIO;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_FORCE_0) = 0;
HWREG(CMD2_REG_PHY_CTRL_SLAVE_DELAY_0) = 0;
HWREG(CMD2_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(CMD2_REG_PHY_INVERT_CLKOUT_0) = 0;
/*DATA0 and DATA1 PHY config*/
HWREG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0) = (((DDR2_PHY_RD_DQS_SLAVE_RATIO<<30)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<20)|
(DDR2_PHY_RD_DQS_SLAVE_RATIO <<10)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_1) = DDR2_PHY_RD_DQS_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_WRLVL_INIT_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_WRLVL_INIT_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) = 0;
HWREG(DATA0_REG_PHY_GATELVL_INIT_RATIO_1) = 0;
HWREG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0)= (((DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<30)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<10)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_1)= DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0)= (((DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<30)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<10)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<0)));
HWREG(DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_1)= DDR2_REG_PHY_WR_DATA_SLAVE_RATIO>>2;
HWREG(DATA0_REG_PHY_DLL_LOCK_DIFF_0) = 0;
HWREG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0) = (((DDR2_PHY_RD_DQS_SLAVE_RATIO<<30)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<20)|
(DDR2_PHY_RD_DQS_SLAVE_RATIO <<10)|(DDR2_PHY_RD_DQS_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_1) = DDR2_PHY_RD_DQS_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_WRLVL_INIT_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_WRLVL_INIT_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_GATELVL_INIT_RATIO_0) = 0;
HWREG(DATA1_REG_PHY_GATELVL_INIT_RATIO_1) = 0;
HWREG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)= (((DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<30)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<10)|(DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_1)= DDR2_REG_PHY_FIFO_WE_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0)= (((DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<30)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<20)|
(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<10)|(DDR2_REG_PHY_WR_DATA_SLAVE_RATIO<<0)));
HWREG(DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_1)= DDR2_REG_PHY_WR_DATA_SLAVE_RATIO>>2;
HWREG(DATA1_REG_PHY_DLL_LOCK_DIFF_0) = 0;
/* IO configuration*/
//IO to work for mDDR
//HWREG(SOC_CONTROL_REGS + CONTROL_DDR_IO_CTRL) |= 0x10000000;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(0)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(1)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CMD_IOCTRL(2)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_DATA_IOCTRL(0)) |= PM_DDR_IO_CONTROL;
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_DATA_IOCTRL(1)) |= PM_DDR_IO_CONTROL;
//CKE controlled by EMIF/DDR_PHY
HWREG(SOC_CONTROL_REGS + CONTROL_DDR_CKE_CTRL) |= 0x00000001;
/*EMIF Timings*/
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_1) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_1_SHDW) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_DDR_PHY_CTRL_2) = OPP100_DDR2_READ_LATENCY;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_1) = OPP100_DDR2_SDRAM_TIMING1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_1_SHDW) = OPP100_DDR2_SDRAM_TIMING1;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_2) = OPP100_DDR2_SDRAM_TIMING2;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_2_SHDW) = OPP100_DDR2_SDRAM_TIMING2;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_3) = OPP100_DDR2_SDRAM_TIMING3;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_TIM_3_SHDW) = OPP100_DDR2_SDRAM_TIMING3;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL) = OPP100_DDR2_REF_CTRL;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_REF_CTRL_SHDW) = OPP100_DDR2_REF_CTRL;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_CONFIG) = OPP100_DDR2_SDRAM_CONFIG;
HWREG(SOC_EMIF_0_REGS + EMIF_SDRAM_CONFIG_2) = OPP100_DDR2_SDRAM_CONFIG;
/* DDR out of SR */
HWREG(SOC_EMIF_0_REGS + EMIF_PWR_MGMT_CTRL) &=
~((EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SELFREFRESH <<
EMIF_PWR_MGMT_CTRL_REG_LP_MODE_SHIFT) & EMIF_PWR_MGMT_CTRL_REG_LP_MODE);
/* Enable interrupts */
IntMasterFIQEnable();
IntMasterIRQEnable();
}
